Compal La-6847p Pwwaa r10

A
PWWAA
Delhi
LA-6847P REV 1.0 Schematic

Intel Processor(ARD) /PCH(HM55)
2010-10-07 Rev 1.0
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Tuesday, December 28, 2010
Sheet
E
of
52
Compal Confidential
Fan Control
APL5607
Intel Arrandale
Model Name : PWWAA

File Name : LA-6847P
Clock Generator
RTM890N-631-GRT
page 6
page 21
PCIE-Express 16X 2.5GHz
Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2
rPGA-988
Dual Channel
page 5,6,7,8,9,10
VGA (DDR3)
ATI PARK XT S3 64bit with 512MB
BANK 0, 1, 2, 3
page 11,12
1.5V DDRIII 800/1066 MT/s
USB
USB port 0,1
DMI X4
page 13,14,15,16,17,18,19,20
page 32
2.5GHz
RTS5137
USB port 10
2IN1
page 35
USB
Int. Camera
USB port 11
page 21
5V 480MHz
LCD Conn.
page 21
CRT
page 22
USB
USB port 13
page 33
5V 480MHz
PCIeMini Card
WLAN
PCIe 1x
1.5V 2.5GHz(250MB/s)
PCIe port 1
page 33
Intel Ibex Peak

SATA port 1
5V 3GHz(300MB/s)
RTL8105E-GR 10/100M
RJ45
page 34
PCIe port 0
PCIe 1x
page 34
SATA port 4
BGA-951
1.5V 2.5GHz(250MB/s)
PCIeMini Card
WiMax
5V 3GHz(300MB/s)
SATA HDD0
page 32
SATA ODD
page 32
PCI
3
Power/B conn.
page 40
3.3V 33 MHz
LPC BUS
page 23~31
HD Audio
3.3V/1.5V 24MHz
RTC CKT.
HDA Codec
page 23
SPI ROM
page 23
Debug Port
ALC259-GR
ENE KB926 E0
page 39
page 36
page 38
DC/DC Interface CKT.

page 41
Touch Pad
page 40
Power Circuit DC/DC
Int.
MIC CONN
(LVDS CONN)
page 21
EC ROM
Int.KBD
page 39
page 39
Ext.
MIC CONN
page 37
HP CONN
page 37
SPK CONN
page 37
page 42~50
2010/09/05
Issued Date
Compal Secret Data
Deciphered Date
2011/09/05
Title
Size
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
E
of
52
DESIGN CURRENT 0.1A
+3VL
B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9
DESIGN CURRENT 5A
+5VALW
DESIGN CURRENT 4A
+5VS
SUSP
N-CHANNEL
SI4800
D
DESIGN CURRENT 5A
+3VALW
DESIGN CURRENT 2A
+1.8VS
UP6182CQAG
SUSP#
APL5930
SUSP
DESIGN CURRENT 4A
N-CHANNEL
SI4800
+3VS
LCD_ENVDD
P-CHANNEL
AO3413
DESIGN CURRENT 1.5A
+LCD_VDD
VR_ON
DESIGN CURRENT 48A
+CPU_CORE
DESIGN CURRENT 15A
+VGA_CORE
ISL62883HRZ
SUSP#
TPS51218DSCR
VTTP_EN
DESIGN CURRENT 18A
+VTT
APW7138NITRL
SUSP#
DESIGN CURRENT 7A
+1.05VS
RT8209BGQW
SUSP#
DESIGN CURRENT 15A
+1.5V
SUSP
RT8209BGQW
DESIGN CURRENT 2A
N-CHANNEL
+1.5V_CPU
FDS6676AS
SUSP
DESIGN CURRENT 2A
N-CHANNEL
+1.5VS
FDS6676AS
0.75VR_EN#
DESIGN CURRENT 1.5A
+0.75VS
G2992F1U
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
of
52
Voltage Rails
( O MEANS ON
+RTCVCC
X MEANS OFF )
+B
+5VS
+5VL
+5VALW
+3VL
+3VALW
+3VS
+VSB
+1.5VS
power
plane
+1.5V
+VGA_CORE
+CPU_CORE
BTO Option Table
+VTT
Function
+1.05VS
+1.8VS
LAN
description
SLOT1
explain
WLAN/BT
+1.1VS
State
LAN
MINI PCI-E SLOT
+0.75VS
10/100M
BTO
Camera & Mic
Function
Camera & Mic
description
S0
explain
Camera & Mic
S1
BTO
CAM@
S3
Function
description
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery

don't exist
S3 Power Saving
S3 Power Saving
Power Saving
explain
BTO
PCH SM Bus Address
Power
Device
HEX
Address
+3VS
DDR SO-DIMM 0
A0 H
1010 0000 b
+3VS
DDR SO-DIMM 1
A4 H
1010 0100 b
+3VS
Clock Generator
D2 H
1101 0010 b
+3VS
New Card
+3VS
WLAN/WIMAX
+3VS
Clock Generator
SIGNAL
SLP_S3# SLP_S4# SLP_S5#

HIGH
HIGH
HIGH
S1(Power On Suspend)
HIGH
HIGH
HIGH
S3 (Suspend to RAM)
LOW
HIGH
HIGH
S4 (Suspend to Disk)
LOW
LOW
HIGH
S5 (Soft OFF)
LOW
LOW
LOW
G3
LOW
LOW
LOW
Full ON
EC SM Bus1 Address
STATE
EC SM Bus2 Address
Power
Device
HEX
Address
Power
Device
HEX
Address
+3VL
Smart Battery
16 H
0001 0110 b
+3VS
PCH
96 H
1001 0110 b
Power
Device
HEX
Address
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size Document Number
Custom
SCHEMATICS,MB A6847
Rev
B
4019AP
Date:
Sheet
E
of
52
JCPUB
AH24
COMP1
COMP0
SKTOCC#
28
CATERR#
2
49.9_0402_1%
AK14
AT15
PECI
CATERR#
THERMAL
1
R18
PECI
Power has removed VR_TT#

H_PROCHOT#_D
2
68_0402_5%
1
R9
+VTT
PROCHOT#
AK15
THERMTRIP#
A16
B16
BCLK_ITP
BCLK_ITP#
AR30
AT30
PEG_CLK
PEG_CLK#
E16
D16
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
A18
A17
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PM_EXT_TS#[0]
PM_EXT_TS#[1]
F6
CLK_CPU_BCLK 28
CLK_CPU_BCLK# 28
CLK_PEG 24
CLK_PEG# 24
R6 1
R7 1
R8 1
AN15 PM_EXTTS#0
AP15 PM_EXTTS#_R
AN28
AP28
AT27
TDI
TDO
TDI_M
TDO_M
AT29
AR27
AR29
AP29
DBR#
AN25
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23
1 10K_0402_5%
1 10K_0402_5%
2
R12
2 100_0402_1%
2 24.9_0402_1%
2 130_0402_1%
1
0_0402_5%
DDR3 Compensation Signals

Layout Note:Please these
resistors near Processor
PM_EXTTS# 11,12
SM_DRAMRST#_CPU
28 H_PWRGOOD
R28 @
1.1K_0402_1%
DRAMPWROK
25 DRAMPWROK
46 VTTPWROK_CPU
750_0402_1%
R29
1.5K_0402_1%
AN27
VCCPWRGOOD_0
AK13
SM_DRAMPWROK
VTTPWRGOOD
AM26
TAPPWRGOOD
AL14
RSTIN#
BUF_PLT_RST#_R
27 BUF_PLT_RST#
VCCPWRGOOD_1
VTTPWROK_CPU AM15
DRAMPWROK
AN14
R30
R31
750_0402_1%
PAD
R127
100K_0402_5%
RST_GATE 28
2
T42
SM_DRAMRST# 11,12
Q41
BSS138_NL_SOT23-3
XDP_TDO
XDP_TDI_M
XDP_TDO_M
PAD
PAD
PAD
2
R312
1
1K_0402_5%
+3VS
C301
0.047U_0402_16V7K
C301, Q41,
R127 from PS@
to mount
1 H_PWRGOOD1_R
R25
2
0_0402_5%
PM_SYNC
JTAG & BPM
+1.5V_CPU
AL15
T45
T44
T43
PMSYNCH
RESET_OBS#
PWR MANAGEMENT
25
AP26
TCK
TMS
TRST#
R15
PM_EXTTS#_R R13
AT28
AP27
PM_EXTTS#0
SM_DRAMRST#_CPU
AL1 SM_RCOMP_0
AM1 SM_RCOMP_1
AN1 SM_RCOMP_2
PRDY#
PREQ#
+VTT
Unused by Clarksfield rPGA989
28 H_THERMTRIP#
AN26
BCLK
BCLK#
CLOCKS
TP_SKTOCC#
T41
COMP2
DDR3
MISC
PAD
+VTT
COMP3
MISC
H_COMP3 AT23
2
20_0402_1%
H_COMP2 AT24
2
20_0402_1%
H_COMP1 G16
2
49.9_0402_1%
H_COMP0 AT26
2
49.9_0402_1%
1
R1
1
R2
1
R4
1
R3
XDP_DBRESET# 25
Add on 10/28
XDP_TDO_M
XDP_TDO
1
R23
1
R22
XDP_TDI_M
2
0_0402_5%
2
51_0402_5%
+VTT
IC,AUB_CFD_rPGA,R0P9
@
R28 unmount for NPS@

R29 always mount for PS@
For S3 CPU Power Saving
place near JCPU

+3VALW
DRAMPWROK
1 C488 VTTPWROK_CPU
1
C163
5
1 C487
VTTPWROK
IN1
IN2
O
3
41,46 VTTPWROK
2
0.1U_0402_16V4Z
U16
1000P_0402_50V7K
1000P_0402_50V7K
R33
DRAMPWROK
1.5K_0402_1%
SN74AHC1G08DCKR_SC70-5
0715 --> change BOM structure to mount
Issued Date
Compal Secret Data
2010/09/05
2011/09/05
Deciphered Date
Title
SCHEMATICS,MB A6847
Custom
Rev
B
4019AP
Date:
Sheet
1
of
52
+5VS
FAN Control Circuit

Remove Cap, for EMI
1A
2
C3
10U_0805_10V4Z
U1
1
2
3
4
+FAN1
38
EN_DFAN1
10mil
EN
VIN
VOUT
VSET
GND
GND
GND
GND
C4
@ 1000P_0402_25V8J
1
8
7
6
5
25
25
25
25
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
B24
D23
B23
A22
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
25
25
25
25
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
D24
G24
F23
H23
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
25
25
25
25
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
D25
F24
E23
G23
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
E22
D21
D19
D18
G21
E19
F21
G18
FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]
D22
C21
D20
C18
G22
E20
F20
G19
FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]
2
R686
1
1K_0402_5%
F17
E17
FDI_FSYNC[0]
FDI_FSYNC[1]
2
R688
1
1K_0402_5%
C17
FDI_INT
F18
D17
FDI_LSYNC[0]
FDI_LSYNC[1]
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PCI EXPRESS -- GRAPHICS
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
Intel(R) FDI
A24
C23
B22
A21
1
2
3
4
5
GND
GND
R34
C5
10U_0805_10V4Z
10K_0402_5%
1
+3VS
FAN_SPEED1 38
C6
0.01U_0402_25V7K
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
DMI
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
1
2
3
ACES_85204-0300N
APL5607KI-TRG_SO8
JCPUA
25
25
25
25
JFAN @
+FAN1
1
2
B26 PEG_COMP
R38
49.9_0402_1%
A26
B27
PEG_RBIAS 1
2
A25
R39
750_0402_1%
PCIE_GTX_C_CRX_N0
K35
PCIE_GTX_C_CRX_N1
J34
PCIE_GTX_C_CRX_N2
J33
PCIE_GTX_C_CRX_N3
G35
PCIE_GTX_C_CRX_N4
G32
PCIE_GTX_C_CRX_N5
F34
PCIE_GTX_C_CRX_N6
F31
PCIE_GTX_C_CRX_N7
D35
PCIE_GTX_C_CRX_N8
E33
PCIE_GTX_C_CRX_N9
C33
PCIE_GTX_C_CRX_N10
D32
PCIE_GTX_C_CRX_N11
B32
PCIE_GTX_C_CRX_N12
C31
PCIE_GTX_C_CRX_N13
B28
PCIE_GTX_C_CRX_N14
B30
PCIE_GTX_C_CRX_N15
A31
PCIE_GTX_C_CRX_N[0..15]
13
PCIE_GTX_C_CRX_P[0..15]
13
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30
PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_P5
PCIE_GTX_C_CRX_P6
PCIE_GTX_C_CRX_P7
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_P15
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N15
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_N8
PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_N15
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P15
C55
C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_N[0..15]
13
PCIE_CTX_C_GRX_P[0..15]
13
@
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size
B
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
of
52
JCPUC
JCPUD
12 DDR_B_D[0..63]
A10
C10
C7
A7
B10
D10
E10
A8
D8
F10
E6
F7
E9
B7
E7
C6
H10
G8
K7
J8
G7
G10
J7
J10
L7
M6
M8
L9
L6
K8
N8
P9
AH5
AF5
AK6
AK7
AF6
AG5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
AC3
AB2
U7
SA_BS[0]
SA_BS[1]
SA_BS[2]
11 DDR_A_CAS#
11 DDR_A_RAS#
11 DDR_A_WE#
AE1
AB3
AE9
SA_CAS#
SA_RAS#
SA_WE#
AA6
AA7
P7
DDRA_CLK0 11
DDRA_CLK0# 11
DDRA_CKE0 11
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
Y6
Y5
P6
DDRA_CLK1 11
DDRA_CLK1# 11
DDRA_CKE1 11
SA_CS#[0]
SA_CS#[1]
AE2
AE8
DDRA_SCS0# 11
DDRA_SCS1# 11
SA_ODT[0]
SA_ODT[1]
AD8
AF9
DDRA_ODT0 11
DDRA_ODT1 11
DDR_A_DM[0..7]
SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]
DDR SYSTEM MEMORY A
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
B9
D7
H7
M7
AG6
AM7
AN10
AN13
11
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
C9 DDR_A_DQS#0
DDR_A_DQS#1
F8
DDR_A_DQS#2
J9
N9 DDR_A_DQS#3
AH7 DDR_A_DQS#4
AK9 DDR_A_DQS#5
AP11 DDR_A_DQS#6
AT13 DDR_A_DQS#7
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
C8
F9
H9
M9
AH8
AK10
AN11
AR13
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
11
11
11
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5
AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT10
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
AB1
W5
R7
SB_BS[0]
SB_BS[1]
SB_BS[2]
12 DDR_B_CAS#
12 DDR_B_RAS#
12 DDR_B_WE#
AC5
Y7
AC6
SB_CAS#
SB_RAS#
SB_WE#
12
12
12
SB_CK[0]
SB_CK#[0]
SB_CKE[0]
W8
W9
M3
DDRB_CLK0 12
DDRB_CLK0# 12
DDRB_CKE0 12
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
V7
V6
M2
DDRB_CLK1 12
DDRB_CLK1# 12
DDRB_CKE1 12
SB_CS#[0]
SB_CS#[1]
AB8
AD6
DDRB_SCS0# 12
DDRB_SCS1# 12
SB_ODT[0]
SB_ODT[1]
AC7
AD1
DDRB_ODT0 12
DDRB_ODT1 12
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]
D4
E1
H3
K1
AH1
AL2
AR4
AT8
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
D5
F4
J4
L4
AH2
AL4
AR5
AR8
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
C5
E3
H4
M5
AG2
AL5
AP5
AR7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_DM[0..7]
12
DDR SYSTEM MEMORY - B
11 DDR_A_D[0..63]
11
11
11
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
12
12
DDR_B_MA[0..15]
12
@
A
@
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size
B
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
of
52
(Place these capacitors under CPU socket Edge, top layer)
(Place these capacitors between inductor and socket on Bottom)
+VTT
+CPU_CORE
VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44
AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15
10U_0805_10V4K
10U_0805_10V4K
10U_0805_10V4K
10U_0805_10V4K
D
C144 1
C267 1
AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
2 390U_2.5V_M_R10
C81 1
2 10U_0805_10V4K
VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32
2 390U_2.5V_M_R10
C83 1
2 10U_0805_10V4K
C85 1
2 10U_0805_10V4K
C87 1
2 10U_0805_10V4K
C89 1
2 22U_0805_6.3V6M
C88 1
2 10U_0805_10V4K
C91 1
2 22U_0805_6.3V6M
C90 1
2 10U_0805_10V4K
C92 1
2 10U_0805_10V4K
C94 1
2 10U_0805_10V4K@
SF000002O00
ESR 10m-ohm
H6.3
1
C71
10U_0805_10V4K
1
C72
1
C73
10U_0805_10V4K
1
C74
1
C75
10U_0805_10V4K
1
C76
1
C77
10U_0805_10V4K
1
C78
C79
10U_0805_10V4K
(Place these capacitors under CPU socket, top layer)

+CPU_CORE
10U_0805_10V4K
1
C98
10U_0805_10V4K
Power team request for F-Din
10U_0805_10V4K
1
C99
10U_0805_10V4K
1
C100
10U_0805_10V4K
1
C101
1
C102
10U_0805_10V4K
1
C103
C104
2
10U_0805_10V4K
(Place these capacitors on CPU cavity, Bottom Layer)
+CPU_CORE
+CPU_CORE
22U_0805_6.3V6M
22U_0805_6.3V6M
C114
C179
C131
22U_0805_6.3V6M
1
C116
C132
C129
C149
C105
C106
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
C107
C108
22U_0805_6.3V6M
C109
C110
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
+CPU_CORE
22U_0805_6.3V6M
C111
C112
POWER
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
1.1V RAIL POWER
Auburndale:18A
CPU CORE SUPPLY
Clarksfield: 21A
Auburndale:48A
PSI#
CPU VIDS
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
Clarksfield: 65A
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
PROC_DPRSLPVR
VTT_SELECT
AN33
H_PSI#
AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34 H_DPRSLPVR_R 1
R62
CPU_VID0 49
CPU_VID1 49
CPU_VID2 49
CPU_VID3 49
CPU_VID4 49
CPU_VID5 49
CPU_VID6 49
H_DPRSLPVR 49
2
0_0402_5%
CRB default setting:

VID[6:0]=[0100111]
49
22U_0805_6.3V6M
AJ34
AJ35
VTT_SENSE
VSS_SENSE_VTT
C148
22U_0805_6.3V6M
Auburndale +1.1VS_VTT=1.05V
Clarksfield +1.1VS_VTT=1.1V
+CPU_CORE
C121
VCC_SENSE
VSS_SENSE
C115
22U_0805_6.3V6M
22U_0805_6.3V6M
1
TOP side (under inductor)
AN35
C130
VTT Rail
G15
ISENSE
22U_0805_6.3V6M
1
C113
330U_D2_2.5VM_R9M
1
C122
330U_D2_2.5VM_R9M
2
SENSE LINES
Material Note (+VTT):

390uF/ 10mohm, number are 3,
power x1, HW x2
JCPUF
+CPU_CORE
+
2
C123
1
+
330U_D2_2.5VM_R9M
1
C124
330U_D2_2.5VM_R9M
2
+
2
IMVP_IMON 49
VCCSENSE_R R65
VSSSENSE_R R66
B15
A15
1
1
2 0_0402_5%
2 0_0402_5%
VTT_SENSE 46
VSS_SENSE_VTT 46
1
R64
VCCSENSE
VSSSENSE
R67
2
100_0402_1%
+CPU_CORE
Check list:
VCCSENSE 49
VSSSENSE 49
+CPU_CORE: 6x 470uF, 12x 22uF, 17x 10uF
2
100_0402_1%
near CPU
+VTT: 4x 330uF, 7x 22uF, 8x 10uF

A
Issued Date
Compal Secret Data
@
2010/09/05
2011/09/05
Deciphered Date
Title
Custom
SCHEMATICS,MB A6847
Rev
B
4019AP
Date:
Sheet

1
of
52
+1.5V_CPU
+1.5V
Q33
3A
2
1
2
3
4
+1.5V_CPU
C273
FDS6676AS_SO8
SUSP
2N7002DW-T/R7_SOT363-6
7/22 modified for cost down.
C472
Q46B
R418
1
2
220K_0402_5%
10U_0805_10V4K
JUMP_43X79
+VSB
R417
820K_0402_5%
Q46A
2
1
form PS@ to mount
R424
470_0805_5%
D
D
D
D
S
S
S
G
0.1U_0402_25V6
PJ32
+1.5VS
8
7
6
5
SUSP
SUSP
41,48
2N7002DW-T/R7_SOT363-6
22U_0805_6.3V6M
C142
J24
J23
H25
VTT1_45
VTT1_46
VTT1_47
AR22
AT22
GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]
AM22
AP22
AN22
AP23
AM23
AP24
AN24
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
- 1.5V RAILS
Auburndale:3A
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
DDR3
GRAPHICS VIDs
Clarksfield: 5A
FDI
VAXG_SENSE
VSSAXG_SENSE
22U_0805_6.3V6M
22U_0805_6.3V6M
VTT1_48
VTT1_49
VTT1_50
VTT1_51
VTT1_52
VTT1_53
VTT1_54
VTT1_55
VTT1_56
VTT1_57
VTT1_58
1.1V
C147
K26
J27
J26
J25
H27
G28
G27
G26
F26
E26
E25
AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1
VTT0_59
VTT0_60
VTT0_61
VTT0_62
P10
N10
L10
K10
VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68
J22
J20
J18
H21
H20
H19
VCCPLL1
VCCPLL2
VCCPLL3
L26
L27
M26
R687 2
1 1K_0402_5%
1U_0402_6.3V4Z
1U_0402_6.3V4Z
22U_0805_6.3V6M
2
1
1
C133
1
C134
1
C135
1U_0402_6.3V4Z
1
C136
1
C137
1U_0402_6.3V4Z
1
C138
1U_0402_6.3V4Z
+1.5V
PJ31 need to open for

S3 CPU Power Saving
22U_0805_6.3V6M
(Place these capacitors under CPU socket Edge, top layer)

1
C143
10U_0805_10V4K
C145
22U_0805_6.3V6M
+1.8VS
Clarksfield: 0.6A
+1.8VS_H_PLL 1U_0402_6.3V4Z
C151
1U_0402_6.3V4Z
4.7U_0603_6.3V6K
1
C152
2
R71
1
0_0805_5%
1
C153
C154
C155
2 22U_0805_6.3V6M
2.2U_0603_6.3V4Z
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size
B
Date:
+ C216
390U_2.5V_M_R10
C139
PJ31
JUMP_43X79
@
2 0.1U_0402_16V4Z
remove PJ30
Auburndale:1.35A
A
2 0.1U_0402_16V4Z
C186 1
+VTT
1.8V
PEG & DMI
22U_0805_6.3V6M
2 0.1U_0402_16V4Z
C205 1
GFXVR_IMON
Auburndale:18A
+VTT
2 0.1U_0402_16V4Z
C314 1
+VTT
Clarksfield: 21A
C146
AR25
AT25
AM24
C230 1
+1.5V_CPU
Auburndale:22A
+VTT
C141
GRAPHICS
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
POWER
2
1
R258
0_0402_5%
SENSE
LINES
JCPUG
AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AL21
AL19
AL18
AL16
AK21
AK19
AK18
AK16
AJ21
AJ19
AJ18
AJ16
AH21
AH19
AH18
AH16
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
of
52
JCPUI
JCPUH
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AJ8
AJ5
AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35
VSS
NCTF
K27
K9
K6
K3
J32
J30
J21
J19
H35
H32
H28
H26
H24
H22
H18
H15
H13
H11
H8
H5
H2
G34
G31
G20
G9
G6
G3
F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11
E8
E5
E2
D33
D30
D26
D9
D6
D3
C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11
B8
B6
B4
A29
A27
A23
A9
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
AT35
AT1
AR34
B34
B2
B1
A35
@
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
JCPUE
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30
AP25
AL25
AL24
AL22
AJ33
AG9
M27
L28
J17
H17
G25
G17
E31
E30
WW41 Recommend not pull down

PCIE2.0 Jitter is over on ES1
3.01K_0402_1% 1 @ R74
3.01K_0402_1% 1 @ R75
3.01K_0402_1% 1 @ R76
2
2
AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
H16
*1:Single PEG
0:Bifurcation enabled
RSVD15
RSVD16
A20
B20
RSVD17
RSVD18
U9
T9
RSVD19
RSVD20
AC9
AB9
RSVD21
RSVD22
C1
A3
CFG3 - PCI-Express Static Lane Reversal

*1 :Normal Operation
0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86
B19
A19
CFG0 - PCI-Express Configuration Select
RSVD32
RSVD33
AJ13
AJ12
RSVD34
RSVD35
AH25
AK26
RSVD36
RSVD_NCTF_37
AL26
AR2
RSVD38
RSVD39
AJ26
AJ27
RSVD_NCTF_40
RSVD_NCTF_41
AP1
AT2
RSVD_NCTF_42
RSVD_NCTF_43
AT3
AR1
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57
RSVD58
AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32
RSVD_TP_59
RSVD_TP_60
KEY
RSVD62
RSVD63
RSVD64
RSVD65
E15
F15
A2
D15
C15
AJ15
AH15
RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75
AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9
RSVD_NCTF_23
RSVD_NCTF_24
J29
J28
RSVD26
RSVD27
A34
A33
RSVD_NCTF_28
RSVD_NCTF_29
C35
B35
RSVD_NCTF_30
RSVD_NCTF_31
VSS
CFG4 - Display Port Presence

*1:Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port
device is connected to the Embedded
Display Port
@
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9 (SA_DIMM_VREF)
RSVD10(SB_DIMM_VREF)
RSVD11
RSVD12
RSVD13
RSVD14
RESERVED
AP34
@
*:Default
A
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
SCHEMATICS,MB A6847
Custom
Rev
B
4019AP
Date:
Sheet
1
10
of
52
+1.5V
DDR3 SO-DIMM A
Standard Type
JDDRL
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
close to JDDRL.1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDRA_CKE0
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
7
7
DDRA_CLK0
DDRA_CLK0#
DDR_A_MA10
DDR_A_BS0
7
7
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDRA_SCS1#
DDR_A_D32
DDR_A_D33
B
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
1
1
C182
2
R91
10K_0402_5%
2
1
C181
2.2U_0603_6.3V4Z
+3VS
0.1U_0402_16V4Z
DDR_A_D58
DDR_A_D59
R90 1
2
10K_0402_5%
+0.75VS
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
205
207
GND1
GND2
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
BOSS1
BOSS2
206
208
+1.5V
7 DDR_A_DQS#[0..7]
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
M1 Circuit
7 DDR_A_DQS[0..7]
DDR_A_DQS#0
DDR_A_DQS0
7 DDR_A_D[0..63]
+1.5V
R79
1K_0402_1%
7 DDR_A_DM[0..7]
DDR_A_D6
DDR_A_D7
2
R78
1
0_0402_5%
+VREF_DQB
7 DDR_A_MA[0..15]
R83
1K_0402_1%
2
R80
1
0_0402_5%
+VREF_DQA
+V_DDR3_DIMM_REF
DDR_A_D12
DDR_A_D13
DDR_A_DM1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
R81
1K_0402_1%
R83 from PS@ to mount

SM_DRAMRST# 5,12
DDR_A_DM0
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
DDR_A_D0
DDR_A_D1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDRA_CKE1 7
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDRA_CLK1 7
DDRA_CLK1# 7
DDR_A_BS1 7
DDR_A_RAS# 7
DDRA_SCS0# 7
DDRA_ODT0 7
+V_DDR3_DIMM_REF
DDRA_ODT1 7
R89
1
0_0402_5%
+DDR_VREF_CA_DIMMA
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
C161
2.2U_0603_6.3V4Z
C157
2.2U_0603_6.3V4Z
C156
0.1U_0402_16V4Z
+VREF_DQA
Layout Note:
Place near JDDRL
Layout Note: Place these 4 Caps near

Command and Control signals of DIMMA
Layout Note:
Place near JDDRL1.203 and 204
2
+1.5V
C218 1
+1.5V
C162
0.1U_0402_16V4Z
2 390U_2.5V_M_R10
close to JDDRL.126
DDR_A_D46
DDR_A_D47
C166 1
2 10U_0805_6.3V6M
C168 1
2 10U_0805_6.3V6M
C171 1
2 10U_0805_6.3V6M
DDR_A_DM6
C174 1
2 10U_0805_6.3V6M
DDR_A_D54
DDR_A_D55
C176 1
2 10U_0805_6.3V6M
C178 1
2 10U_0805_6.3V6M
DDR_A_D52
DDR_A_D53
DDR_A_D60
DDR_A_D61
+1.5V
+0.75VS
C164 1
2 0.1U_0402_16V4Z
C167 1
2 0.1U_0402_16V4Z
C170 1
2 0.1U_0402_16V4Z
C173 1
2 0.1U_0402_16V4Z
C165 1
2 10U_0805_6.3V6M
C169 2
1 1U_0402_6.3V4Z
C172 2
1 1U_0402_6.3V4Z
C175 2
1 1U_0402_6.3V4Z
C177 2
1 1U_0402_6.3V4Z
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PM_EXTTS# 5,12
PM_SMBDATA 12,21,24,33
PM_SMBCLK 12,21,24,33
+0.75VS
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Custom
FOX_AS0A626-U2SN-7F_204P
@
SCHEMATICS,MB A6847
Rev
B
4019AP
Date:
Sheet
1
11
of
52
+1.5V
+1.5V
DDR_B_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
close to JDDRH.1
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDRB_CKE0
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
7
7
DDRB_CLK0
DDRB_CLK0#
DDR_B_MA10
DDR_B_BS0
7
7
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDRB_SCS1#
DDR_B_D32
DDR_B_D33
3
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
R98 1
2
10K_0402_5%
+3VS
2.2U_0603_6.3V4Z
1
1 R99
2
10K_0402_5%
C207
C208
2
2
0.1U_0402_16V4Z
+0.75VS
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
205
207
GND1
GND2
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
BOSS1
BOSS2
206
208
DDR_B_D4
DDR_B_D5
7 DDR_B_DQS[0..7]
DDR_B_D6
DDR_B_D7
7 DDR_B_D[0..63]
DDR_B_D12
DDR_B_D13
7 DDR_B_DM[0..7]
1
7 DDR_B_MA[0..15]
DDR_B_DM1
SM_DRAMRST# 5,11
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDRB_CKE1 7
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDRB_CLK1 7
DDRB_CLK1# 7
DDR_B_BS1 7
DDR_B_RAS# 7
DDRB_SCS0# 7
DDRB_ODT0 7
DDRB_ODT1 7
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
+V_DDR3_DIMM_REF
R97
1
+DDR_VREF_CA_DIMMB
2 0_0402_5%
Layout Note:
Place near JDDRH
DDR_B_DQS#5
DDR_B_DQS5
Layout Note: Place these 4 Caps near

Command and Control signals of DIMMB
Layout Note:
Place near JDDRH.203 and 204
+1.5V
+1.5V
@
C189 1
DDR_B_D44
DDR_B_D45
close to JDDRH.126
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
+0.75VS
2 330U_B2_2.5VM_R15M
C192 1
2 10U_0805_6.3V6M
C194 1
2 10U_0805_6.3V6M
C197 1
2 10U_0805_6.3V6M
C200 1
2 10U_0805_6.3V6M
C202 1
2 10U_0805_6.3V6M
C204 1
2 10U_0805_6.3V6M
C190 1
2 0.1U_0402_16V4Z
C193 1
2 0.1U_0402_16V4Z
C196 1
2 0.1U_0402_16V4Z
C199 1
2 0.1U_0402_16V4Z
C191 1
2 10U_0805_6.3V6M
C195 2
1 1U_0402_6.3V4Z
C198 2
1 1U_0402_6.3V4Z
C201 2
1 1U_0402_6.3V4Z
C203 2
1 1U_0402_6.3V4Z
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PM_EXTTS# 5,11
PM_SMBCLK 11,21,24,33
+0.75VS
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Custom
FOX_AS0A626-UASN-7F_204P
@
A
7 DDR_B_DQS#[0..7]
DDR_B_DQS#0
DDR_B_DQS0
C188
0.1U_0402_16V4Z
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
C187
2.2U_0603_6.3V4Z
C184
0.1U_0402_16V4Z
C183
2.2U_0603_6.3V4Z
DDR_B_D0
DDR_B_D1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
Standard Type
DDR3 SO-DIMM B
JDDRH
+VREF_DQB
SCHEMATICS,MB A6847
Rev
B
4019AP
Date:
Sheet
E
12
of
52
6 PCIE_GTX_C_CRX_P[0..15]
PCIE_GTX_C_CRX_P[0..15]
UV1A
6 PCIE_GTX_C_CRX_N[0..15]
6 PCIE_CTX_C_GRX_P[0..15]
PCIE_GTX_C_CRX_N[0..15]
LANE Reversal
LANE Reversal
Close to UV1
PCIE_CTX_C_GRX_P[0..15]
6 PCIE_CTX_C_GRX_N[0..15]
PCIE_CTX_C_GRX_N[0..15]
PCIE_RX0P
PCIE_RX0N
PCIE_TX0P
PCIE_TX0N
AH30
AG31
PCIE_GTX_CRX_P15
PCIE_GTX_CRX_N15
CV1
CV2
1
1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_CRX_P15
PCIE_GTX_C_CRX_N15
PCIE_CTX_C_GRX_P14 AE29
PCIE_CTX_C_GRX_N14 AD28
PCIE_RX1P
PCIE_RX1N
PCIE_TX1P
PCIE_TX1N
AG29
AF28
PCIE_GTX_CRX_P14
PCIE_GTX_CRX_N14
CV3
CV4
1
1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_N14
PCIE_CTX_C_GRX_P13 AD30
PCIE_CTX_C_GRX_N13 AC31
PCIE_RX2P
PCIE_RX2N
PCIE_TX2P
PCIE_TX2N
AF27
AF26
PCIE_GTX_CRX_P13
PCIE_GTX_CRX_N13
CV5
CV6
1
1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_N13
PCIE_CTX_C_GRX_P12 AC29
PCIE_CTX_C_GRX_N12 AB28
PCIE_RX3P
PCIE_RX3N
PCIE_TX3P
PCIE_TX3N
AD27
AD26
PCIE_GTX_CRX_P12
PCIE_GTX_CRX_N12
CV7
CV8
1
1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_N12
PCIE_CTX_C_GRX_P11 AB30
PCIE_CTX_C_GRX_N11 AA31
PCIE_RX4P
PCIE_RX4N
PCIE_TX4P
PCIE_TX4N
AC25
AB25
PCIE_GTX_CRX_P11
PCIE_GTX_CRX_N11
CV9 1
CV10 1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_CRX_P11
PCIE_GTX_C_CRX_N11
PCIE_CTX_C_GRX_P10 AA29
PCIE_CTX_C_GRX_N10
Y28
PCIE_RX5P
PCIE_RX5N
PCIE_TX5P
PCIE_TX5N
Y23
Y24
PCIE_GTX_CRX_P10
PCIE_GTX_CRX_N10
CV11 1
CV12 1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_N10
PCIE_TX6P
PCIE_TX6N
AB27
AB26
PCIE_GTX_CRX_P9
PCIE_GTX_CRX_N9
CV13 1
CV14 1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_N9
PCIE_TX7P
PCIE_TX7N
Y27
Y26
PCIE_GTX_CRX_P8
PCIE_GTX_CRX_N8
CV15 1
CV16 1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_N8
PCIE_TX8P
PCIE_TX8N
W24
W23
PCIE_GTX_CRX_P7
PCIE_GTX_CRX_N7
CV17 1
CV18 1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_CRX_P7
PCIE_GTX_C_CRX_N7
PCIE_TX9P
PCIE_TX9N
V27
U26
PCIE_GTX_CRX_P6
PCIE_GTX_CRX_N6
CV19 1
CV20 1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_CRX_P6
PCIE_GTX_C_CRX_N6
PCIE_TX10P
PCIE_TX10N
U24
U23
PCIE_GTX_CRX_P5
PCIE_GTX_CRX_N5
CV21 1
CV22 1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_CRX_P5
PCIE_GTX_C_CRX_N5
PCIE_TX11P
PCIE_TX11N
T26
T27
PCIE_GTX_CRX_P4
PCIE_GTX_CRX_N4
CV23 1
CV24 1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_N4
PCIE_TX12P
PCIE_TX12N
T24
T23
PCIE_GTX_CRX_P3
PCIE_GTX_CRX_N3
CV25 1
CV26 1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_N3
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_N9
Y30
W31
PCIE_RX6P
PCIE_RX6N
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_N8
W29
V28
PCIE_RX7P
PCIE_RX7N
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7
V30
U31
PCIE_RX8P
PCIE_RX8N
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6
U29
T28
PCIE_RX9P
PCIE_RX9N
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5
T30
R31
PCIE_RX10P
PCIE_RX10N
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
R29
P28
PCIE_RX11P
PCIE_RX11N
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
P30
N31
PCIE_RX12P
PCIE_RX12N
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
N29
M28
PCIE_RX13P
PCIE_RX13N
PCIE_TX13P
PCIE_TX13N
P27
P26
PCIE_GTX_CRX_P2
PCIE_GTX_CRX_N2
CV27 1
CV28 1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_N2
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
M30
L31
PCIE_RX14P
PCIE_RX14N
PCIE_TX14P
PCIE_TX14N
P24
P23
PCIE_GTX_CRX_P1
PCIE_GTX_CRX_N1
CV29 1
CV30 1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_N1
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
L29
K30
PCIE_RX15P
PCIE_RX15N
PCIE_TX15P
PCIE_TX15N
M27
N26
PCIE_GTX_CRX_P0
PCIE_GTX_CRX_N0
CV31 1
CV32 1
2
2
0.1U_0402_16V7K
0.1U_0402_16V7K
PCIE_GTX_C_CRX_P0
PCIE_GTX_C_CRX_N0
PCI EXPRESS INTERFACE
PCIE_CTX_C_GRX_P15 AF30
PCIE_CTX_C_GRX_N15 AE31
CLOCK
AK30
AK32
24 CLK_PCIE_VGA
24 CLK_PCIE_VGA#
PCIE_REFCLKP
PCIE_REFCLKN
CALIBRATION
RV133 1
27,33,34,38,39 PLT_RST#
2 10K_0402_5%
N10
PWRGOOD
AL27
PCIE_CALRP
Y22
RV1
2 1.27K_0402_1%
PCIE_CALRN
AA22
RV2
2 2K_0402_1%
+1.0VS
PERSTB
216-0774009-A11PARK_FCBGA631
PARKR1@
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size
Date:

SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
13
of
52
UV1B
M93-S3/M92-S2
TV15
20
20
20
VRAM_ID2
VRAM_ID1
VRAM_ID0
AE9
L9
N9
AE8
AD9
AC10
AD7
AC8
AC7
AB9
AB8
AB7
AB4
AB2
Y8
Y7
DVCNTL_0/ DVPDATA_18
DVCNTL_1 / NC
DVCNTL_2 / TESTEN#2
DVDATA_12 / DVPDATA_16
DVDATA_7 / DVPCNTL_0
DVDATA_4 DVPDATA_4
+1.8VS
2
1 10U_0603_6.3V6M
BLM18PG121SN1D_0603 1
1
CV54
TX0P_DPA2P
TX0M_DPA2N
TX1P_DPA1P
TX1M_DPA1N
AH3
AH1
TX2P_DPA0P
TX2M_DPA0N
AK3
AK1
DPA
TXCBP_DPB3P
TXCBM_DPB3N
AK5
AM3
TX3P_DPB2P
TX3M_DPB2N
AK6
AM5
TX4P_DPB1P
TX4M_DPB1N
AJ7
AH6
TX5P_DPB0P
TX5M_DPB0N
AK8
AL7
DPB
0.1U_0402_16V4Z
1
CV55
CV53
2
2
1U_0402_6.3V4Z
+1.0VS
2
1
BLM18PG121SN1D_0603
10U_0603_6.3V6M
0.1U_0402_16V4Z
1
1
CV61
CV60
W6
V6
DPC_PVDD / DVPDATA_11
DPC_PVSS / GND
+DPC_VDD18
AC6
AC5
DPC_VDD18#1/DVPDAT10
+DPC_VDD10
AA5
AA6
M92-S2/M93-S3
DVPDATA_3/TXCCP_DPC3P
DVPCNTL_2/TXCCM_DPC3N
V4
U5
DVPDATA_7 / TX0P_DPC2P
DVPDATA_1 / TX0M_DPC2N
W3
V2
DVPCNTL_MV1 / TX1P_DPC1P
DVPDATA_9 / TX1M_DPC1N
CV59
2
1U_0402_6.3V4Z
U1
W1
U3
Y6
AA1
+3VS
DPC_VSSR#1 / DVPCLK
DVPDATA_13 / TX2P_DPC0P
DPC_VSSR#2 / DVPDAT5
DVPCNTL_1 / TX2M_DPC0N
DPC_VSSR#3 / GND
DPC_VSSR#4 / GND
VDDR4 / DPCD_CALR
DPC_VSSR#5/ DVPCNTL_MV0
VGA_EDID_CLK
VGA_EDID_CLK
VGA_EDID_DATA
21 VGA_EDID_CLK
21 VGA_EDID_DATA
R1
R3
SCL
SDA
VGA_PWRSEL0
20 GPU_GPIO0
20 GPU_GPIO1
20 GPU_GPIO2
20 GPU_SMB_DA2
20 GPU_SMB_CK2
1 RV131 VGA_PWRSEL1
@ 10K_0402_5% 2
10K_0402_5% 2
1 RV32
THERM#_VGA
@ 10K_0402_5% 2
1 RV33
CLKREQ_PEG#_R
@ 10K_0402_5% 2
1 RV35
GENERIC_C
@ 10K_0402_5% 2
1 RV31
GPU_SMB_DA2
38
20
20
20
20
20
1 RV142 GPU_SMB_CK2
@ 10K_0402_5% 2
10K_0402_5% 1
2 RV17
GPU_SMB_DA2
GPU_SMB_CK2
VGA_ENBKL
VGA_ENBKL
SOUT_GPIO8
SIN_GPIO9
GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
TV11
VGA_PWRSEL0
50 VGA_PWRSEL0
21
27M_SSC
20 THERM#_VGA
VGA_ENBKL
THERM#_VGA
VGA_PWRSEL1
50 VGA_PWRSEL1
20 ROMSE_GPIO22
2
0_0402_5%
@
1
RV27
24 CLKREQ_PEG#
CLKREQ_PEG#_R
TV14
TV9
TV12
TV13
TV10
TV16
GENERIC_C
RB/GB/BB: Grounded right

away. MUST not be connected
to AVSSQ.
TV17
U6
U10
T10
U8
U7
T9
T8
T7
P10
P4
P2
N6
N5
N3
Y9
N1
M4
R6
W10
M2
P8
P7
N8
N7
GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
L6
L5
L3
L1
K4
AF24
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
TESTEN
AB13
W8
W9
W7
AD10
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
AC14
DAC1
R
RB
AM26
AK26
VGA_CRT_R
G
GB
AL25
AJ25
VGA_CRT_G
B
BB
AH24
AG25
VGA_CRT_B
HSYNC
VSYNC
AH26
AJ27
RSET
AD22
AVDD
AVSSQ
AG24
AE22
VDD1DI
VSS1DI
AE23
AD23
AC16
+AVDD_VGA
1
2
RV18 499_0402_1%
+AVDD_VGA
HPD1
1
CV33
1U_0402_6.3V4Z
+VDD1DI
AM12
AK12
G2 / NC
G2B / NC
AL11
AJ11
B2 / NC
B2B / NC
AK10
AL9
C / NC
Y / NC
COMP / NC
AH12
AM10
AJ9
H2SYNC
V2SYNC
AL13
AJ13
VDD2DI / NC
VSS2DI / NC
AD19
AC19
+VDD1DI
A2VDD / NC
AE20
+A2VDD
A2VDDQ / NC
AE17
+A2VDDQ
VREFG
M92-S2/M93-S3
+VDD1DI
HSYNC_DAC2
VSYNC_DAC2
A2VSSQ
AE19
R2SET / NC
AG13
20
20
0.1U_0402_16V4Z +DPLL_PVDD
1
1
CV42
CV41
1U_0402_6.3V4Z
CV40
2
2
2
10U_0603_6.3V6M
+DPLL_PVDD
1
LV3
21
AF14
AE14
DPLL_PVDD
DPLL_PVSS
75mA
DDC/AUX
+DPLL_VDDC
47.5_0402_1%
2
1
RV28
27M_CLK
XTALIN
1
AD14
DPLL_VDDC
AM28
AK28
XTALIN
XTALOUT
125mA
RV29
100_0402_1%
BLM18PG121SN1D_0603
0.1U_0402_16V4Z
2
1
LV5
1
1
1
CV43
CV44
2
+DPLL_VDDC
AC22
AB22
+1.0VS
CV45
Check voltage level
2 1U_0402_6.3V4Z
10U_0603_6.3V6M
THERMAL
T4
T2
20 GPU_THERMAL_D+
20 GPU_THERMAL_D-
+1.8VS
BLM18PG121SN1D_0603
0.1U_0402_16V4Z
2
1
LV7
1
1
1
CV51
CV50
2
10U_0603_6.3V6M
R5
AD17
AC17
+TSVDD
CV52
1U_0402_6.3V4Z
1
LV12
2
0_0603_5%
TS_FDO
TSVDD
TSVSS
BLM18PG121SN1D_0603
2
1
+1.8VS
LV1
CV35
CV34
10U_0603_6.3V6M
2
2
0.1U_0402_16V4Z
DDC1CLK
DDC1DATA
AUX1P
AUX1N
AD2
AD4
DDC2CLK
DDC2DATA
AC11
AC13
AUX2P
AUX2N
AD13
AD11
DDC6CLK
DDC6DATA
NC/DDCCLK_AUX3P
NC/DDCDATA_AUX3N
1
CV37
2
2
0.1U_0402_16V4Z
2mA
1
1
RV22
2
715_0402_1%
VGA_CRT_CLK
VGA_CRT_DATA
10U_0603_6.3V6M
VGA_CRT_CLK 22
VGA_CRT_DATA 22
BLM18PG121SN1D_0603
2
1
+1.8VS
LV2
CV38
10U_0603_6.3V6M
1
CV46
1
CV47
2
2
0.1U_0402_16V4Z
BLM18PG121SN1D_0603
2
1
+1.8VS
LV6
CV48
1U_0402_6.3V4Z
CRT
Follow HB uses DDC1 for CRT
AE16
AD16
AC1
AC3
+3VS
AD20
AC20
VGA_CRT_CLK
RV134
1 4.7K_0402_5%
VGA_CRT_DATA RV135
1 4.7K_0402_5%
216-0774009-A11PARK_FCBGA631
Compal Secret Data
Issued Date
2010/09/05
Deciphered Date
2011/09/05
Title
Date:
20mA
Size
5
+3VS
DPLUS
DMINUS
PARKR1@
150_0402_1%
2
AE6
AE5
DDCCLK_AUX5P
DDCDATA_AUX5N
NC#2/XO_IN
NC#1/XO_IN2
150_0402_1%
45mA
CV36
1U_0402_6.3V4Z
+A2VDDQ
R2SET
M92-S2/M93-S3
PLL/CLOCK
+1.8VS
150_0402_1%
70mA
CV49
0.1U_0402_16V4Z
BLM18PG121SN1D_0603
20,22
20,22
CRT
VGA_CRT_B 22
R2 / NC
R2B / NC
DAC2
1
RV21
249_0402_1%
VGA_CRT_G
M92-S2/M93-S3
+VGA_VREF
VGA_CRT_G 22
VGA_CRT_R
1
RV11
1
RV12
VGA_CRT_B
1
RV13
VGA_CRT_R 22
VGA_CRT_HSYNC
VGA_CRT_VSYNC
RESET
RV20
499_0402_1%
+1.8VS
RV16
1
2
150_0402_1%
I2C
GENERAL PURPOSE I/O
1 RV30
AA12
LCD
+3VS
@ 10K_0402_5% 2
Y4
W5
AA3
Y2
DPC
VGA_EDID_DATA
M93-S3/M92-S2
+DPC_VDD18
LV10
1
4.7K_0402_5%
1
4.7K_0402_5%
AF2
AF4
AG3
AG5
DVO
LV8
2
RV139
2
RV140
TXCAP_DPA3P
TXCAM_DPA3N

SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
1
Sheet
14
of
52
UV1F
LVDS CONTROL
VARY_BL
DIGON
AB11
AB12
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
AH20
AJ19
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
AL21
AK20
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
AH22
AJ21
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
AL23
AK22
TXOUT_U3P
TXOUT_U3N
AK24
AJ23
VGA_PWM 21
VGA_ENVDD 21
UV1G
+1.8VS
+1.8VS_DPEF
LV15
2
1 10U_0603_6.3V6M
BLM18PG121SN1D_0603 1
1
CV89
2
+1.0VS
LVTMDP
CV99
DP E/F POWER
+1.8VS_DPAB
DP A/B POWER
LV18
AG15
AG16
220mA
130mA
DPE_VDD18#1
DPE_VDD18#2
DPA_VDD18#1
DPA_VDD18#2
AG20
AG21
120mA
110mA
DPE_VDD10#1
DPE_VDD10#2
DPA_VDD10#1
DPA_VDD10#2
AF6
AF7
AG14
AH14
AM14
AM16
AM18
DPE_VSSR#1
DPE_VSSR#2
DPE_VSSR#3
DPE_VSSR#4
DPE_VSSR#5
DPA_VSSR#1
DPA_VSSR#2
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5
AE1
AE3
AG1
AG6
AH5
+1.8VS_DPEF
AF16
AG17
200mA
130mA
DPF_VDD18#1
DPF_VDD18#2
DPB_VDD18#1
DPB_VDD18#2
+1.0VS_DPEF
AF22
AG22
120mA
110mA
DPF_VDD10#1
DPF_VDD10#2
AF23
AG23
AM20
AM22
AM24
0.1U_0402_16V4Z
1
CV73
AE11
AF11
+1.0VS_DPEF
2
2
1U_0402_6.3V4Z
+1.8VS
0_0603_5%
+1.0VS_DPAB
LV19
+1.0VS
0_0603_5%
LV32
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
AL15
AK14
2
1 10U_0603_6.3V6M
BLM18PG121SN1D_0603 1
1
VGA_TXCLK+ 21
VGA_TXCLK- 21
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
AH16
AJ15
VGA_TXOUT0+ 21
VGA_TXOUT0- 21
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
AL17
AK16
VGA_TXOUT1+ 21
VGA_TXOUT1- 21
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
AH18
AJ17
VGA_TXOUT2+ 21
VGA_TXOUT2- 21
TXOUT_L3P
TXOUT_L3N
AL19
AK18
CV165
0.1U_0402_16V4Z
1
CV166
CV164
2
2
1U_0402_6.3V4Z
Single channel
AE13
AF13
+1.8VS_DPAB
DPB_VDD10#1
DPB_VDD10#2
AF8
AF9
+1.0VS_DPAB
DPF_VSSR#1
DPF_VSSR#2
DPF_VSSR#3
DPF_VSSR#4
DPF_VSSR#5
DPB_VSSR#1
DPB_VSSR#2
DPB_VSSR#3
DPB_VSSR#4
DPB_VSSR#5
AF10
AG9
AH8
AM6
AM8
AF17
DPEF_CALR
DPAB_CALR
AE10
+1.8VS_DPEF
AG18
AF19
DPE_PVDD
DPE_PVSS
+1.8VS_DPEF
AG19
AF20
20mA
20mA
DPF_PVDD
DPF_PVSS
DPB_PVDD
DPB_PVSS
216-0774009-A11PARK_FCBGA631
PARKR1@
RV14
1
2
150_0402_1%
20mA
20mA
DP PLL POWER
DPA_PVDD
DPA_PVSS
RV15
1
2
150_0402_1%
AG8
AG7
+1.8VS_DPAB
AG10
AG11
+1.8VS_DPAB
216-0774009-A11PARK_FCBGA631
PARKR1@
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size
Date:

SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
15
of
52
UV1D
+1.5VS
MEM I/O
10U_0603_6.3V6M
4.7U_0603_6.3V6K
2
2
2
1
1
1
+
CV78
390U_2.5V_M_R10
CV91
2
CV87
CV83
1
1
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CV275
CV274
CV273
2
2
4.7U_0603_6.3V6K
CV102
CV98
CV97
CV96
H13
H16
H19
J10
J23
J24
J9
K10
K23
K24
K9
L11
L12
L13
L20
L21
L22
CV95
1
1
1
1
1
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
CV119
CV123
1U_0402_6.3V4Z
2
CV162
1
AA20
AA21
AB20
AB21
CV135
1
CV158
1
1U_0402_6.3V4Z
AA17
AA18
AB17
AB18
CV152
V12
Y12
U12
CV148
+VDDR4
1
10U_0603_6.3V6M
AA11
Y11
V11
U11
LV24
2
1
BLM18PG121SN1D_0603
+1.8VS
0.1U_0402_16V4Z
1
1
CV172
CV173
2
VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4
VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4
I/O
VDDR4#1 / VDDR5
VDDR4#2
VDDR4#3 / VDDR5
NC#1 / VDDR4
DVCLK / VDDR4
NC#3 / VDDR5
TESTEN#2 / VDDR5
MEM CLK
1U_0402_6.3V4Z
L17
VDDRHA
L16
VSSRHA
VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#20
VDDC#21
VDDC#22
VDDC#23 /BIF_VDDC
VDDC#19/BIF_VDDC
CORE
M93-S3/M92-S2
0.1U_0402_16V4Z
1U_0402_6.3V4Z
2
+VDD_CT
1U_0402_6.3V4Z
2
CV131
PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12
POWER
1U_0402_6.3V4Z
+3VS
CV127
PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
LEVEL
TRANSLATION
17mA
LV22
10U_0603_6.3V6M
2
1
BLM18PG121SN1D_0603
2
+1.8VS
VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
+MPV18
+SPV18
LV28
2
1
BLM18PG121SN1D_0603
+1.0VS
1U_0402_6.3V4Z
1
1
CV189
CV190
2
10U_0603_6.3V6M
+1.8VS
LV30
2
1 10U_0603_6.3V6M
BLM18PG121SN1D_0603 1
1
CV276
2
+1.8VS
LV31
2
1
BLM18PG121SN1D_0603
CV309
CV303
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CV277
2
2
10U_0603_6.3V6M
1
CV308
2
1U_0402_6.3V4Z
CV191
75mA
L8
MPV18
SPV18
J7
SPVSS
L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22
AA15
N15
N17
R13
R16
R18
Y21
T12
T15
T17
T20
U13
U16
U18
V21
V15
V17
V20
Y13
Y16
Y18
R21
U21
0.1U_0402_16V4Z
2
2
CV101
1
CV105
1
0.1U_0402_16V4Z
CV82
1
1U_0402_6.3V4Z
2
CV86
CV90
1
1U_0402_6.3V4Z
CV77
1
10U_0603_6.3V6M
+1.0VS
2A
1U_0402_6.3V4Z
2
2
CV104
1
1U_0402_6.3V4Z
2
CV108
1
1U_0402_6.3V4Z
2
CV111
1
1U_0402_6.3V4Z
CV112
CV113
1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
CV115
CV118
1
1U_0402_6.3V4Z
CV100
1
10U_0603_6.3V6M
+VGA_CORE
13A
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
2
CV153
CV121
1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
2
CV140
1
CV122
1
1U_0402_6.3V4Z
2
CV125
1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
2
CV141
1
1U_0402_6.3V4Z
CV143
1
CV129
1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
CV144
1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
CV126
CV167
1
1U_0402_6.3V4Z
CV133
1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
CV145
1U_0402_6.3V4Z
2
CV130
CV281
1U_0402_6.3V4Z
2
CV137
1
1U_0402_6.3V4Z
4.7U_0603_6.3V6K
1
1
CV163
CV134
CV279
2
2
4.7U_0603_6.3V6K
CV138
1
4.7U_0603_6.3V6K
1
CV280
CV278
2
2
4.7U_0603_6.3V6K
C
+ CV114
390U_2.5V_M_R10
10U_0603_6.3V6M
10U_0603_6.3V6M
2
2
2
2
CV116
390U_2.5V_M_R10
CV132
1
CV136
1
CV139
1
CV142
1
2
10U_0603_6.3V6M
VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
10U_0603_6.3V6M
M13
M15
M16
M17
M18
M20
M21
N20
+VGA_CORE
SPV10
0.1U_0402_16V4Z
2
2
BACK BIAS
M11
M12
1U_0402_6.3V4Z
2
2
ISOLATED
CORE I/O
PCIE_PVDD
75mA H7
120mA H8
1
0.1U_0402_16V4Z
+VGA_CORE
+MPV18
0.1U_0402_16V4Z
1
1
+SPV10
2
AM30
+PCIE_VDDR
AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26
PLL
+PCIE_VDDR
+1.8VS
LV21
1
2
BLM18PG121SN1D_0603
500mA
PCIE
1.2A
4.7U_0603_6.3V6K 1U_0402_6.3V4Z 1U_0402_6.3V4Z

1
2
2
2
2
2
CV272
BBP#1
BBP#2
0.1U_0402_16V4Z
2
1
CV201
1
1
0.1U_0402_16V4Z
CV197
1U_0402_6.3V4Z
1
CV198
2
1U_0402_6.3V4Z
CV199
2
4.7U_0603_6.3V6K
1
CV200
2
10U_0603_6.3V6M
CV271
2
B
CV302
1U_0402_6.3V4Z
216-0774009-A11PARK_FCBGA631
PARKR1@
+SPV18
1
CV305
2
CV306
1U_0402_6.3V4Z
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size
Date:

SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet

1
16
of
52
UV1E
AA27
AB24
AB32
AC24
AC26
AC27
AD25
AD32
AE27
AF32
AG27
AH32
K28
K32
L27
M32
N25
N27
P25
P32
R27
T25
T32
U25
U27
V32
W25
W26
W27
Y25
Y32
M6
N11
N12
N13
N16
N18
N21
P6
P9
R12
R15
R17
R20
T13
T16
T18
T21
T6
U15
U17
U20
U9
V13
V16
V18
Y10
Y15
Y17
Y20
PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
GND#56
GND#57
GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#1
GND#2
GND#3 / EVDDQ#2
GND#4
GND#5
GND#6 / EVDDQ#3
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#85
GND#86
A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6
T11
R11
VSS_MECH#1
VSS_MECH#2
VSS_MECH#3
A32
AM1
AM32
GND
216-0774009-A11PARK_FCBGA631
PARKR1@
B
Compal Secret Data
Issued Date
2010/09/05
2011/09/05
Deciphered Date
Title
Size
Date:

SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
17
of
52
UV1C
D
MDA[0..63]
MDA[0..63]
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
+3VS
RV23
10K_0402_5%
@
Close to pin K26
TEST_EN
+1.5VS
RV41
40.2_0402_1%
RV19
10K_0402_5%
+MVREFDA
1
RV43
100_0402_1%
2
2
CV202
0.1U_0402_16V4Z
+MVREFDA
+MVREFSA
+1.5VS
RV48
2
240_0402_1% TEST_EN
RV49 1
RV52 1
Close to pin J26
2 150_0402_1%
2 240_0402_1%
+1.5VS
1
DRAM_RST
RV45
40.2_0402_1%
@
RV57 2
2
RV58 @
1 51_0402_5%
1
51_0402_5%
2 0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
K17
J20
H23
G23
G24
H24
J19
K19
J14
K14
J11
J13
H11
G11
J16
L15
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1
MAA[13..0]
DQMA_0
DQMA_1
DQMA_2
DQMA_3
DQMA_4
DQMA_5
DQMA_6
DQMA_7
E32
E30
A21
C21
E13
D12
E3
F4
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
DQMA#[7..0]
RDQSA_0
RDQSA_1
RDQSA_2
RDQSA_3
RDQSA_4
RDQSA_5
RDQSA_6
RDQSA_7
H28
C27
A23
E19
E15
D10
D6
G5
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
QSA[7..0]
WDQSA_0
WDQSA_1
WDQSA_2
WDQSA_3
WDQSA_4
WDQSA_5
WDQSA_6
WDQSA_7
H27
A27
C23
C19
C15
E9
C5
H4
QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7
QSA#[7..0]
ODTA0
ODTA1
L18
K16
ODTA0
ODTA1
19
19
CLKA0
CLKA0B
H26
H25
CLKA0
CLKA0#
19
19
CLKA1
CLKA1B
G9
H9
CLKA1
CLKA1#
19
19
RASA0B
RASA1B
G22
G17
RASA0#
RASA1#
19
19
CASA0B
CASA1B
G19
G16
CASA0#
CASA1#
19
19
CSA0B_0
CSA0B_1
H22
J22
CSA0#_0
19
CSA1B_0
CSA1B_1
G13
K13
CSA1#_0
19
CKEA0
CKEA1
K20
J17
CKEA0
CKEA1
19
19
MEM_CALRN0
NC/TESTEN#2
WEA0B
WEA1B
G25
H10
WEA0#
WEA1#
19
19
J8
K25
MEM_CALRP1/DPC_CALR
MEM_CALRP0
PX_EN
AB16
L10
DRAM_RST
K8
L7
CLKTESTA
CLKTESTB
MAA13
19
DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63
K26
J26
MVREFDA
MVREFSA
J25
K7
RSVD#2
G14
RSVD#3
G20
A_BA[2..0]
MAA[13..0] 19
A_BA[2..0] 19
DQMA#[7..0] 19
QSA[7..0] 19
QSA#[7..0] 19
216-0774009-A11PARK_FCBGA631
PARKR1@
+MVREFSA
@
CV320 1
1
CV321 @
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13/BA2
MAA_14/BA0
MAA_15/BA1
K27
J29
H30
H32
G29
F28
F32
F30
C30
F27
A28
C28
E27
G26
D26
F25
A25
C25
E25
D24
E23
F23
D22
F21
E21
D20
F19
A19
D18
F17
A17
C17
E17
D16
F15
A15
D14
F13
A13
C13
E11
A11
C11
F11
A9
C9
F9
D8
E7
A7
C7
F7
A5
E5
C3
E1
G7
G6
G1
G3
J6
J1
J3
J5
MEMORY INTERFACE
19
RV47
100_0402_1%
CV204
0.1U_0402_16V4Z
Debug Only, for clock observation

As short as possible
DRAM_RST#
1
19
RV50
1
2
51_0402_5%
DRAM_RST
1
RV51
10K_0402_5%
C236
68P_0402_50V8J
Issued Date
Check with ATI FAE
Compal Secret Data
2010/09/05
2011/09/05
Deciphered Date
Title
Size
Date:

SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
18
of
52
A_BA[2..0]
MDA4
MDA2
MDA1
MDA3
MDA5
MDA0
MDA7
MDA6
+VREFC_A2
+VREFD_A2
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDA18
MDA19
MDA21
MDA22
MDA20
MDA16
MDA17
MDA23
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
M8
H1
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
A_BA0
A_BA1
A_BA2
M2
N8
M3
BA0
BA1
BA2
CLKA0
CLKA0#
CKEA0
J7
K7
K9
CK
CK
CKE/CKE0
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
Group0
Group2
+1.5VS
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
MDA10
MDA13
MDA8
MDA15
MDA11
MDA14
MDA9
MDA12
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDA28
MDA26
MDA29
MDA27
MDA30
MDA24
MDA31
MDA25
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
+VREFC_A3
+VREFD_A3
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
A_BA0
A_BA1
A_BA2
M2
N8
M3
BA0
BA1
BA2
CLKA1
CLKA1#
CKEA1
J7
K7
K9
CK
CK
CKE/CKE0
ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
QSA5
QSA4
F3
C7
DQSL
DQSU
DQMA#5
DQMA#4
E7
D3
DML
DMU
QSA#5
QSA#4
G3
B7
DQSL
DQSU
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
Group1
Group3
+1.5VS
CLKA0
CLKA0#
CKEA0
CLKA0
CLKA0#
CKEA0
J7
K7
K9
CK
CK
CKE/CKE0
ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
QSA0
QSA2
F3
C7
DQSL
DQSU
DQMA#0
DQMA#2
E7
D3
ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#
A1
A8
C1
C9
D2
E9
F1
H2
H9
QSA1
QSA3
F3
C7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA#1
DQMA#3
E7
D3
DML
DMU
QSA#1
QSA#3
G3
B7
DQSL
DQSU
G3
B7
DQSL
DQSU
DRAM_RST#
T2
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
RV62
243_0402_1%
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
CV216
2
BA0
BA1
BA2
CLKA1
CLKA1#
CKEA1
J7
K7
K9
CK
CK
CKE/CKE0
A1
A8
C1
C9
D2
E9
F1
H2
H9
ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#
K1
L2
J3
K3
L3
ODT/ODT0
CS/CS0
RAS
CAS
WE
QSA7
QSA6
F3
C7
DQSL
DQSU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA#7
DQMA#6
E7
D3
DML
DMU
QSA#7
QSA#6
G3
B7
DQSL
DQSU
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
+1.5VS
D7
C3
C8
C2
A7
A2
B8
A3
MDA48
MDA52
MDA51
MDA54
MDA50
MDA55
MDA49
MDA53
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
Group7
Group6
+1.5VS
DRAM_RST# T2
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
CV233
96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96
+1.5VS
@
+1.5VS
96-BALL
SDRAM DDR3
+1.5VS
@
CV236
2
1U_0402_6.3V4Z
2
CV253
@
+1.5VS
1
CV211
RV78
4.99K_0402_1%
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
1U_0402_6.3V4Z
1
+VREFD_A3
1
CV212
RV74
4.99K_0402_1%
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
RV75
4.99K_0402_1%
0.1U_0402_16V4Z
2
+1.5VS
1U_0402_6.3V4Z
1
1
CV217
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
1
CV218
2
CV219
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
1
CV220
2
CV221
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
1
CV222
CV223
2
2
1U_0402_6.3V4Z
+VREFC_A4
+VREFD_A4
1
CV213
1
CV214
RV80
4.99K_0402_1%
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
+1.5VS
1U_0402_6.3V4Z
1
1
CV249
@
+VREFC_A3
1
CV208
RV79
4.99K_0402_1%
+VREFD_A2
+VREFC_A2
1
CV207
RV77
4.99K_0402_1%
1
CV210
CV209
RV76
0.1U_0402_16V4Z 4.99K_0402_1%
+VREFD_A1
+VREFC_A1
1
RV73
4.99K_0402_1%
RV72
4.99K_0402_1%
+1.5VS
RV71
4.99K_0402_1%
CV235
2
+1.5VS
RV64
243_0402_1%
RV70
4.99K_0402_1%
1U_0402_6.3V4Z
1
1
2
1U_0402_6.3V4Z
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
RV69
4.99K_0402_1%
2
CV232
2
1U_0402_6.3V4Z
M2
N8
M3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
RV68
4.99K_0402_1%
2
CV215
2
J1
L1
J9
L9
+1.5VS
+1.5VS
CV231
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A_BA0
A_BA1
A_BA2
Group4
MDA63
MDA58
MDA60
MDA59
MDA61
MDA56
MDA62
MDA57
RV67
4.99K_0402_1%
+1.5VS
2
1U_0402_6.3V4Z
B2
D9
G7
K2
K8
N1
N9
R1
R9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
E3
F7
F2
F8
H3
H8
G2
H7
RV66
4.99K_0402_1%
ZQ/ZQ0
RV63
243_0402_1%
96-BALL
SDRAM DDR3
@
+1.5VS
+1.5VS
1
CV252
0.01U_0402_25V7K
1U_0402_6.3V4Z
1
1
RESET
L8
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
Group5
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
RV65
4.99K_0402_1%
1
2
RV84 56_0402_1%
1U_0402_6.3V4Z
1
1
DRAM_RST# T2
MDA34
MDA32
MDA38
MDA35
MDA37
MDA36
MDA39
MDA33
VREFCA
VREFDQ
1
2
RV83 56_0402_1%
CLKA1#
ZQ/ZQ0
ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#
D7
C3
C8
C2
A7
A2
B8
A3
M8
H1
1
CLKA1
B1
B9
D1
D8
E2
E8
F9
G1
G9
96-BALL
SDRAM DDR3
@
+1.5VS
CV234
0.01U_0402_25V7K
RESET
L8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
18
18
18
18
18
1
2
RV82 56_0402_1%
DRAM_RST# T2
A1
A8
C1
C9
D2
E9
F1
H2
H9
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
+VREFC_A4
+VREFD_A4
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
CLKA0#
DQSL
DQSU
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
CLKA1
CLKA1#
CKEA1
MDA40
MDA45
MDA41
MDA43
MDA42
MDA46
MDA44
MDA47
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
2
1
2
RV81 56_0402_1%
ODT/ODT0
CS/CS0
RAS
CAS
WE
J1
L1
J9
L9
RV61
243_0402_1%
CLKA0
K1
L2
J3
K3
L3
18
18
+1.5VS 18
E3
F7
F2
F8
H3
H8
G2
H7
+1.5VS
DRAM_RST#
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#
DML
DMU
QSA#0
QSA#2
+1.5VS
18
BA0
BA1
BA2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
18
18
18
18
18
M2
N8
M3
18
18
18
A_BA0
A_BA1
A_BA2
UV5
M8
H1
A_BA[2..0]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
E3
F7
F2
F8
H3
H8
G2
H7
18
QSA#[7..0]
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
QSA#[7..0]
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
QSA[7..0]
VREFCA
VREFDQ
QSA[7..0]
18
UV3
UV4
+VREFC_A1 M8
+VREFD_A1 H1
DQMA#[7..0]
DQMA#[7..0]
18
UV2
MAA[13..0]
18
MDA[0..63]
MAA[13..0]
MDA[0..63]
18
18
CV224
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
1
CV237
2
CV225
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
1
CV226
2
CV238
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
1
CV239
2
CV227
2
1U_0402_6.3V4Z
CV254
@
1U_0402_6.3V4Z
1
CV240
2
2
1U_0402_6.3V4Z
CV228
1U_0402_6.3V4Z
1
CV241
CV229
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
CV242
2
1U_0402_6.3V4Z
CV243
2
1U_0402_6.3V4Z
1
CV230
2
1U_0402_6.3V4Z
CV255
@
+1.5VS
+1.5VS
1
0.1U_0402_16V4Z
1
1
CV177
CV176
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
CV178
CV182
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
CV179
CV183
0.1U_0402_16V4Z
1
CV181
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CV184
2
0.1U_0402_16V4Z
1
1
CV248
2
2
0.1U_0402_16V4Z
CV192
0.1U_0402_16V4Z
1
1
CV193
CV205
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
CV194
CV206
CV203
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CV245
0.1U_0402_16V4Z
1
1
CV260
CV244
2
2
0.1U_0402_16V4Z
+1.5VS
+1.5VS
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
1
1
CV250
CV257
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
CV251
0.1U_0402_16V4Z
1
CV258
CV256
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CV259
2
0.1U_0402_16V4Z
1
1
CV268
2
2
0.1U_0402_16V4Z
CV261
0.1U_0402_16V4Z
1
1
CV262
CV265
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
CV263
CV266
CV264
CV267
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
A
+1.5VS
+1.5VS
+1.5VS
10U_0603_6.3V
2
CV284
1
CV283
1
1
10U_0603_6.3V
CV282
10U_0603_6.3V
CV246
10U_0603_6.3V
+1.5VS
CV269
10U_0603_6.3V
CV247
10U_0603_6.3V
CV270
10U_0603_6.3V
Compal Secret Data
2
Issued Date
2010/09/05
2011/09/05
Deciphered Date
Title
Size
Date:

SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
19
of
52
CONFIGURATION STRAPS
GPU STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
+3VS
GPU_GPIO0
GPU_GPIO1
@ RV109
@RV109
@RV110
@
RV110
14
GPU_GPIO2
14
14
SOUT_GPIO8
SIN_GPIO9
Net Name
2
2
1 10K_0402_5%
1 10K_0402_5%
Straps Name
@RV111
@
RV111
1 10K_0402_5%
TX_PWRS_ENB
@ RV125
@RV125
@RV113
@
RV113
2
2
1 10K_0402_5%
1 10K_0402_5%
@RV114
@
RV114
1 10K_0402_5%
RV115
@ RV116
@RV116
@RV117
@
RV117
2
2
2
1 10K_0402_5%
1 10K_0402_5%
1 10K_0402_5%
14,22 VGA_CRT_HSYNC
14,22 VGA_CRT_VSYNC
@ RV119
@RV119
@RV118
@
RV118
2
2
1 10K_0402_5%
1 10K_0402_5%
RESERVED
GPIO_8_ROMSO
14 VSYNC_DAC2
14 HSYNC_DAC2
@ RV121
@RV121
@RV120
@
RV120
2
2
1 10K_0402_5%
1 10K_0402_5%
RESERVED
GPIO_21_BB_EN
VGA_DIS
GPIO_9_ROMSI
14
14
14 ROMSE_GPIO22
14
14
14
GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
GPU by the system BIOS
Pin Name
GPIO0
DESCRIPTION OF DEFAULT SETTINGS
GPU_GPIO0
TX_DEEMPH_EN
GPIO1
GPU_GPIO1
PCI Express Transmitter De-emphasis Enable

0: Tx de-emphasis disabled
1: Tx de-emphasis enabled
BIF_GEN2_EN_A
GPIO2
GPU_GPIO2
PCIE GNE2 ENABLED

0 = Advertises the PCIe device as 2.5 GT/s capable at power-on
1 = Advertises the PCIe device as 5.0 GT/s capable at power-on.
SOUT_GPIO8
N.C
SIN_GPIO9
GPU by VBIOS
ROMSE_GPIO22
GPIO_22_ROMCSB
BIOS_ROM_EN
GPIO22 = 0 (BIOS_ROM_EN = 0) GPIO22 = 1 (BIOS_ROM_EN = 1)

GPIO[13:11]
MEMORY SIZE
0 0 0
0 0 1
0 1 0
128MB
GPIO[13:11]
64MB
VGA Controller
0: VGA Controller capacity enabled
1: The device will not be recognized as the systems VGA controller
0 (Enable)
Enable external BIOS ROM device

0 - Disable external BIOS ROM device
1 - Enable external BIOS ROM device
VIP Device Strap Enable indicates to the software driver

0 - Driver would ignore the value sampled on VHAD_0 during reset
1 - Driver would use the value sampled at reset from VHAD_0 to
determine whether or not a VIP slave device is connected
RESERVED
H2SYNC
HSYNC_DAC2
RESERVED
AUD[1]
AUD[0]
HSYNC
VSYNC
VGA_CRT_HSYNC
VGA_CRT_VSYNC
0 0 1 (256M)
AUD[1:0]:
00 - No audio function;
01 - Audio for DisplayPort only;
10 - Audio for DisplayPort and HDMI if dongle is detected;
11 - Audio for both DisplayPort and HDMI.
0 0
RV138
0_0402_5%
1
RV141
0_0402_5%
@
CV304
0.1U_0402_16V4Z
0
0 (Internal pulldown)
VSYNC_DAC2
EC_SMB_DA2 24,38
2
+3VS
RESERVED
RESERVED
V2SYNC
EC_SMB_CK2 24,38
For Internal Thermal Sensor
0
5.0 GT/s capability will be
controlled by software
GPU_GPIO11
GPU_GPIO12
GPU_GPIO13
GPIO[13:11]
CONFIG(2:0)
VIP_DEVICE_STRAP_DIS
External VGA Thermal Sensor
SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

a) If BIOS_ROM_EN = 1, then Config[2:0] defines the ROM type
b) If BIOS_ROM_EN = 0, then Config[2:0] defines
the primary memory aperture size.
1 0 0
(M25P05A)
256MB
RECOMMENDED SETTINGS
Transmitter Power Savings Enable

0: 50% Tx output swing
1: Full Tx output swing
UV12 @
14 GPU_THERMAL_D+
1
14 GPU_THERMAL_D-
@
CV307
2200P_0402_50V7K
VDD
SCLK
D+
SDATA
D-
ALERT#
GND
THERM#
1
RV136
1
RV137
2
0_0402_5%
2
0_0402_5%
GPU_SMB_CK2 14
GPU_SMB_DA2 14
THERM#_VGA 14
STRAPS
PIN
GPU
Vendor Part Number#
Compal Part Number#
512M 64Mx16 (x4)
HYN H5TQ1G63BFR-12C-C
SA000032460
000
512M 64Mx16 (x4)
SAM
K4W1G1646E-HC12
SA000035700
001
1G 128Mx16 (x4)
HYN
H5TQ2G63BFR-12C
SA00003VS00
010
1G 128Mx16 (x4)
SAM
K4W2G1646C-HC12
SA00003MQ40
011
512M 64Mx16 (x4)
HYN H5TQ1G63BFR-12C-C
SA000032460
100
512M 64Mx16 (x4)
SAM
K4W1G1646E-HC12
SA000035700
101
1G 128Mx16 (x4)
HYN
H5TQ2G63BFR-12C
SA00003VS00
110
1G 128Mx16 (x4)
SAM
K4W2G1646C-HC12
SA00003MQ40
111
VRAM size
ADM1032ARMZ-2REEL_MSOP8
B
Park XT S3
VRAM_ID[2:0] DVDATA
(2,1,0)
VRAM_ID 2,1,0
Design Ready
RV124
10K_0402_5%
@
1
RV123
10K_0402_5%
@
RV122
10K_0402_5%
@
Need to check the VBIOS setting
RV127
10K_0402_5%
@
Design Ready
RV126
10K_0402_5%
@
VRAM_ID2 14
VRAM_ID1 14
VRAM_ID0 14
RV128
10K_0402_5%
@
Robson LP S3
+1.8VS
Compal Secret Data
2010/09/05
Issued Date
2011/09/05
Deciphered Date
Title
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Date:
SCHEMATICS,MB A6847
Rev
B
4019AP
Sheet
1
20
of
52
Clock Generator
+3VS_CK505
2
2
2
10U_0805_10V4Z
0.1U_0402_16V4Z
1
+1.5VS
FBMH1608HM601-T_0603
1
2
R126
0.1U_0402_16V4Z
1
1
1
C213
For SED
C214
2
1U_0402_6.3V4Z
C212
C251
47P_0402_50V8J
C219
C220
C221
C222
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C252
47P_0402_50V8J
CK_PWRGD
2N7002_SOT23-3 S
+1.5VS_CK505
+3VS_CK505
Silego Have Internal Pull-Up
+1.05VS_CK505
+3VS_CK505
H_STP_CPU#
10K_0402_5% 2
CLK_DOT
CLK_DOT#
1
1
1
27M_CLK_R
27M_SSC_R
CLK_48M_CR_R
24 CLK_SATA
24 CLK_SATA#
24 PCH_CLK_DMI
24 PCH_CLK_DMI#
H_STP_CPU#
1
2
3
4
5
6
7
8
VDD_USB_48
VSS_48M
DOT_96
DOT_96#
VDD_27
27MHZ
27MHZ_SS
USB_48
SCL
SDA
REF_0/CPU_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
CKPWRGD/PD#
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
VSS_27M
SATA
SATA#
VSS_SRC
SRC_1
SRC_1#
VDD_SRC_IO
CPU_STOP#
VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
VDD_SRC
24
23
22
21
20
19
18
17
33
PM_SMBCLK 11,12,24,33
CLK_14M_PCH 24
CPU_SEL 1
2
33_0402_5% R102
CLK_XTAL_IN
CLK_XTAL_OUT
CPU_SEL
CLK_BCLK 24
CLK_BCLK# 24
Y1
CLK_XTAL_IN
1
2
2
2
14.318MHZ_16PF_7A14300083
C223
C224
22P_0402_50V8J
22P_0402_50V8J
1
1
CPU_SEL
CPU_0/0#
0 (Default)
133MHz
133MHz
100MHz
100MHz
INVT_PWM_R
Q1B
2N7002DW-T/R7_SOT363-6
W=60mils
R112
10K_0402_5%
VGA_TXOUT0+
VGA_TXOUT0VGA_TXOUT1+
VGA_TXOUT1VGA_TXOUT2+
VGA_TXOUT2VGA_TXCLK+
VGA_TXCLK-
C233
0.1U_0402_16V4Z
INVT_PWM 38
1
R160
2
0_0402_5%
VGA_PWM 15
2
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
32
GND1
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
PACDN042Y3R_SOT23-3
VGA_EDID_CLK 14
VGA_EDID_DATA 14
INT_MIC_CLK
INT_MIC_DATA
INVT_PWM_R
BKOFF#_R
INT_MIC_CLK 36
INT_MIC_DATA 36
R114
BKOFF#_R
10K_0402_5%
+3VS
+LCDVDD_R
+LCD_INV
2
1
R137 33_0402_5%
BKOFF# 38
R113
10K_0402_5%
C232
0.1U_0402_16V4Z
B+
ACES_87242-3001-09
UMA PD 100K ohm

DIS PD 10K ohm
USB20_P11_R
USB20_N11_R
2
0_0402_5%
3
1
+LCD_VDD
15
15
15
15
15
15
15
15
1
@ R159
6 2
1
1
Q17
AO3413_SOT23
VGA_ENVDD
1
2
2
47K_0402_5% 1
C229
0.01U_0402_25V7K
1
R109
0.1U_0402_16V4Z
1
2
C231 CAM@
2
S
C228
0.1U_0402_16V7K
Q1A
2N7002DW-T/R7_SOT363-6
15
Camera
CPU_1/1#
D84 @
JLVDS
W=60mils
+3VS_LVDS_CAM
R120
100K_0402_5%
0_0603_5%
R398 1
2
CAM@
1 R106
CLK_XTAL_OUT
+1.5VS_CK505
+3VS
+3VS
+1.05VS
Remove C484 (for RF)
0618 --> change camera power rail to +3VS

W=20mils
1 R119
CK_PWRGD
TGND
+3VS
10K_0402_5% 2
LVDS / Int.Camera / Int.MIC Conn
R107
150_0603_5%
1 R105
IDT Have Internal Pull-Down
RTM890N-631-GRT QFN 32P
+LCD_VDD
10K_0402_5% 2
U5
+3VS_CK505
14
27M_CLK
14
27M_SSC
35 CLK_48M_CR
CLK_ENABLE# 49
C215
+1.5VS_CK505
R404 2 33_0402_5%
R405 2 33_0402_5%
2
R400
33_0402_5%
2
G
Q37
2
2
0.1U_0402_16V4Z
Add C213 for NALA eSATA transmit issue
+1.05VS_CK505
R110
10K_0402_5%
+1.05VS_CK505
C211
For SED
FBMH1608HM601-T_0603
10U_0805_10V4Z
0.1U_0402_16V4Z
1
2
R101
1
1
1
+1.05VS
C210
+3VS_CK505
C209
0.1U_0402_16V4Z
1
1
0.1U_0402_16V4Z
1
1
For SED
FBMH1608HM601-T_0603
1
2
R100
For SED
For SED
+3VS
24
24
Rated Current MAX:600mA
1.5A, 60mils
L2 2
1
FBMA-L11-201209-221LMA30T_0805
C234
68P_0402_50V8J
+LCDVDD_R
2 L1
1
0_0805_5%
1
C235
0.1U_0402_25V6
+LCD_VDD
1
C226
0.1U_0402_16V4Z
C227
4.7U_0805_10V4Z
remove choke co-layout for DFB request

4
27
USB20_N11
27
USB20_P11
R93 CAM@
1
2
0_0402_5%
R92 CAM@
1
2
0_0402_5%
USB20_N11_R
USB20_P11_R
Issued Date
Compal Secret Data
2010/09/05
Deciphered Date
2011/09/05
Title
SCHEMATICS,MB A6847
Custom
Rev
B
4019AP
Date:

G
Sheet
21
of
H
52
D5
D4
D3
CRT CONNECTOR
+3VS
C239
L5
1
2
NBQ100505T-800Y_0402
CRT_B_L
C240
CRT_G_L
1
C241
1
C242
1
C243
2.2P_0402_50V8C
1
C238
L4
1
2
NBQ100505T-800Y_0402
2.2P_0402_50V8C
R140
CRT_R_L
2.2P_0402_50V8C
R139
R138
DAN217_SC59
@
L3
1
2
NBQ100505T-800Y_0402
2.2P_0402_50V8C
VGA_CRT_B
2.2P_0402_50V8C
14
2.2P_0402_50V8C
VGA_CRT_G
2
1
150_0402_1%
14
2
1
150_0402_1%
VGA_CRT_R
2
1
150_0402_1%
14
DAN217_SC59
@
DAN217_SC59
@
+5VS
+CRT_VCC_R
+CRT_VCC
F1
30mil
1
1
2
RB491D_SOT23-3
1
1.1A_6V_MINISMDC110F-2
C237
If=1A
@ 0.1U_0402_16V4Z
2
D6
2
3
+CRT_VCC
2
0.1U_0402_16V4Z
2
R141
5
1
1
C244
JCRT
1
10K_0402_5%
1
L6
2
10_0402_5%
HSYNC
U6
SN74AHCT1G125GW_SOT353-5
D_CRT_VSYNC
1
L7
2
10_0402_5%
VSYNC
+CRT_VCC
1
C245
@
5
1
P
OE#
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
CRT_R_L
1
C246
@
HSYNC
CRT_B_L
+CRT_VCC
PAD
VSYNC
T47
CRT_DDC_CLK
14,20 VGA_CRT_VSYNC
T46
CRT_DDC_DAT
CRT_G_L
10P_0402_50V8J
D_CRT_HSYNC
10P_0402_50V8J
14,20 VGA_CRT_HSYNC
P
OE#
PAD
G
G
16
17
ALLTO_C10532-11505-L_15P-T
@
U7
SN74AHCT1G125GW_SOT353-5
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
+3VS
1
Q2B
14 VGA_CRT_CLK
1
C247
33P_0402_50V8K
2
@
14 VGA_CRT_DATA
R146 and R1472.2k-ohm
R147
2.2K_0402_5%
R146
2.2K_0402_5%
Q2A
+CRT_VCC
CRT_DDC_DAT
2N7002DW-T/R7_SOT363-6
CRT_DDC_CLK
2N7002DW-T/R7_SOT363-6
C249
C248
470P_0402_50V8J
33P_0402_50V8K
@
2 @
C250
470P_0402_50V8J
2 @
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
E
22
of
52
OSC
NC
OSC
32.768KHZ_12.5PF_Q13MC14610002
2
2
1U_0402_6.3V4Z
2
C290
1
15P_0402_50V8J
+RTCVCC
Integrated SUS 1.05V VRM Enable
1
R285
1
R275
High - Enable Internal VRs

PCH_INTVRMEN (must be always pulled high)
+RTCVCC
B13
D13
RTCX1
RTCX2
PCH_RTCRST#
C14
RTCRST#
SRTCRST#
SM_INTRUDER#
2
1M_0402_5%
PCH_INTVRMEN
2
330K_0402_5%
A16
INTRUDER#
A14
INTVRMEN
A30
HDA_BCLK
HDA_SYNC
AZ_SYNC
D29
HDA_SYNC
This signal has a weak internal pull down.

H=>On Die PLL is supplied by 1.5V
Die PLL is supplied by 1.8V
PCH_SPKR
HDA_SDO
P1
36 AZ_SDIN0_HD
This signal has a weak internal pull down.

This signal can't PU
remove SDN1 for MDC
HDA_RST#
G30
HDA_SDIN0
F30
HDA_SDIN1
E32
HDA_SDIN2
F32
@ R118 1K_0402_5%
1
2
AZ_SDOUT
HDA_SDIN3
B29
HDA_SDO
38 PWRME_CTRL#
remove CR_CPPE# for JM385
H32
HDA_DOCK_EN# / GPIO33
J30
HDA_DOCK_RST# / GPIO13
R288 1
36 AZ_BITCLK_HD
R290 1
36 AZ_SYNC_HD
ITPM Enabled
SPI_MOSI
PCH_JTAG_TCK
M3
JTAG_TCK
PCH_JTAG_TMS
K3
JTAG_TMS
PCH_JTAG_TDI
K1
JTAG_TDI
PCH_JTAG_TDO
J2
JTAG_TDO
PCH_JTAG_RST#
J4
TRST#
AZ_SYNC
2 33_0402_5%
R294 1
36 AZ_SDOUT_HD
AZ_BITCLK
2 33_0402_5%
R292 1
36 AZ_RST_HD#
2 33_0402_5%
AZ_RST#
2 33_0402_5%
AZ_SDOUT
FWH4 / LFRAME#
C34
LPC_FRAME# 38,39
LDRQ0#
LDRQ1# / GPIO23
A34
F34
SERIRQ
AB9
Internal: Pull down 20k
High = Enabled
Low = Disabled (Default)
2
R273
AH6
AH5
AH9
AH8
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AF11
AF9
AF7
AF6
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
AH3
AH1
AF3
AF1
+3VS
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
AD9
AD8
AD6
AD5
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
AD3
AD1
AB3
AB1
SATAICOMPO
AF16
SATAICOMPI
AF15
SATA_PRX_C_DTX_N4 32
SATA_PRX_C_DTX_P4 32
SATA_PTX_DRX_N4 32
SATA_PTX_DRX_P4 32
SATA ODD
remove eSATA SATA

+3VS
SATAICOMP
1
R295
SPI_CS1#
SATALED#
T3
SATA_LED#
AY1
SPI_MOSI
SATA0GP / GPIO21
Y9
PCH_GPIO21
SATA1GP / GPIO19
V1
PCH_GPIO19
SPI_MISO
1ST HDD
SPI_CS0#
2
37.4_0402_1%
+1.05VS
PCH_GPIO21
R302 2
1 10K_0402_5%
SATA_LED#
R301 2
1 10K_0402_5%
PCH_GPIO19
R306 1
2 10K_0402_5%
HM55R1@
4MB
For EMI
Place near U13
PCH_JTAG_RST#
R385
@ 10_0402_5%
@
R364
10K_0402_5%
PCH_SPI_CLK
@
C16
10P_0402_50V8J
C293
0.1U_0402_16V4Z
U13
VCC
HOLD
PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_MOSI
VSS
PCH_SPI_MISO
MX25L3205DM2I-12G SO8
2
1
R156
38,39
+3VS
@
R643
20K_0402_5%
1
1
@
R537
100_0402_5%
PCH_JTAG_TDI
Desktop Only
AY3
AV1
SERIRQ
2
10K_0402_5%
SATA_PTX_DRX_N1 32
SATA_PTX_DRX_P1 32
SPI_CLK
@
R535
100_0402_5%
PCH_JTAG_TDO
@
R536
200_0402_5%
@
R355
100_0402_5%
@
R363
200_0402_5%
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
+3VALW
1
2
1
PCH_JTAG_TMS
+3VALW
1
2
@
R386
200_0402_5%
+3VALW
AK7
AK6
AK11
AK9
AV3
IBEXPEAK-M QV20 A0_FCBGA1071

+3VALW
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
BA2
1PCH_SPI_MOSI
1K_0402_5%
PCH_SPI_MISO
C291
0.1U_0402_16V4Z
@ JRTC
LOTES_AAA-BAT-054-K01
SERIRQ
PCH_SPI_CS0#
+3VS
38,39
38,39
38,39
38,39
remove FELICA_PWR#
PCH_SPI_CLK
SPI
HDA_DOCK_EN#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
SPKR
C30
Flash Descriptor Security Overide

Low = Enabled
High = Disabled
D33
B33
C32
A32
AZ_BITCLK
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
1
R286
AZ_RST#
3
2
1
R277 1K_0402_5%
CHN202UPT SC-70
PCH_RTCX1
PCH_RTCX2
D17
26,36 PCH_SPKR
+3VL
PCH_SRTCRST#
*L=>On
+RTCBATT
D10
U11A
1
2PCH_SRTCRST# 1
R284 20K_0402_1%
1
C289
NC
J2
LPC
iME Setting.
Y3
2
1U_0402_6.3V4Z
SATA
1
C288
RTC schematic for non-chargeable
RTC
IHDA
JTAG
1
2PCH_RTCRST#
R282 20K_0402_1%
R283
10M_0402_5%
2
1
CMOS Setting, near DDR Door

JCMOS
+RTCVCC
C287
15P_0402_50V8J
2
1
PCH_JTAG_TCK
2
51_0402_5%
06/01 change R125 from 4.7K to 51 ohm
PCH Pin
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TCK
PCH_JTAG_RST#
PCH JTAG Enable

ES1
ES2
No Install
200ohm
No Install
100ohm
200ohm
200ohm
100ohm
100ohm
200ohm
200ohm
100ohm
100ohm
51ohm
51ohm
20Kohm
20Kohm
10Kohm
10Kohm
RefDes
R358
R535
R355
R354
R536
R537
R156
R643
R353
PCH JTAG Disable (Default)

ES1
ES2
No Install
No Install
No Install
No Install
No Install
No Install
No Install
No Install
20Kohm
No Install
No Install
10Kohm
51ohm
51ohm
No Install
No Install
No Install
No Install
Issued Date
Compal Secret Data
2010/09/05
Deciphered Date
2011/09/05
Title
Size
B
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
23
of
52
2 R229
2 R230
+3VALW
+3VS
1 2.2K_0402_5%
1 2.2K_0402_5%
Q3B
PCH_SMBDATA
R231
R232
Q3A
PCH_SMBCLK
4.7K_0402_5%
4.7K_0402_5%
2N7002DW-T/R7_SOT363-6
PM_SMBCLK 11,12,21,33
2N7002DW-T/R7_SOT363-6
U11B
AU30
AT30
AU32
AV32
PERN3
PERP3
PETN3
PETP3
remove NewCard PCIE
remove JET PCIE
remove CardReader PCIE
NC
LAN
34
34
CLK_LAN#
CLK_LAN
CLKREQ_LAN#
34 CLKREQ_LAN#
WLAN
33
33
CLKREQ_WLAN#
33 CLKREQ_WLAN#
remove NEWCARD CLK

B
+3VS
1
10K_0402_5%
1
10K_0402_5%
2
R244
PCH_GPIO20
2
R248
CLKREQ_WLAN#
BA32
BB32
BD32
BE32
PERN4
PERP4
PETN4
PETP4
BF33
BH33
BG32
BJ32
PERN5
PERP5
PETN5
PETP5
BA34
AW34
BC34
BD34
PERN6
PERP6
PETN6
PETP6
AT34
AU34
AU36
AV36
PERN7
PERP7
PETN7
PETP7
BG34
BJ34
BG36
BJ36
PERN8
PERP8
PETN8
PETP8
AK48
AK47
CLKOUT_PCIE0N
CLKOUT_PCIE0P
P9
AM43
AM45
CLK_WLAN#
CLK_WLAN
form CLKREQ_NEW# to PCH_GPIO20
U4
AM47
AM48
PCH_GPIO20
N4
remove JET CLK
AH42
AH41
PCH_GPIO25
A8
AM51
AM53
PCH_GPIO26
SMBDATA
M9
PCIECLKRQ1# / GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P
PCH_SMBCLK
C8
PCH_SMBDATA
PCH_GPIO60
SML0CLK
C6
PCH_SMLCLK0
SML0DATA
G8
PCH_SMLDATA0
SML1ALERT# / GPIO74
M14
PCH_GPIO74
SML1CLK / GPIO58
E10
PCH_SMLCLK1
SML1DATA / GPIO75
G12
PCH_SMLDATA1
CL_CLK1
T13
CL_DATA1
T11
CL_RST1#
T9
H1
AJ50
AJ52
CLKREQ_LAN#
PCH_GPIO44
1
10K_0402_5%
2
R245
PCH_GPIO25
1
10K_0402_5%
2
R249
PCH_GPIO26
1
10K_0402_5%
2
R250
PCH_GPIO44
1
10K_0402_5%
2
R251
PCH_GPIO56
AK53
AK51
form CLKREQ_CR# to PCH_GPIO26

PCH_GPIO56
H6
form CLKREQ_JET# to PCH_GPIO25
AT1
AT3
PCH_CLK_DMI# 21
PCH_CLK_DMI 21
CLKIN_BCLK_N
CLKIN_BCLK_P
AP3
AP1
CLK_BCLK# 21
CLK_BCLK 21
CLKIN_DOT_96N
CLKIN_DOT_96P
F18
E18
CLK_DOT# 21
CLK_DOT 21
AH13
AH12
CLK_SATA# 21
CLK_SATA 21
P41
CLK_14M_PCH 21
CLKIN_PCILOOPBACK
CLKOUT_PCIE4N
CLKOUT_PCIE4P
P13
CLKOUT_PCIE5N
CLKOUT_PCIE5P
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ# / GPIO56
EC_SMB_CK2 20,38
CLKREQ_PEG#
AW24
BA24
REFCLK14IN
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
AF38
CLKOUTFLEX0 / GPIO64
T45
P43
T42
N50
2.2K_0402_5%
2.2K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
2
2
2
2
2
1
1
1
1
1
@
1
2
R260
10K_0402_5%
1
2
R262
10K_0402_5%
+3VALW
R247
2
1M_0402_5%
1
Y2
CLK_PCILOOP 27
C277
PCH_X2
25MHZ_20PF_7A25000012
27P_0402_50V8J
2
PCH_X1
PCH_X2
XCLK_RCOMP 1
2
R252 90.9_0402_1%
R237
R238
R239
R240
R241
FROM CLK GEN FOR: 133/100/96/14.318 MHZ
PCH_X1
J42
AH51
AH53
PCH_SMLCLK0
PCH_SMLDATA0
PCH_GPIO60
PCH_GPIO74
EC_LID_OUT#
CLKREQ_PEG# 14
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
CLKREQ_PEG#
CLK_PEG# 5
CLK_PEG 5
CLKOUT_PCIE3N
CLKOUT_PCIE3P
EC_SMB_DA2 20,38
+3VALW
AN4
AN2
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
4
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
CLKOUT_DMI_N
CLKOUT_DMI_P
Q4B
PCH_SMLCLK1
CLK_PCIE_VGA# 13
CLK_PCIE_VGA 13
CLKIN_DMI_N
CLKIN_DMI_P
+3VS
1 2.2K_0402_5%
1 2.2K_0402_5%
PCH_SMLDATA1
AD43
AD45
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
Clock Flex
2
R246
2 R233
2 R234
+3VALW
+3VALW
1
10K_0402_5%
EC_LID_OUT# 38
Q4A
PEG_A_CLKRQ# / GPIO47
CLKOUT_PCIE1N
CLKOUT_PCIE1P
H14
J14
SML0ALERT# / GPIO60
EC_LID_OUT#
PERN2
PERP2
PETN2
PETP2
SMBCLK
B9
AW30
BA30
PCIE_PTX_WLANRX_N2 BC30
PCIE_PTX_WLANRX_P2 BD30
SMBALERT# / GPIO11
SMBus
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
PERN1
PERP1
PETN1
PETP1
Link
C274 2
C275 2
1 0.1U_0402_16V7K
1 0.1U_0402_16V7K
Controller
For WLAN
PCIE_PRX_WLANTX_N2
PCIE_PRX_WLANTX_P2
PCIE_PTX_C_WLANRX_N2
PCIE_PTX_C_WLANRX_P2
C371 2
C340 2
PEG
33
33
33
33
PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_C_LANRX_N1
PCIE_PTX_C_LANRX_P1
BG30
BJ30
BF29
BH29
PCI-E*
34
34
34
34
For LAN
PCIE_PRX_C_LANTX_N1
PCIE_PRX_C_LANTX_P1
PCIE_PTX_LANRX_N1
PCIE_PTX_LANRX_P1
From CLK BUFFER
C278
27P_0402_50V8J
+1.05VS
C277
@
0_0402_5%
Note: Stuff 0 ohm if

25MHz crystal un-stuff
for EMI request

@
CLK_PCILOOP
@
1
R125
2
10_0402_5%
HM55R1@
CLK_14M_PCH
@
1
2
R70
100_0402_5%
C265 22P_0402_50V8J
@
2
1
C206 100P_0402_50V8J
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size
B
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
24
of
52
PCH_SUSPWRDN
2
10K_0402_5%
PCH_LOW_BAT#
2
10K_0402_5%
IBEX_RI#
2
10K_0402_5%
2
R329
2
R322
2
R323
PM_PWROK
1
10K_0402_5%
PWROK
1
10K_0402_5%
LAN_RST#
1
10K_0402_5%
BC24
BJ22
AW20
BJ20
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
6
6
6
6
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
BD24
BG22
BA20
BG20
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
6
6
6
6
DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3
BE22
BF21
BD20
BE18
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
6
6
6
6
DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
BD22
BH21
BC20
BD18
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
1
R311
+1.05VS
BH25
DMI_ZCOMP
BF25
DMI_IRCOMP
Close to PCH
2
0_0402_5%
5 XDP_DBRESET#
38,49
XDP_DBRESET#
T6
VGATE
VGATE
VGATE
M6
PWROK
B17
1
R321
2
0_0402_5%
LAN_RST#
K5
A10
D9
5 DRAMPWROK
PCH_RSMRST#
38 PCH_SUSPWRDN
C16
PCH_SUSPWRDN
38 PBTN_OUT#
38,44
ACIN
1
R324
FDI_INT
BJ14
FDI_FSYNC0
BF13
FDI_FSYNC1
BH13
FDI_LSYNC0
BJ12
FDI_LSYNC1
BG14
1
R689
1
R691
2
1K_0402_5%
2
1K_0402_5%
PCH_ACIN
2
330K_0402_5%
D26
1
2
PCH_LOW_BAT#
J12
PCH_WAKE#
CLKRUN# / GPIO32
Y1
PM_CLKRUN#
SUS_STAT# / GPIO61
P8
SUS_STAT#
SUSCLK / GPIO62
F3
EC_CLK
SLP_S5# / GPIO63
E4
PM_SLP_S5# 38
SLP_S4#
H7
PM_SLP_S4# 38
SLP_S3#
P12
PM_SLP_S3# 38
SLP_M#
K8
TP23
N2
SYS_PWROK
PWROK
MEPWROK
LAN_RST#
DRAMPWROK
RSMRST#
+3VALW
BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12
WAKE#
IN2
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
SYS_RESET#
PM_PWROK
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12
1
R256
+3VS
0.1U_0402_16V4Z
1
2
C272
U12
1 IN1
38
DMI_COMP
2
49.9_0402_1%
System Power Management
1
R316
1
R318
1
R320
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
FDI
+3VALW
6
6
6
6
DMI
U11C
PCH_WAKE#
PCH_WAKE# 34
2
R319
1
8.2K_0402_5%
2
R313
1
10K_0402_5%
+3VALW
+3VS
PADT38
PADT38
EC_CLK 38
For EC Crystal cost down
M1
SUS_PWR_DN_ACK / GPIO30
P5
PWRBTN#
P7
ACPRESENT / GPIO31
A6
BATLOW# / GPIO72
BJ10
PMSYNCH
PMSYNCH 5
CH751H-40PT_SOD323-2
IBEX_RI#
F14
RI#
SLP_LAN# / GPIO29
+3VALW
2
1K_0402_5%
2 R325
1
E
MMBT3906_SOT23-3
RSMRST# circuit
PCH_RSMRST#
0716 --> Unmount : R327, Q26,

D15A, D15B, R328, R690
Mount : R325, D29, D28
D28
43,45
POK
D15B @
BAV99DW-7_SOT363
1
R327
@ 4.7K_0402_5%
@ D15A
BAV99DW-7_SOT363
+3VALW
PWROK
PCH_RSMRST#
2
1
R326
10K_0402_5%
Q26 1
@
38 EC_RSMRST#
HM55R1@
D29
0_0402_5%
for abnormal shutdowm from s3 resume
1
2
@ R328
2.2K_0402_5%
Compal Secret Data
1
@ R690
F6
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size
B
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
25
of
52
U11D
T48
T47
L_BKLTEN
L_VDD_EN
Y48
2 R266
1CRT_IREF
1K_0402_1%
L_CTRL_CLK
L_CTRL_DATA
AP39
AP41
LVD_IBG
LVD_VBG
AT43
AT42
LVD_VREFH
LVD_VREFL
AV53
AV51
LVDSA_CLK#
LVDSA_CLK
BB47
BA52
AY48
AV47
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
BB48
BA50
AY49
AV48
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
AP48
AP47
LVDSB_CLK#
LVDSB_CLK
AY53
AT49
AU52
AT53
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
AY51
AT48
AU50
AT51
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
AA52
AB53
AD53
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
Y53
Y51
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
SDVO_INTN
SDVO_INTP
BF45
BH45
T51
T53
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
BG44
BJ44
AU38
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38
DDPC_CTRLCLK
DDPC_CTRLDATA
Y49
AB49
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
BE44
BD44
AV40
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36
R68
100K_0402_5%
1
2
For INTEL issue (pending interrupts from the PCH for unused HDMI ports)
DDPD_CTRLCLK
DDPD_CTRLDATA
V51
V53
AD48
AB51
SDVO_STALLN
SDVO_STALLP
SDVO_CTRLCLK
SDVO_CTRLDATA
Digital Display Interface
AB46
V48
LVDS
T15 PAD
L_DDC_CLK
L_DDC_DATA
BJ46
BG46
BJ48
BG48
BC46
BD46
AT38
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36
R343 100K_0402_5%
1
2
U50
U52
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
CRT
L_BKLTCTL
AB48
Y45
SDVO_TVCLKINN
SDVO_TVCLKINP
R77
100K_0402_5%
2
HM55R1@
PCH Strap Pin

B

During Reset: HZ
Initial: Low
+3VS
@
PCH_SPKR
1
2
R269
1K_0402_5%
PCH_SPKR 23,36
Internal: Pull up 20k

During Reset: High
Initial: High
1K_0402_5% 2
1 R270
PCI_GNT#0
1K_0402_5% 2
1 R271
PCI_GNT#1
PCI_GNT#1 27

During Reset: High
Initial: High
2
R272
1
1K_0402_5%
PCI_GNT#3
NO REBOOT Strap
+1.8VS_PCH_NAND
PCH_SPKR Low= Disable

High= Enable
0
0
1
1
0
1
0
1
Boot BIOS Loaction
1
1K_0402_5%
NV_ALE
NV_ALE 27
2
R268
NV_CLE
1
1K_0402_5%
NV_CLE 27
LPC
Reserved (NAND)
PCI
SPI (Default)
Danbury Technology Enabled

NV_ALE
2
R267
Boot BIOS Strap

PCI_GNT#1 PCI_GNT#0
PCI_GNT#0 27

During Reset: Low
Initial: Low

During Reset: Low
Initial: Low
High = Enabled
Low = Disabled (Default)
DMI Termination Voltage

NV_CLE
Low= Set to Vss (Default)

High= Set to Vcc
PCI_GNT#3 27

During Reset: High
Initial: High
A16 Swap Override Strap

PCI_GNT#3
Low= A16 swap override Enable

High= A16 swap override Disable
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Custom
SCHEMATICS,MB A6847
Rev
B
4019AP
Date:
Sheet
1
26
of
52
@
1
R253
U11E
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
F51
A46
B45
M53
REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
F48
K45
F36
H53
GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
B41
K53
A36
A48
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
RP2
1
2
3
4
8
7
6
5
PCI_PIRQH#
PCI_TRDY#
PCI_FRAME#
PCI_PIRQA#
8.2K_0804_8P4R_5%
RP3
1
2
3
4
8
7
6
5
PCI_STOP#
PCI_PIRQE#
PCI_PIRQC#
PCI_PIRQG#
8.2K_0804_8P4R_5%
GNT2#: Not pull low, internal pull up 20K
26
26
PCI_GNT#0
PCI_GNT#1
26
PCI_GNT#3
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
+3VS
RP4
1
2
3
4
8
7
6
5
T37 PAD
PCI_REQ#3
PCI_PIRQF#
PCI_PIRQB#
PCI_REQ#0
8.2K_0804_8P4R_5%
+3VS
TP_PCI_RST#
8
7
6
5
PCI_DEVSEL#
PCI_PERR#
PCI_SERR#
PCI_PLOCK#
SERR#
PERR#
PCI_IRDY#
PCI_DEVSEL#
PCI_FRAME#
A42
H44
F46
C46
IRDY#
PAR
DEVSEL#
FRAME#
PCI_PLOCK#
D49
PLOCK#
PCI_STOP#
PCI_TRDY#
8.2K_0804_8P4R_5%
13,33,34,38,39 PLT_RST#
39 CLK_PCI_DDR
38 CLK_PCI_EC
24 CLK_PCILOOP
PCIRST#
E44
E50
RP5
1
2
3
4
K6
PCI_SERR#
PCI_PERR#
2
1 CLK_SIO
22_0402_5%
R280
2
1 CLK_EC
22_0402_5%
R281
2
1 CLK_PCH
22_0402_5% R279
D41
C48
STOP#
TRDY#
M7
PME#
D5
PLTRST#
N52
P53
P46
P51
P48
NV_ALE
NV_CLE
BD3
AY6
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
NV_RCOMP
AU2
NV_RB#
AV7
NV_WR#0_RE#
NV_WR#1_RE#
AY8
AY5
NV_WE#_CK0
NV_WE#_CK1
AV11
BF5
5 BUF_PLT_RST#
IN2
PLT_RST#
R51
100K_0402_5%
R129
100K_0402_5%
@
NV_ALE 26
NV_CLE 26
NV_RCOMP
@
1
2
R276
32.4_0402_1%
C
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24
USBRBIAS#
B25
USBRBIAS
D25
USBBIAS
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
N16
J16
F16
L16
E14
G16
F12
T15
USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
EXP_CPPE#
IN1
G38
H51
B37
A44
8.2K_0804_8P4R_5%
U8
C477
0.1U_0402_16V4Z
1
2
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
add PCI_REQ#2 for non-ODD_EN#
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6
USB
PCI_REQ#1
PCI_REQ#2
PCI_PIRQD#
PCI_IRDY#
PCI
8
7
6
5
NV_DQS0
NV_DQS1
AV9
BG8
+3VS
C/BE0#
C/BE1#
C/BE2#
C/BE3#
RP1
1
2
3
4
AY9
BD1
AP15
BD8
J50
G42
H47
G34
+3VS
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
NVRAM
H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36
2
0_0402_5%
USB20_N0
USB20_P0
USB20_N1
USB20_P1
32
32
32
32
USB-LIGHT1
USB-LIGHT2
USB-Left1
remove eSATA
remove NewCard
remove BT
HM55 USB port6/7 NC

remove FingerPr
remove FELICA
USB20_N10
USB20_P10
USB20_N11
USB20_P11
35
35
21
21
Card reader(2 in 1)
Int. Camera
remove 3G/TV#1
USB20_N13 33
USB20_P13 33
WLAN
+3VALW
2
R278
1
22.6_0402_1%
Within 500 mils
RP6
USB_OC#6
USB_OC#4
USB_OC#0
USB_OC#5
(USB-Right)
USB_OC#0 32,38
4
3
2
1
5
6
7
8
10K_0804_8P4R_5%
RP8
USB_OC#2
USB_OC#1
USB_OC#3
EXP_CPPE#
HM55R1@
4
3
2
1
5
6
7
8
10K_0804_8P4R_5%
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size
B
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
27
of
52
pull down 100k to GND

U11F
PCH_GPIO6
D37
TACH2 / GPIO6
LAN_PHY_PWR_CTRL / GPIO12
A20GATE
PCH_GPIO15
T7
GPIO15
PCH_GPIO16
AA2
SATA4GP / GPIO16
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AM3
CLK_CPU_BCLK# 5
PCH_GPIO17
F38
TACH0 / GPIO17
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
AM1
CLK_CPU_BCLK 5
TACH3 / GPIO7
F10
GPIO8
PCH_GPIO27
1
1K_0402_5%
PCH_GPIO28
Y7
NBQAA 11.6/13.3"
C
NBQAA 14"
ID1
33
GPIO24
AB12
GPIO27
V13
GPIO28
M11
STP_PCI# / GPIO34
remove BT_RST#
NALAA 17.3"
+3VS
1
2
10K_0402_5%
BT_PWR#
R261
AB7
PROJECT_ID1
AB13
38
RST_GATE
THM_ALT#
1
R416
1
R415
@
@
PECI
RCIN#
U2
T1
PROCPWRGD
BE10
THRMTRIP#
BD10
TP1
BA22
SATA3GP / GPIO37
TP2
AW22
SATA2GP / GPIO36
SLOAD / GPIO38
TP3
BB22
P3
SDATAOUT0 / GPIO39
TP4
AY45
LVDS_SEL
H3
TP5
AY46
RST_GATE
F1
TP6
AV43
PCH_GPIO48
AB6
SDATAOUT1 / GPIO48
TP7
AV45
THM_ALT#
AA4
SATA5GP / GPIO49
TP8
AF13
GPIO57
TP9
M18
TP10
N18
TP11
AJ24
TP12
AK41
TP13
AK42
TP14
M32
TP15
N32
TP16
M30
TP17
N30
TP18
H12
TP19
AA23
NC_1
AB45
NC_2
AB38
NC_3
AB42
NC_4
AB41
NC_5
T39
A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BE53
BF1
BF53
BH1
BH2
BH52
BH53
BJ1
BJ2
BJ4
BJ49
BJ5
BJ50
BJ52
BJ53
D1
D2
D53
E1
E53
change Netname from

RF_OFF# to PCH_GPIO17
change R254 to 10k and

Netname from CIR_EN# to PCH_GPIO39
change Netname from

ISDBT_DET to PCH_GPIO39
add R261 10k

for BT fun
PECI
KB_RST#
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
INIT3_3V#
TP24
HM55R1@
LVDS_SEL=H
for Single Channel LVDS
KB_RST# 38
H_PWRGOOD 5
THRMTRIP_PCH#
1
R212
2
56_0402_1%
H_THERMTRIP# 5
1
R210
2
+VTT
56_0402_1%
C
V3
F8
GATEA20 38
SATACLKREQ# / GPIO35
PCH_GPIO39
PCH_GPIO57
GATEA20
BG10
PCH_GPIO38
+3VALW
EC_SMI#
1
2
R225
10K_0402_5%
1
2 PCH_GPIO57
R226
10K_0402_5%
1
2 PCH_GPIO15
R227
1K_0402_5%
1
2 PCH_GPIO28
R242
10K_0402_5%
1
2 LVDS_SEL
R222
10K_0402_5%
1
2 RST_GATE
R223
10K_0402_5%
1
2 PCH_GPIO12
10K_0402_5% R219
V6
PROJECT_ID0
*NWQAA 16"
1
2 PCH_GPIO1
10K_0402_5% R214
1
2 PCH_GPIO6
10K_0402_5% R218
EC_SCI#
1
2
10K_0402_5% R224
1
2 PCH_GPIO16
10K_0402_5% R221
1
2 PCH_GPIO17
10K_0402_5% R220
BT_DET#
1
2
8.2K_0402_5% R215
1
2 PCH_GPIO38
10K_0402_5% R217
1
2 PCH_GPIO39
10K_0402_5% R254
1
2 PROJECT_ID0
10K_0402_5% R255
1
2 PROJECT_ID1
10K_0402_5% R216
1
2 PCH_GPIO48
10K_0402_5% R257
1
2 THM_ALT#
10K_0402_5% R259
BT_PWR#
SCLOCK / GPIO22
H10
PROJECT_ID
ID0
K9
J32
EC_SMI#
BT_DET#
Name
AF48
AF47
PCH_GPIO12
EC_SCI#
EC_SMI#
AH45
AH46
CLKOUT_PCIE7N
CLKOUT_PCIE7P
EC_SCI#
2
R274
CLKOUT_PCIE6N
CLKOUT_PCIE6P
MISC
TACH1 / GPIO1
38
On-Die PLL VR
PCH_GPIO27
C38
38

During Reset: Low
Initial: Low
High = Enabled (Default)

Low = Disabled
BMBUSY# / GPIO0
PCH_GPIO1
CPU
GPIO15
a Strong pull up may be needed
for GPIO Functionality
Y3
RSVD

During Reset: High
Initial: High
PCH_HDMI_HPD
GPIO
Not pull down
NCTF
R189 100K_0402_5%
1
2
GPIO8
P6
C10
Not pull low

internal pull up
During Reset: High
Initial: High
Compal Secret Data
2 PROJECT_ID0
10K_0402_5%
2 PROJECT_ID1
10K_0402_5%
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size
B
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
28
of
52
Add R52 for CRT wave issue at pre-MP

+1.05VS
C294
1U_0402_6.3V4Z
+3VS
2
C310
1
0.1U_0402_16V4Z
VCCAPLLEXP
VSSA_DAC[2]
AF51
AN30
AN31
VCCIO[54]
VCCIO[55]
AN35
VCC3_3[1]
AT22
VCCVRM[1]
BJ18
VCCFDIPLL
AM23
VCCIO[1]
LVDS
C296
0.01U_0402_25V7K
1
C297
0.1U_0402_16V4Z
R52
1
2
0_0603_5%
C298
10U_0805_10V4Z
L12
1
2.2_0603_1%
Change L12 to 2.2 ohm

for CRT issue at pre-MP
close to AE50
AH39
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
AP43
AP45
AT46
AT45
+3VS
+1.8VS
+3VS
375mA
VCC3_3[2]
AB34
VCC3_3[3]
AB35
VCC3_3[4]
AD35
C300
0.01U_0402_25V7K
C299
0.01U_0402_25V7K
2
0.1U_0402_16V4Z
C303
1
close to AB34
+1.8VS
3062mA
196mA VCCVRM[2]
AT24
VCCDMI[1]
AT16
VCCDMI[2]
AU16
61mA
375mA
37mA
+VTT
+PCH_VCCDMI
156mA
FDI
+1.05VS
AF53
AH38
HVCMOS
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO[50]
VCCIO[51]
VCCIO[52]
VCCIO[53]
40mA
DMI
AN20
AN22
AN23
AN24
AN26
AN28
BJ26
BJ28
AT26
AT28
AU26
AU28
AV26
AV28
AW26
AW28
BA26
BA28
BB26
BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28
BH27
VCCIO[24]
+1.8VS
VSSA_DAC[1]
+3VS_VCCADAC
VCCALVDS
PCI E*
BJ24
2
10U_0805_10V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
2
1U_0402_6.3V4Z
AE52
VSSA_LVDS
NAND / SPI
AK24
1
C304
1
C305
1
C306
1
C307
1
C308
VCCADAC[2]
> 1mA
59mA
+1.05VS
AE50
1432mA
+1.05VS
VCCADAC[1]
69mA
CRT
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCC CORE
C295
10U_0805_10V4Z
AB24
AB26
AB28
AD26
AD28
AF26
AF28
AF30
AF31
AH26
AH28
AH30
AH31
AJ30
AJ31
+3VS
POWER
U11G
VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]
AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15
1
R335
2
0_0603_5%
C309
1U_0402_6.3V4Z
close to AT16
+1.8VS_PCH_NAND
+1.8VS
1
R338
2
0_0603_5%
C311
0.1U_0402_16V4Z
1
close to Ak13
+3VS
85mA
VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]
HM55R1@
AM8
AM9
AP11
AP9
2
C313
close to AM8
0.1U_0402_16V4Z
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size
B
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
29
of
52
POWER
1
C323
22U_0805_6.3V6M
1
C327
+1.05VS
VCCME[2]
AD41
VCCME[3]
AF43
VCCME[4]
AF41
VCCME[5]
C324
1U_0402_6.3V4Z
+VCCRTCEXT
2
0.1U_0402_16V4Z
VCCME[6]
V39
VCCME[7]
V41
VCCME[8]
V42
VCCME[9]
Y39
VCCME[10]
Y41
VCCME[11]
Y42
VCCME[12]
V9
DCPRTC
R349 0_0603_5%
1
2
C329
1U_0402_6.3V4Z
L18 1
2
10UH_LB2012T100MR_20%
C80
10U_0805_10V4K
+1.05VS_PCHDPLL_A
R347
0_0603_5%
@
2
VCCVRM[3]
196mA
AU24
+1.8VS
C82
10U_0805_10V4K
C332
1U_0402_6.3V4Z
+1.05VS
1
C334
1U_0402_6.3V4Z
163mA
1849mA
AF42
Reseve R349 for L17 Filter Cap.

C
VCCME[1]
AD39
68mA
BB51
BB53
VCCADPLLA[1]
VCCADPLLA[2]
69mA
+1.05VS_PCHDPLL_B
BD51
BD53
VCCADPLLB[1]
VCCADPLLB[2]
1U_0402_6.3V4Z
1
1
AH23
AJ35
AH35
VCCIO[21]
VCCIO[22]
VCCIO[23]
AF34
VCCIO[2]
C335
2
C336
2
change cap to 10uf for cost
2
1U_0402_6.3V4Z
Short AF34, AH34 and AF32 power

for HDMI Deep Color
AH34
VCCIO[3]
AF32
VCCIO[4]
1
C338
+VCCSST
2
0.1U_0402_16V4Z
V12
DCPSST
1
C341
2 +V1.1A_INT_VCCSUS Y22
0.1U_0402_16V4Z
DCPSUS
VCCSUS3_3[28]
U23
VCCIO[56]
V23
+1.05VS
V5REF_SUS
F24
+PCH_VCC5REFSUS
> 1mA
> 1mA
375mA
V5REF
K49
VCC3_3[8]
J38
VCC3_3[9]
L38
VCC3_3[10]
M36
VCC3_3[11]
N36
VCC3_3[12]
P36
VCC3_3[13]
U35
VCC3_3[14]
AD13
3062mA
31mA
VCCSATAPLL[1]
VCCSATAPLL[2]
+3VALW
C321
0.1U_0402_16V4Z
C325
0.1U_0402_16V4Z
+3VALW +5VALW
D16
R344
100_0402_1%
+3VS
2
C326
1
1U_0402_6.3V4Z
D17
+PCH_VCC5REF
+PCH_VCC5REF
R346
C
100_0402_1%
+3VS
+5VS
1
C447
22U_0805_6.3V6M
AD38
1U_0402_6.3V4Z
Near V39
1
DCPSUSBYP
1
C318
1U_0402_6.3V4Z
320mA
VCCLAN[2]
Y20
V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26
C316
If two VccME rails can be

combined, only total 2 x 22 F and
2 x 1 F caps are necessary
1
C322
22U_0805_6.3V6M
AF24
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]
1
C391
22U_0805_6.3V6M
VCCLAN[1]
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
3062mA
+1.05VS
AF23
52mA
+1.05VS
V24
V26
Y24
Y26
Near AD38
VCCACLK[2]
USB
1 +TP_PCH_VCCDSW
0.1U_0402_16V4Z
2
C320
VCCACLK[1]
AP53
PCI/GPIO/LPC
VccLAN may be grounded if Intel LAN is disabled
AP51
U11J
Clock and Miscellaneous
C330
1U_0402_6.3V4Z
C333
0.1U_0402_16V4Z
+3VS
2
C337
1
0.1U_0402_16V4Z
AK3
AK1
+1.05VS
2
0.1U_0402_16V4Z
VCCSUS3_3[29]
U19
VCCSUS3_3[30]
U20
VCCSUS3_3[31]
U22
VCCSUS3_3[32]
+3VS
1
C344
2
0.1U_0402_16V4Z
+VTT
Remove HDA power rail to +1.5V
1
C345
1
C346
1
C347
2
4.7U_0603_6.3V6K
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
1
C351
2
0.1U_0402_16V4Z
375mA
V15
VCC3_3[5]
V16
VCC3_3[6]
Y16
VCC3_3[7]
VCCIO[9]
196mA VCCVRM[4]
AT20
VCCIO[10]
AH19
VCCIO[11]
AD20
VCCIO[12]
AF22
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
AD19
AF20
AF19
AH20
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
AB19
AB20
AB22
AD22
SATA
1
C343
163mA
P18
PCI/GPIO/LPC
+3VALW
3062mA
> 1mA
AT18
V_CPU_IO[1]
AU18
V_CPU_IO[2]
CPU
AH22
1849mA
VCCRTC
1
C348
1
C349
2
1U_0402_6.3V4Z
2mA
HDA
A12
RTC
+RTCVCC
6mA
VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]
VCCSUSHDA
HM55R1@
+1.8VS
+1.05VS
1
+1.05VS
AA34 +PCH_VCCME1
Y34 +PCH_VCCME2
Y35 +PCH_VCCME3
AA35 +PCH_VCCME4
L30
+VCC_HDA
1
2
0.1U_0402_16V4Z
C342
1U_0402_6.3V4Z
R351
R352
R353
R354
1
1
1
1
2
2
2
2
R356 1
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
2 0_0402_5%
+3VALW
A
C350
1U_0402_6.3V4Z
Remove VCCSUSHDA can be

either 1.5V or 3.3V
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Custom
SCHEMATICS,MB A6847
Rev
B
4019AP
Date:
Sheet
1
30
of
52
U11I
AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BB5
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]
H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14
U11H
VSS[0]
AA19
AA20
AA22
AM19
AA24
AA26
AA28
AA30
AA31
AA32
AB11
AB15
AB23
AB30
AB31
AB32
AB39
AB43
AB47
AB5
AB8
AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AD7
AE2
AE4
AF12
Y13
AH49
AU4
AF35
AP13
AN34
AF45
AF46
AF49
AF5
AF8
AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AH7
AJ19
AJ2
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AT5
AJ4
AK12
AM41
AN19
AK26
AK22
AK23
AK28
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47
HM55R1@
HM55R1@
Compal Secret Data
AB16
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Custom
SCHEMATICS,MB A6847
Rev
B
4019AP
Date:
Sheet
1
31
of
52
SATA HDD Conn.

+5VS
1.2A
1
SATA ODD Conn
Place closely JHDD SATA CONN.

1
C356
10U_0805_10V4Z
C357
0.1U_0402_16V4Z
C358
0.1U_0402_16V4Z
C359
0.1U_0402_16V4Z
JODD @
SSD HDD need 400mA for 3V(PHISON)

+3VS
+3VS rail reserve for SSD

1
C363
10U_0805_10V4Z
@
C364
0.1U_0402_16V4Z
@
C365
0.1U_0402_16V4Z
@
C366
0.1U_0402_16V4Z
@
15
14
GND
GND
GND
A+
AGND
BB+
GND
1
2
3
4
5
6
7
DP
+5V
+5V
MD
GND
GND
8
9
10
11
12
13
SATA_PTX_C_DRX_P4
SATA_PTX_C_DRX_N4
C378 1
C377 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PTX_DRX_P4 23
SATA_PTX_DRX_N4 23
SATA_PRX_DTX_N4
SATA_PRX_DTX_P4
C376 1
C375 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
+5VS
SANTA_206401-1_RV
JHDD @
GND
A+
AGND
BB+
GND
1
2
3
4
5
6
7
SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1
C369 1
C367 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PTX_DRX_P1 23
SATA_PTX_DRX_N1 23
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
C368 1
C370 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
+5VS
24
23
GND
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Place components closely ODD CONN.
1.1A
1
+3VS
2
1
C354
@
10U_0805_10V4Z 1U_0402_6.3V4Z
2
2
C352
10U_0805_10V4Z
C353
1
C355
0.1U_0402_16V4Z
C360
0.1U_0402_16V4Z
C
+5VS
SANTA_191201-1
this is temp. footprint
USB Conn. (2 Port)

Reserve for EMI request
@ R73
1
1.4A
38
USB_EN#
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
27
+USB_VCCA
U48
1
2
3
4
L53
W=60mils
USB20_N0
USB20_N0_R
@ 2
C361
RT9715BGS_SO8
W=60mils
W=60mils
C19
For EMI request

8
7
6
5
C18
220U_6.3V_M
2
+USB_VCCA
1
1000P_0402_50V7K
27
USB20_P0
USB20_P0_R
USB_OC#0 27,38
@ R86
1
C362
4.7U_0805_10V4Z
2 @
0.1U_0402_16V4Z
C20
2
1
WCM-2012-900T_0805
1
C21
0_0402_5%
2
USB-LIGHT1
1000P_0402_50V7K
JUSB1
1
2
3
4
USB20_N0_R
USB20_P0_R
Reserve for EMI request
VCC
DD+
GND
5
6
7
8
GND
GND
GND
GND
JUSB2
1
2
3
4
USB20_N1_R
USB20_P1_R
VCC
DD+
GND
@
GND
GND
GND
GND
5
6
7
8
ALLTOP C107L8-10405-L
D7@
USB-LIGHT2
1000P_0402_50V7K
ALLTOP C107L8-10405-L
0_0402_5%
2
@ R88
1
0.1U_0402_16V4Z
C22
2
1
+5VALW
+USB_VCCA
+
W=80mils
0_0402_5%
2
D8@
PJDLC05_SOT23-3
USB20_N1
27
USB20_P1
USB20_N1_R
USB20_P1_R
PJDLC05_SOT23-3
@ R87
1
WCM-2012-900T_0805
0_0402_5%
2
Issued Date
Compal Secret Data
2010/09/05
2011/09/05
Deciphered Date
Title
Size
Date:
L54
27
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet

1
32
of
52
PCIe Mini Card-WLAN/WiMax

Slot#1 Half PCIe Mini Card-WLAN/WiMax
BT_CRTL
HI
LO
BT_PWR#
LO
HI
BT_CTRL
24 CLKREQ_WLAN#
24
24
24 PCIE_PRX_WLANTX_N2
24 PCIE_PRX_WLANTX_P2
**If +3V_WLAN is +3VS, please

remove D24.
24 PCIE_PTX_C_WLANRX_N2
24 PCIE_PTX_C_WLANRX_P2
D24 @
28
BT_PWR#
WLAN/ WiFi
BT_CTRL
2
G
Q36
BT@
38,41,48,50 SUSP#
S 2N7002_SOT23-3
CLK_WLAN#
CLK_WLAN
+3V_WLAN
38
38
1
1R16
R17
E51_TXD
E51_RXD
2
0_0402_5%
2
0_0402_5%
Debug card using
E51_RXD_R
53
GND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
54
2
@ PJ26 2
+3VS
1
1 JUMP_43X79
+3V_WLAN
Short PJ26 for WiFi(WLAN) module only.
PLT_RST#
WL_OFF# 38
PLT_RST# 13,27,34,38,39
+1.5VS
PM_SMBCLK 11,12,21,24
USB20_N13 27
USB20_P13 27
For SED
0.1U_0402_16V4Z
1
1
CM7
WiMax
CM8
2
0.01U_0402_25V7K
+3V_WLAN
For SED
0.1U_0402_16V4Z
1
1
@
C254
CM1
CM2
47P_0402_50V8J
2
2
4.7U_0805_10V4Z
0.01U_0402_25V7K
CM9
Disable
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
@
C253
47P_0402_50V8J
2
4.7U_0805_10V4Z
CM3
Enable
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
BT
on module
+3V_WLAN
2 A
JWLAN
WLAN&BT Combo module circuits

BT
on module
+1.5VS
1 A
@ FOX_AS0B226-S40N-7F
E51_RXD_R
2
R287
BT_CTRL
1
1K_0402_5%
Compal Secret Data
Issued Date
2010/09/05
Deciphered Date

2011/09/05
Title
Size
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
33
of
52
3/19 --> Change JLAN for don't support LAN LED fuction
--> Pin40, 37 change to NC Pin
UL1
24 PCIE_PRX_C_LANTX_P1
CL1
2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1
22
HSOP
24 PCIE_PRX_C_LANTX_N1
CL2
2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1
23
HSON
17
18
24 PCIE_PTX_C_LANRX_P1
24 PCIE_PTX_C_LANRX_N1
LED3/EEDO
LED1/EESK
LED0
31
37
40
EECS/SCL
EEDI/SDA
30
32
HSIP
HSIN
0715 --> LL1, CL13, CL9, LL3, CL28,

CL29 are unmount for RTL8105E-VC
RL19
0_0402_5% 16
1
RL3
2 PCH_WAKE#
100K_0402_5%
1
2
4
5
7
8
10
11
DVDD10
DVDD10
DVDD10
13
29
41
RL2
RL1
+LAN_REGOUT
1
2
2.2UH +-5% NLC252018T-2R2J-N
1 10K_0402_5%
1 10K_0402_5%
2
2
0.1U_0402_16V4Z
43
CKXTAL1
44
CKXTAL2
28
LANWAKEB
26
ISOLATEB
DVDD33
DVDD33
27
39
+3V_LAN
14
15
38
NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT
AVDD33
AVDD33
AVDD33
AVDD33
12
42
47
48
+3V_LAN
33
ENSWREG
EVDD10
21
+LAN_EVDD10
0.1U_0402_16V4Z
34
35
VDDREG
VDDREG
AVDD10
AVDD10
AVDD10
AVDD10
3
6
9
45
+LAN_VDD10
0.1U_0402_16V4Z
REGOUT
36
1 RL22
RL22 need always pull-high
for RTL8105E Efuse mode
2 1K_0402_5%
ENSWREG
+LAN_VDDREG
+3VS
1
RL5
2
2.49K_0402_1%
46
RSET
24
49
GND
PGND
+LAN_VDD10
2
CL4
2
CL5
2
CL6
2
CL7
+LAN_EVDD10
2
0_0603_5%
1
LL2
CL18
1U_0402_6.3V4Z
CL17
0.1U_0402_16V4Z
1
CL19,CL20,CL21,CL22 close to
Pin 3,13,29,45
+LAN_VDD10
0.1U_0402_16V4Z
Close to Pin 21
0.1U_0402_16V4Z
+3V_LAN
2
CL19
2
CL20
2
CL21
2
CL22
1
1
1
+LAN_VDDREG
2
0_0603_5%
+LAN_REGOUT
2
CL10
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+LAN_VDD10
LAN_X2
PCH_WAKE#
0.1U_0402_16V4Z
CL9 @
0.1U_0402_16V4Z
LAN_X1
ISOLATEB
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-
REFCLK_P
REFCLK_N
+3V_LAN
RL6
1K_0402_1%
0.1U_0402_16V4Z
1
Layout Note: LL1 must be

within 200mil to Pin36,
@CL13
@
CL13
CL13,CL9 must be within 4.7U_0603_6.3V6K
200mil to LL1
+LAN_REGOUT: Width =60mil
PERSTB
25 PCH_WAKE#
+3V_LAN
LL1 @
19
20
CLK_LAN
CLK_LAN#
+3V_LAN
MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3
+LAN_VDD10
25
13,27,33,38,39 PLT_RST#
24
24
CLKREQB
C10,CL4,CL5,CL6,CL7 close to
Pin 27,39,12,47,48
LL1,CL13 will be changed to

2.2uH&4.7uF after EVT test
24 CLKREQ_LAN#
1
LL3@
@CL28
@
CL28
4.7U_0603_6.3V6K
RTL8105E-GR QFN _6X6
CL29 @
0.1U_0402_16V4Z
1
ISOLATEB
0715 --> change P/N to SA00003PO20 (RTL8105E-VC )

RL7
15K_0402_5%
+3V_LAN
ISOLATEB
RL10
@ 0_0402_5%
LAN Conn.
WOL_EN# 38,41
4/2->remove RL8, RL9, CL11
@ RL4
0_0402_5%
RL11
0_0402_5%
WOL_EN
JLAN @
YL1
38
ENSWREG
LAN_X1
LAN_X2
PR4-
PR4+
PR2-
PR3-
PR3+
RJ45_MIDI1+
PR2+
RJ45_MIDI0-
PR1-
RJ45_MIDI0+
PR1+
25MHZ_20PF_7A25000012
RL23
0_0402_5%
Add RL10 for +3V_LAN power enable signal

Add RL11 for wake on LAN function enable signal
1
CL26
27P_0402_50V8J
2
1
CL27
27P_0402_50V8J
RJ45_MIDI1-
0715 --> RL4 is unmount,

RL23 mount for
RTL8105E-VC
3/29 --> swap Line and PHY signal
SHLD1
SHLD2
10
UL3
SANTA_130452-C
LAN_MDI0LAN_MDI0+
Place these components

colsed to LAN chip
TX+
TXCT
NC
NC
CT
RX+
RX-
16
15
14
13
12
11
10
9
RJ45_MIDI1RJ45_MIDI1+
CL42 1000P_0402_50V7K
2
1
CL41 1000P_0402_50V7K
2
1
RJ45_MIDI0RJ45_MIDI0+
1
RL15
2
75_0402_1%
1
RL13
2
75_0402_1%
8/16->Add CL39 for EMI request

Add D69 for ESD
RJ45_GND
RJ45_GND
LFE8456E-R
TD+
TDCT
NC
NC
CT
RD+
RD-
CL36 1
CL34
0.1U_0402_25V6
LANGND
1000P_1808_3KV7K
2
2
1
2
3
4
5
6
7
8
LAN_MDI1LAN_MDI1+
D69
1
CL39
120P_0402_50V8J
CL37 @
0.1U_0402_16V4Z
CL38 @
4.7U_0603_6.3V6K
PJDLC05_SOT23-3
4
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title

SCHEMATICS,MB A6847
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Date:
Rev
B
4019AP
Sheet
E
34
of
52
For EMI request

1
@ CC2
@ RC6
2
100P_0402_50V8J
CLK_48M_CR
10_0402_5%
2
@ CC10
1
10P_0402_50V8J
2
+3VS
27
27
+3VS_CR
RC3
0_0603_5%
UC1
12mil
USB20_N10
USB20_P10
USB20_N10
USB20_P10
+3VS_CR
+VCC_3IN1
+V1_8
1 CC3
0.1U_0402_16V4Z
1
CC7
1U_0402_6.3V4Z
4.7U_0805_10V4Z
2
2
SDWP_MSCLK
2
SD_DATA1
SD_DATA0
CC4
REFE
2
3
DM
DP
4
5
6
3V3_IN
CARD_3V3
V18
XD_CD#
8
9
10
11
12
25
CC3, CC4, CC5, CC6,

CC7, RC2, RC3, UC1
form CARD@ to mount
SP1
SP2
SP3
SP4
SP5
GPIO0
17
CLK_IN
24
XD_D7
23
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6
22
21
20
19
18
16
15
14
13
EPAD
RC2
6.19K_0402_1%
2
1
0620 --> remove CR_LED#

CLK_48M_CR
< 48MHz >
CLK_48M_CR 21
SD_DATA2_MS_DATA5
MS_DATA1_SD_DATA3
0620 --> remove CARD-RADER LED
SDCMD
MS_DATA2_SDCLK
SDCD#
RTS5137-GR_QFN24_4X4
0715 --> change P/N to RTS5137 (SA000043500)

C
< 2 in 1 Card Reader >

0624 --> change CARDREADER conn.
JREAD @
D3 1
CMD 2
VSS1 3
VDD 4
CLK 5
VSS2 6
D0
D1
D2
WP
CD
7
8
9
10
11
GND1
GND2
GND3
GND4
12
13
14
15
MS_DATA1_SD_DATA3
SDCMD
+VCC_3IN1
MS_DATA2_SDCLK
1
SD_DATA0
SD_DATA1
SD_DATA2_MS_DATA5
SDWP_MSCLK
SDCD#
CC6
0.1U_0402_16V4Z
CC5
1U_0402_6.3V4Z
TAITW_PSDAT3-09GLAS1N14N
For EMI request

@ RC4
MS_DATA2_SDCLK
10_0402_5%
2
@ CC8
10_0402_5%
2
@ CC9
@ RC5
SDWP_MSCLK
10P_0402_50V8J
2
10P_0402_50V8J
2
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
35
of
52
Pin36
Codec
+PVDD1
0.1U_0402_16V4Z
1
1
CA57
JA1 place on +5vs source side
35 mA
4.7U_0805_10V4Z
1 CA29
45
44
21
22
MIC1_L
MIC1_R
HP_OUT_L
HP_OUT_R
32
33
MIC2_L
MIC2_R
GPIO0/DMIC_DATA
GPIO1/DMIC_CLK
PD#
1
2
CA15
2.2U_0603_6.3V4Z
+MIC1_VREFO_L
CA47 1
2 0.1U_0603_50V7K
RA18 1
2 0.1U_0603_50V7K
12
SYNC
10
BCLK
SDATA_OUT
SDATA_IN
RESET#
EAPD
SENSE B
36
CBP
35
CBN
31
MIC1_VREFO_L
43
42
49
7
PVSS2
PVSS1
DVSS2
DVSS1
place close to chip
Pin1
37
37
SPKR+
SPKR-
37
37
RA5
75_0402_1%
DIGITAL
(Include Themal PAD)
HP_L
37
HP_R
37
Beep sound
AZ_SYNC_HD
EC Beep
23
38
AZ_SDOUT_HD 23
2
RA6
SPDIFO
48
20
MIC2_VREFO
29
1
33_0402_5%
@
2
1
R391 10_0402_5%
AZ_BITCLK_HD
2
@C24
@
C24
1
10P_0402_50V8J
@
2
1
R402 10_0402_5%
AZ_RST_HD#
VREF
27
AC_VREF
19
AC_JDREF2 RA9
CPVEE
34
1
CA14
AVSS1
AVSS2
26
37
CA17
CA16
10U_0805_10V4Z
2
2 @
0.1U_0402_16V4Z
Place close to chip

3
place close to chip
DGND
ALC259Q PN IS NOT READY
2
0_0603_5%
+MIC1_VREFO_R
AGND
Codec Signals
Function
39.2K
PORT-I (PIN 32, 33)
Headphone out
20K
PORT-B (PIN 21, 22)
Ext. MIC
10K
PORT-C (PIN 23, 24)
5.1K
+MIC1_VREFO_L
@
CA37
1U_0402_6.3V4Z
@
CA36
1U_0402_6.3V4Z
MIC_SENSE
2
RA10
1
20K_0402_1%
SENSE_A
For EMI
21 INT_MIC_CLK
37
NBA_PLUG
RA21
39.2K_0402_1%
0620 --> remove RA13 for SENSE_B
PORT-E (PIN 14, 15)
Issued Date
RA41
INT_MIC_CLK_R
FBMA-10-100505-301T
CAM@
1
CA30
27P_0402_50V8J
@
2
2010/09/05
Deciphered Date
2011/09/05
Title
Size
Date:
Compal Secret Data
0618 --> remove +MIC2_VREFO

for analog IntMIC
place close to chip

37
(PIN 48)
39.2K
100P_0402_50V8J
ALC259-GR_QFN48_7X7
2 0.1U_0603_50V7K
SENSE A
CA18
1 20K_0402_1%
2
2.2U_0603_6.3V4Z
2 0.1U_0603_50V7K
Impedance
+MIC1_VREFO_R CA28 10U_0805_10V4Z

1
2
JDREF
MONO_IN
0.1U_0402_16V4Z
RA12
4.7K_0402_5%
For EMI, place near codec

0618 --> remove +MIC2_VREFO for analoh IntMIC
30
28
CA13
1
2
RA8
1
2
47K_0402_5%
23,26 PCH_SPKR
1
10P_0402_50V8J
CA50 1
Sense Pin
RA7
1
2
47K_0402_5%
EC_BEEP#
PCI Beep
AZ_SDIN0_HD 23
2
@C23
@
C23
MIC1_VREFO_R
LDO_CAP
ANALOG
Pin12
Moat
SPKL+
SPKL-
75_0402_1%
AZ_SDIN0_HD_R
Pin13
CA6
RA4
CA49 1
1
CA48
CA5
AZ_BITCLK_HD 23
MONO_OUT
SENSE A
18
CA4
47
PCBEEP
13
0620 --> remove SENSE_B
SPK_OUT_R+
SPK_OUT_R-
SENSE_A
EC_MUTE#
1
RA45
LINE2_L
LINE2_R
MONO_IN
2
100P_0402_50V8J
25
14
15
INT_MIC_CLK_R
23 AZ_RST_HD#
2
4.7K_0402_5%
46
40
41
11
1
CA12
39
SPK_OUT_L+
SPK_OUT_L-
INT_MIC_DATA
CA3
2
2
2
2
10U_0805_10V4Z 0.1U_0402_16V4Z
LINE1_L
LINE1_R
Int. Mic
38 EC_MUTE#
UA1
23
24
16
17
21 INT_MIC_DATA
2
2
10U_0805_10V4Z
RA3
10U_0805_10V4Z 0.1U_0402_16V4Z 2
1
+5VS
0_0603_5%
MIC1_R_R
1 CA23
ALC259-GR
0.1U_0402_16V4Z
+5VS
1
1
CA62
@
@
CA58
Pin48
PVDD2
1
DVDD
37
RA11
2
1
0_0603_5%
@
CA63
2
10U_0805_10V4Z
68 mA
35mA for 3.3V level
4.7U_0805_10V4Z
MIC1_R_L
0.1U_0402_16V4Z
2
+AVDD
Ext. Mic
37
place close to chip
+PVDD2
1
CA61
CA7
10U_0805_10V4Z
2
2
place close to chip
2
10U_0805_10V4Z
1
CA8
0.1U_0402_16V4Z
2
1
0_0603_5%
Pin24
Pin38
CA43
2
10U_0805_10V4Z
+3VS_DVDD
10U_0805_10V4Z
2
2
RA1
+3VS
38
CA1
Pin37
+5VS
Pin39
2
AVDD2
CA2
Del RA20 with connect to +1.5VS
PVDD1
AVDD1
2
RA19 0_0603_5%
DVDD_IO
+3VS
JA1
JUMP_43X39
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
CA44
2
1
0_0603_5%
CA56
+DVDD_IO
Pin25
RA2
600 mA
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
D
Sheet
36
of
52
Speaker Connector
placement near Audio Codec
D
36
SPKL+
SPKL+
RA26
2
0_0603_5%
SPK_L1
2
RA27
36
SPKL-
SPKL-
1
2
0_0603_5%
@DA4
@
DA4
CA22 @
470P_0402_50V8J 2
1
CA24
1U_0402_6.3V4Z
2
@
1
CA21 @
470P_0402_50V8J
1
SPK_L2
3
JSPK @
SPK_L1
SPK_L2
SPK_R1
SPK_R2
1
2
3
4
@DA5
@
DA5
RA28
36
SPKR+
SPKR+
1
2
0_0603_5%
RA29
36
SPKR-
SPKR-
1
2
0_0603_5%
PJDLC05_SOT23-3
2
PJDLC05_SOT23-3
3
1
2
3
4
ACES_85204-0400N
SPK_R1
2
CA25 @
470P_0402_50V8J 2
1
CA27
1U_0402_6.3V4Z
2
@
1
CA26 @
470P_0402_50V8J
1
SPK_R2
place near JSPK conn.
Ex.MIC JACK
JEXMIC @
MIC1_L_L
1
CA9
100P_0402_50V8J
3
6
2
1
DA6 @
CA10
100P_0402_50V8J
1
2
6
3
MIC1_L
MIC1_L_R
LA6 1
2
KC FBM-L11-160808-121LMT 0603
LA8 1
2
KC FBM-L11-160808-121LMT 0603
MIC1_R
36 MIC_SENSE
7
8
GND
GND
5
AGND
10
9
8
7
Ext.MIC/LINE IN
36 MIC1_R_R
DA7 @
CA19
100P_0402_50V8J
1
2
6
3
CA11
100P_0402_50V8J
HP_L_R
1
HP_L
3
6
2
1
36
4
HP_R_R
LA9 1
2
KC FBM-L11-160808-121LMT 0603
LA101
2
KC FBM-L11-160808-121LMT 0603
MIC1_L
RA25 1
2
2.2K_0402_5%
+MIC1_VREFO_L
0618 --> remove Analog IntMIC, and change to DIGITAL MIC

7
8
GND
GND
HP_R
+MIC1_VREFO_R
MIC1_R
Int. Mic
JLINE @
5
AGND
NBA_PLUG
2
1
1K_0402_5%
RA24
36 MIC1_R_L
Head Phone JACK

36
RA22 1
2
2.2K_0402_5%
3
PJDLC05_SOT23-3
36
RA23
1K_0402_5%
2
1
FOX_JA63331-B39S4-7F
2
10
9
8
7
FOX_JA63331-B39S4-7F
2
1
3
PJDLC05_SOT23-3
2010/09/05
Issued Date
Compal Secret Data
2011/09/05
Deciphered Date
Title
Size
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
37
of
52
+3VL
+3VL
1
1
1000P_0402_50V7K
U19
for EMI request

28
GATEA20
28 KB_RST#
23,39 SERIRQ
23,39 LPC_FRAME#
23,39 LPC_AD3
23,39 LPC_AD2
23,39 LPC_AD1
23,39 LPC_AD0
CLK_PCI_EC
R377
@ 10_0402_5%
27 CLK_PCI_EC
13,27,33,34,39 PLT_RST#
C443
@ 22P_0402_50V8J
+3VL
28
R378
47K_0402_5%
2
1
2
C444
ECRST#
EC_SCI#
GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
1
2
3
4
5
7
8
10
CLK_PCI_EC
PLT_RST#
ECRST#
EC_SCI#
12
13
37
20
38
1
R380
1
R382
2
47K_0402_5%
2
47K_0402_5%
PLT_RST#
1 @
0.1U_0402_16V4Z
KB_RST#
1
0.1U_0402_16V4Z
2
C456
39
KSI[0..7]
39
KSO[0..17]
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
For ESD
63
64
65
66
75
76
BATT_TEMPA
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
68
70
71
72
VTTP_EN
EN_DFAN1
IREF
CHGVADJ
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
83
84
85
86
87
88
EC_MUTE#
USB_EN#
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
97
98
99
109
VGATE
WOL_EN#
PWRME_CTRL#
LID_SW#
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
119
120
126
128
EC_SI_SPI_SO
EC_SO_SPI_SI
SPI_CLK
SPI_CS#
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
73
74
89
90
91
92
93
95
121
127
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
100
101
102
103
104
105
106
107
108
DA Output
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
KSO[0..17]
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
PS2 Interface
+3VS
8
7
6
5
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
43
43
20,24
20,24
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
SPI Flash ROM
GPIO
SM Bus
2.2K_0804_8P4R_5%
CRY1
CRY2
R389
2CRY2
@ 10M_0402_5%
EC_CLK
2
0_0402_5%
R624
100K_0402_5%
@
C450
18P_0402_50V8J
OSC
OSC
NC
NC
Y4
1
1
18P_0402_50V8J
@
C449
25
1
R103
2 0_0402_5%
2 0_0402_5%
122
123
@
C480
ADP_I
ADP_V
VTTP_EN
42,44
1
R337
2
100K_0402_5%
BATT_TEMPA 43
ADP_I
ADP_V
44
44
+5VS
VTTP_EN 46
EN_DFAN1 6
IREF
44
CHGVADJ 44
TP_DATA
1
R379
1
R381
2
4.7K_0402_5%
2
4.7K_0402_5%
EC_MUTE# 36
USB_EN# 32
TP_CLK
TP_DATA
TP_CLK 40
TP_DATA 40
VGATE
25,49
WOL_EN# 34,41
PWRME_CTRL# 23
LID_SW# 39
+3VALW
@
R348 330K_0402_5%
1
2
+3VL
R345 330K_0402_5%
1
2
D23
OTP#
FSTCHG
BATT_FULL_LED#
CAPS_LED#
BATT_CHG_LOW_LED#
OTP#
EC_SI_SPI_SO 39
EC_SO_SPI_SI 39
SPI_CLK 39
SPI_CS# 39
FSTCHG 44
BATT_FULL_LED# 40
CAPS_LED# 39
BATT_CHG_LOW_LED# 40
SYSON
VR_ON
VS_ON
43,45
0621->remove PWR_ON_LED#
SYSON
VR_ON
ACIN_D
SYSON
1
R5
2
4.7K_0402_5%
VR_ON
1
R462
2
10K_0402_5%
47
49
For prevent leakage for CPU_CORE

EC_RSMRST#
EC_LID_OUT#
EC_ON
PM_PWROK
BKOFF#
WL_OFF#
EC_RSMRST# 25
EC_LID_OUT# 24
EC_ON
40,45
PM_PWROK 25
BKOFF# 21
WL_OFF# 33
R341 330K_0402_5%
1
2
+3VL
D21
EC_SEL
ACIN_D
ACIN
25,44
GPI
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
110
112
114
115
116
117
118
V18R
124
XCLK1
XCLK0
PM_SLP_S4#
PM_SLP_S4# 25
VGA_ENBKL 14
SUSP#
PBTN_OUT#
USB_OC#0
SUSP#
SUSP#
33,41,48,50
PBTN_OUT# 25
USB_OC#0 27,32
1
R423
2
10K_0402_5%
+EC_V18R
+3VALW
C448
4.7U_0805_10V4Z
KB926QFE0_LQFP128_14X14
R435
100K_0402_5%
@
EC_SEL
R436
100K_0402_5%
For EC Crystal cost down
EC SEL
EC Version
High
KB926D3
Low
KB926E0
@ R104 1
@R104
@R108
@
R108 1
CRY1
E51_TXD
E51_RXD
ON/OFFBTN#
PWR_LED#
NUM_LED#
ACOFF
33
33
40
40
39
GND
GND
GND
GND
GND
E51_TXD
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
11
24
35
94
113
100K_0402_5%
1
2
25 PCH_SUSPWRDN
21 INVT_PWM
6 FAN_SPEED1
R342
6
14
15
16
17
18
PCH_SUSPWRDN 19
25
FAN_SPEED1
28
29
E51_TXD
30
E51_RXD
31
ON/OFFBTN#
32
34
NUM_LED#
36
ACOFF
EC_BEEP# 36
18P_0402_50V8J
for Wake on
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
THM_ALT#
25 PM_SLP_S3#
25 PM_SLP_S5#
28
EC_SMI#
28
THM_ALT#
LAN 34
WOL_EN
remove SM_SENSE
SPI Device Interface
RP7
1
2
3
4
+3VL
EC_BEEP#
TP_CLK
77
78
79
80
KSI[0..7]
remove KB LED
AD Input
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
KSO2
21
23
26
27
MISC
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
KSO1
Remove CEC_INT# pull high
PWM Output
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
to avoid EC entry ENE test mode

2
C455
0.1U_0402_16V4Z
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
+3VL
1
0.1U_0402_16V4Z
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &
2
100P_0402_50V8J
2
100P_0402_50V8J
2
2
0.1U_0402_16V4Z
C441
1000P_0402_50V7K
67
C440
C439
VCC
VCC
VCC
VCC
VCC
VCC
0.1U_0402_16V4Z
C438
AVCC
C437
BATT_TEMPA
1
C445
ACIN_D
1
C446
C442
1
2
AGND
C436
69
0.1U_0402_16V4Z
1
2
9
22
33
96
111
125
0.1U_0402_16V4Z
1
1
32.768KHZ_12.5PF_Q13MC14610002
A
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size
Remove PM_SLP_S4#/S5# AND Gate
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
38
of
52
SPI Flash (256KB)
LPC Debug Port
Lid SW
Please place the PAD under DDR DIMM.

+3VS
+3VL
1
R401
+3VALW
SPI_CLK
SPI_CLK
38 EC_SO_SPI_SI
+3V_LID
U21
APX9132ATI-TRL_SOT23-3
EC_SI_SPI_SO 38
MX25L2005CMI-12G SOP 8P
1
SPI_CLK
1 R394 @2
10_0402_5%
SERIRQ
HOLD
23,38
2
0_0402_5%
1
C454
2
@ 10P_0402_50V8J
VDD
VOUT
C453
0.1U_0402_16V4Z
PLT_RST# 13,27,33,34,38
LPC_AD2 23,38
R383
47K_0402_5%
23,38
LPC_AD3
23,38
LPC_AD1
LPC_AD0 23,38
10
CLK_PCI_DDR
23,38 LPC_FRAME#
LID_SW#
DEBUG_PAD
38
1
C452
10P_0402_50V8J
27
38
1
R426
+3VL
R393
22_0402_5%
38 SPI_CS#
VSS
1
2
R392 0_0402_5%
VCC
GND
0.1U_0402_16V4Z
U22
2
0_0402_5%
C451
20mils
H7
2
2
1
reserve for EMI, close to U22
C457
22P_0402_50V8J
reserve for EMI
KEYBOARD CONN.
Noticed: KB Connector Pin Definition Reversed with KB Membrane Pin Definition
please close to JKB

KSI[0..7]
KSO[0..17]
KSI[0..7]
38
KSO16
KSO[0..17] 38
JKB @
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ACES_88170-3400
1
C401
1
C402
KSO2
1
C404
KSO1
1
C405
KSO0
1
C406
KSO4
1
C407
KSO3
1
C408
KSO5
1
C409
KSO14
1
C410
KSO6
1
C411
KSO7
1
C412
KSO13
1
C413
KSO8
1
C415
KSO9
1
C416
KSO10
1
C417
KSO11
1
C418
KSO12
1
C419
KSO15
1
C420
KSI7
1
C421
KSI2
1
C422
KSI3
1
C423
KSI4
1
C424
KSI0
1
C425
KSI5
1
C427
KSI6
1
C429
KSI1
1
C431
CAPS_LED#
1
C433
NUM_LED#
1
C435
KSO17
JKB34
KSO16
1
2
R372 300_0402_5%
+3VS
KSO17
KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
JKB4
2
1
CAPS_LED# R376 300_0402_5%
NUM_LED#
+3VS
CAPS_LED# 38
NUM_LED# 38
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
Issued Date
Compal Secret Data
2010/09/05
Deciphered Date
2011/09/05
Title
Size
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
39
of
52
Power Button
R396
10K_0402_5%
S 2N7002_SOT23-3
LEFT
SW_L
SW1
ON/OFFBTN#
TOP side
1
6
5
SMT1-05_4P
6
5
SW_R
PWR/B to MB Conn.
1
3
SMT1-05_4P
ON/OFFBTN#
6
5
JPOWER @
1 1
2 2
3 3
4 4
G1 5
G2 6
For EMI request
1
2
3
4
5
6
GND
GND
ACES_85201-06051
D19 @
AZ5125-02S.R7G_SOT23-3
SW_L
SW_R
SW4
2
3
TP_CLK
TP_DATA
SMT1-05_4P
0620->change JTOUCH connector

D20 @
AZ5125-02S.R7G_SOT23-3
D83 @
AZ5125-02S.R7G_SOT23-3
38
38
6
5
BTM side
RIGHT
C458
0.1U_0402_25V6
@
1
2
3
4
5
6
7
8
+5VS
SMT1-05_4P
38
SW3
ON/OFFBTN#
SW2
JTOUCH @
100K_0402_5%
D
TP Button/Conn.
42
R395
debug phase using
2
G
Q38
1
EC_ON
38,45
+3VL
51_ON#
ACES_85201-0405N
For EMI request

For ESD
Screw Hole
2
510_0402_5%
YG
H3
H4
H_2P9x3P9
@
H_2P9x3P9
@
H_2P9
@
H2
H_3P0
@
H13
H_3P0
@
H12
H_3P0
@
H11
H_3P0
@
PWR_LED# 38
H1
H26
H17
H14
H_2P7N
@
H_2P7x3P2N
@
HT-110UYG5_YELLOW GREEN
H10
H_3P0
@
CPU
H_1P0N
@
H9
H_3P0
@
1
R397
H8
H_3P0
@
D22
+5VALW
H6
H_3P0
@
Vf=1.9V~2.4V
If=5mA
H5
VGA
POWER/SUSPEND LED
H_3P0
@
SB
MINI CARD
BATT CHARGE/FULL LED

H19
H15
H_3P3
@
H16
H_5P0N
@
H_5P0N
@
H_3P3
@
H_4P2x4P7
@
H_4P2
@
H18
H21
H20
Vf=1.8V~2.0V
If=5mA(max)
H22
1
R403
YG
510_0402_5%
510_0402_5%
BATT_CHG_LOW_LED#
H23
H_4P2x4P7
@
38
H_4P7
@
BATT_FULL_LED# 38
HT-210UD5-UYG5_AMBER-YEL GRN
For Codec AGND
PCB Fedical Mark PAD
Dummy
3G
FD1
MDC
FD2
@
FD3
@
FD4
@
1
R399
D25
+5VALW
ISPD
ZZZ
PJP1
PCB
U11
DC-IN
PCB LA-6847P REV1
PCH
PJP1
UV1
UV1
UV1
GPU
PARKR3@
GPU
ROBSONR3@
GPU
ROBSONR1@
GPU
45@
PCH
HM55R3@
Issued Date
Compal Secret Data
2010/09/05
2011/09/05
Deciphered Date
Title
Size
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
40
of
52
+3VALW TO +3VS
+3VALW
+5VALW TO +5VS
+3VS
+1.5V to +1.5VS
+5VALW
Vgs=-0V,Id=9A,Rds=18.5mohm
+5VS
Combine with +1.5V_CPU
+1.5V
4.7U_0805_10V4Z
+1.5VS
4.7U_0805_10V4Z
C469
@
2
Q12A
@
SUSP 5
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
R414
820K_0402_5%
@
3 1
FDS6676AS
Q12B
@
R408
@
@
1 R411
2
+VSB
220K_0402_5%
470_0805_5%
Q11B
SUSP 5
2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
2
1U_0402_6.3V4Z
FDS6676AS_SO8
Q11A
C464
R413
200K_0402_5%
@
470_0805_5%
2
C468
C463
@
1
2
3
4
S
S
S
G
D
D
D
D
C467
@ Q31
8
7
6
5
0.1U_0402_25V6
+VSB
3 1
1U_0402_6.3V4Z
1 R410
2
47K_0402_5%
R407
C470
4.7U_0805_10V4Z
C315
SI4800BDY_SO8
C821
Vgs=10V,Id=14.5A,Rds=6mohm
SUSP
2
5
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
1
2
3
4
C462
Q10B
C292
S
S
S
G
Q10A
D
D
D
D
C461
0.01U_0402_25V7K
R412
330K_0402_5%
+VSB
8
7
6
5
4.7U_0805_10V4Z
C466
1 R409
2
47K_0402_5%
+5VS
+3VS
0.1U_0402_16V4Z
1U_0402_6.3V4Z
0.022U_0402_25V7K
4.7U_0805_10V4Z
C465
R406
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SI4800BDY_SO8
Q30
1
2
3
4
S
S
S
G
1
4.7U_0805_10V4Z
3 1
D
D
D
D
C460
8
7
6
5
C459
470_0805_5%
Q29
For EMI request

For EMI request
0715 --> Q31 change to SB548000310 the same as +5VS
+3VALW TO +3V_LAN
For S3 CPU Power Saving

+3VALW
+3VALW
2
1
+3V_LAN
1
R169
5,46 VTTPWROK
2
1
Q48A
2N7002DW-T/R7_SOT363-6
1
@ C479
1U_0402_6.3V4Z
0.75VR_EN
2
100K_0402_5%
SUSP
Q48A,B
R169, R425 form PS@ to mount
2
1
@ C476
4.7U_0805_10V4Z
0.75VR_EN# 48
Q48B
2N7002DW-T/R7_SOT363-6
PJ24
JUMP_43X79
@
@ C474
0.01U_0402_25V7K
2
47K_0402_5%
@ Q32
AO3413_SOT23
1
@ R420
WOL_EN#
R425
100K_0402_5%
34,38
Vgs=-4.5V,Id=3A,Rds<97mohm
@ 2
C471
0.1U_0402_16V7K
@
R419
100K_0402_5%
+3VALW
Reserve for EMI test
C473
0.1U_0402_16V7K
C478
0.1U_0402_16V7K
R422
100K_0402_5%
9,48
SUSP
SUSP
Q5A
2N7002DW-T/R7_SOT363-6
0715 --> change R412 from 470ohm to 47ohm
Q5B
2N7002DW-T/R7_SOT363-6
SUSP
2
1
33,38,48,50 SUSP#
R421 form PS@ to mount

R421
47_0805_5%
C475
0.1U_0402_16V7K
+0.75VS
+5VALW
+5VALW
+5VS
+3VS
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
E
41
of
52
VIN
PC6
100P_0402_50V8J
1
2
1
2
PC5
680P_0402_50V7K
PC4
1000P_0402_50V7K
@ SINGA_2DW-0005-B03
PC3
100P_0402_50V8J
DC_IN_S2
7A_24VDC_429007.WRML
PC2
680P_0402_50V7K
DC_IN_S1
PJP1
PC1
1000P_0402_50V7K
DC301001M80
+
PL1
SMB3025500YA_2P
1
2
PF1
VIN
PD2
RLS4148_LL34-2
2
PR15
22K_0402_1%
@PR4
@
PR4
100K_0402_5%
100K_0402_5%
@ PR6
1
2
1K_1206_5%
@ PR8
1
2
1K_1206_5%
1 2
@PR7
@
PR7
100K_0402_5%
1
51_ON#
B+
@PR3
@
PR3
@ PR5
1
2
1K_1206_5%
PC10
0.1U_0603_25V7K
1
PC9
0.22U_0603_25V7K
PR13
100K_0402_1%
40
VS
RLS4148_LL34-2
@ PR2
1
2
1K_1206_5%
@PQ2
@
PQ2
TP0610K-T1-E3_SOT23-3
PD1
N1
PD3
RLS4148_LL34-2
BATT+
VIN
@
2
1
2
0_1206_5%
PR10
68_1206_5%
2
PR9
68_1206_5%
2
PQ1
TP0610K-T1-E3_SOT23-3
PreCHG
PR1
@PD4
@
PD4
2
+5VALWP
1
45
RB715F_SOT323-3
3
@PQ30
@
PQ30
@PQ3
@
PQ3
DTC115EUA_SC70-3
ACOFF
38,44
DTC115EUA_SC70-3
PJ1
+3VALWP
PJ4
1
+3VALW
+1.5VP
@ JUMP_43X118
(5A,200mils ,Via NO.= 10)
+5VALW
PJ7
1
+1.8VS
@ JUMP_43X79
PJ9
1
+VGA_CORE
+3VLP
+3VL
1
@ PJ102
@ JUMP_43X118
+VSB
@ JUMP_43X39
(100mA,40mils ,Via NO.= 2)
PJ10
OCP(min)=7.9A
2
+1.8VSP
@ JUMP_43X118
+1.5V
PJ8
+VGA_COREP
@ JUMP_43X118
+VSBP
OCP(min)=16.57A
PJ5
2
PJ3
1
(14A,360mils ,Via NO.= 18)
OCP(min)=7.7A
+5VALWP
@ JUMP_43X118
+1.0VSP
@ JUMP_43X39
(20A,880mils ,Via NO.=44)
(120mA,40mils ,Via NO.= 1)
OCP(min)=24.49A
+1.0VS
JUMP_43X79
PJ17
PJ11
+0.75VSP
+0.75VS
@ JUMP_43X79
@ JUMP_43X118
(1.5A,60mils ,Via NO.= 4)
PJ13
+VTTP
+VTT
Issued Date
(20A,800mils ,Via NO.=40)
Compal Secret Data
@ JUMP_43X118
2010/09/05
Deciphered Date
2011/09/05
Title
Size
OCP(min)=22.9A
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
D
Sheet
42
of
52
VMB
PJP2
BATT_S1
1
2
3
4
5
6
7
8
9
PH1 under CPU botten side :

CPU thermal protection at 90degree C
Recovery at 56 degree C
BATT+
PR30
1K_0402_1%
PC16
1000P_0402_50V7K
@PC18
@
PC18
0.1U_0402_25V6K
BATT_P4
BATT_P5
EC_SMDA
EC_SMCA
10A_125V_451010MRL
PC17
0.01U_0402_25V7K
GND
GND
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
PL2
SMB3025500YA_2P
1
2
PF2
@ SUYIN_200045MR009G171ZR
VL
PD6
PD7
PJSOT24C_SOT23-3
1
2
1
PC19
0.1U_0402_16V4Z
PR31
23.2K_0402_1%
2
PR32
6.49K_0402_1%
2
1
+3VLP
2
PJSOT24C_SOT23-3
PR34
10.7K_0402_1%
PU4
VCC TMSNS1
GND RHYST1
OT1 TMSNS2
OT2 RHYST2
PR37
100_0402_1%
BATT_TEMPA 38
38,45
PR36
100_0402_1%
VS_ON
PH1
100K_0402_1%_NCP15WF104F03RC
2
PR35
1K_0402_1%
G718TM1U_SOT23-8
EC_SMB_DA1 38
EC_SMB_CK1 38
PQ4
TP0610K-T1-E3_SOT23-3
PR42
22K_0402_1%
1
2
1
2
1
2
PC20
0.22U_0603_25V7K
2
1
PR41
100K_0402_1%
VL
+VSBP
PC21
0.1U_0603_25V7K
B+
3
PR44
0_0402_5%
2
POK
PQ5
SSM3K7002FU_SC70-3
2
G
25,45
@ PC22
.1U_0402_16V7K
PR43
100K_0402_1%
Issued Date
Compal Secret Data
2010/09/05
Deciphered Date
2011/09/05
Title
Size
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
D
Sheet
43
of
52
CSIN
20
VCOMP
CSIP
19
ICM
PHASE
18
VREF
UGATE
17
4
4.7U_0805_25V6-K
PC26
4.7U_0805_25V6-K
2
1
PC25
4.7U_0805_25V6-K
2
1
VDDP
15
VADJ
LGATE
14
GND
PGND
13
ACLIM
PR70
20K_0402_1%
11
12
2
AO4466L_SO8
4
PD12
RB751V-40TE17_SOD323-2
6251VDDP
DL_CHG
26251VDD
16
PQ19
10
BOOT
1
2
2
1
PL3
10UH_MSCDRI-104A-100M-E_4.6A_20%
CHG
1
2
3
2
1
6251aclim
CHLIM
PC40
0.1U_0603_25V7K
BST_CHGA 2
1
PR69
120K_0402_1%
PR68
24K_0402_1%
6251VREF
1
2
DH_CHG
PR67
0_0603_5%
BST_CHG 1
PQ20
DTC115EUA_SC70-3
ACOFF
6251VREF
1
2
PC39
.1U_0402_16V7K
PR66
154K_0402_1%
2
1
PQ16
SSM3K7002FU_SC70-3
PR61
2.2_0603_1%
LX_CHG
2
G
AO4466L_SO8
5
6
7
8
ADP_I
1
ACOFF
6
PR62 47K_0402_1%
2
7
ACPRN
PQ17
PR71
4.7_0603_5%
PC45
4.7U_0805_6.3V6K
PR63
0.02_1206_1%
4
BATT+
PC107
10U_1206_25V6M
2
1
ICOMP
10K_0402_1%
2
CSOP
PC42
10U_1206_25V6M
2
1
21
CSOP
CELLS
BATT_ON
CSON
PC32
0.047U_0603_16V7K
1
2
PR58
20_0603_5%
2
1
PR59
20_0603_5%
PC37
0.1U_0603_25V7K
1
2
PC41
10U_1206_25V6M
2
1
45
PR57
20_0603_5%
1
2
2200P_0402_25V7K
PC33
CSON
EN
ACPRN
23
22
PC43
PR65
680P_0603_50V8J 4.7_1206_5%
ACSET ACPRN
38
38,42
6800P_0402_25V7K
2
0.01U_0402_25V7K
PC31
1
5
6
7
8
IREF
38
PR60
PC44
0.01U_0402_25V7K
2
1
3
4
PR64
47K_0402_5%
PACIN 1
2
PQ18B
DMN66D0LDW-7_SOT363-6
5
G
PC35
1
PC36
1
2
PR54
100K_0402_1%
24
PQ15
DTC115EUA_SC70-3
2
DCIN
ACSETIN
0.1U_0603_25V7K
PC24
2
1
VDD
VIN
PR52
10K_0402_1%
3
2
1
1
2
8
7
6
5
PR49
47K_0402_1%
1
2
PR51
14.3K_0402_1%
PU5
PR55
150K_0402_1%
PQ18A
PR47
191K_0402_1%
2
G
FSTCHG
38
PR50
10_1206_5%
2
PQ13
DTC115EUA_SC70-3
PR56
100K_0402_1%
PR53
10K_0402_1%
2
1
6251VDD
PreCHG
PC77
1000P_0402_25V8J
2
1
PD8
PR46
200K_0402_1%
CSIP
ACSETIN
BATT_ON
PC75
10U_1206_25V6M
2
1
CSIN
VIN
1
2
3
CHG_B+
PL19
1.2UH_1231AS-H-1R2N=P3_2.9A_30%
1
2
0.1U_0402_25V6K
2
1
RB751V-40_SOD323-2
PC29
2.2U_0603_6.3V6K
2
PR48
200K_0402_1%
PC28
5600P_0402_25V7K
1
2
1
1
PQ10
DTA144EUA_SC70-3
PC27
0.1U_0603_25V7K
0.02_1206_1%
8
7
6
5
PQ6
AO4435_SO8
PC23
1
2
3
B+
PR45
P3
B+
1
2
3
8
7
6
5
VIN
PQ8
AO4409L_SO8
P2
PQ7
AO4435_SO8
PC74
10U_1206_25V6M
2
1
PC73
10U_1206_25V6M
2
1
G5209S31U_SSOP24
PR72
15.4K_0402_1%
1
2
1
38 CHGVADJ
PR73
31.6K_0402_1%
VIN
CP mode
Iada=0~3.42A(65W)
CP= 92%*Iada; CP=3.147A
Vaclim=1.08V(65W)
PR68=75k
@PR74
309K_0402_1%
6251VDD
@ PR75
10K_0402_1%
1
2
ADP_V 38
2
@
2
G
@ PC46
.1U_0402_16V7K
ACPRN
100K_0402_1%
Vin Detector
@PR89
@
PR89
@ PR76
47K_0402_1%
PACIN
PR249
14.3K_0402_1%
PQ214
DTC115EUA_SC70-3
3.2935V
25,38
1.882V
4.35V
ACIN
High 18.089V
Low 17.44V
4.2V
PR250
10K_0402_1%
2
EN0
VCHLIM need over 95mV
45
0V
PC30
.1U_0402_16V7K
4V
PR252
47K_0402_1%
IREF=0.254V~3.048V
CHGVADJ
Vcell
PQ11
SSM3K7002FU_SC70-3
IREF=1.016*Icharge
PR251
10K_0402_1%
1
2
CHGVADJ=(Vcell-4)/0.10627
CC=0.25A~3A
PR45=0.02
Issued Date
Compal Secret Data
2010/09/05
Deciphered Date
2011/09/05
Title
Size
Date:
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
D
Sheet
44
of
52
PC47
1U_0603_10V6K
2VREF_51125
ENTRIP1
LG_5V
VCLK
5
6
7
8
PQ24
AO4712L_SO8
4
1
3
2
1
Ipeak=5A
Imax=3.5A
F=245kHZ
Total capacitor
330u
ESR=15m ohm
PQ31
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Size
DTC115EUA_SC70-3
Date:
2
1
PC59
0.1U_0603_25V7K
2VREF_51125
PC58
4.7U_0805_10V6K
1
2
PR88
100K_0402_5%
1
2
PC57
1U_0402_6.3V6K
B++
+5VALWP
PC54
330U_6.3V_M
19
DRVL1
PL5
4.7UH_SIL1045R-4R7PF_6.3A_30%
1
2
18
VIN
VREG5
17
16
LX_5V
PR86
4.7_1206_5%
VFB1
VREF
VFB2
TONSEL
6
13
20
2
G
EC_ON
21
LL1
PQ27
DTC115EUA_SC70-3
38,40
DRVH1
PC52
PR84
.1U_0402_16V7K
BST_5V 1
2BST_5V1
1
2
0_0603_5%
UG_5V
PC60
2.2U_0603_10V6K
PR105
200K_0402_1%
25,43
VL
ACPRN
44
POK
PR91
100K_0402_1%
44
DRVL2
PQ25B
5
G
1
2
12
PR90
100K_0402_1%
2
1
PR92
42.2K_0402_1%
LG_3V
PQ9
SSM3K7002FU_SC70-3
VS_ON
LL2
ENTRIP2
38,43
11
PR87
499K_0402_1%
1
2
B+
22
DRVH2
GND
VL
VBST2 TPS51125ARGER_QFN24_4X4
VBST1
EN0
ENTRIP1
23
LX_3V
AO4712L_SO8
PQ25A
PGOOD
SKIPSEL
8
7
6
5
PC51
.1U_0402_16V7K
24
VREG3
PR83
2 BST_3V 9
2.2_0603_1%
UG_3V 10
VO1
PC56
680P_0603_50V8J
AO4466L_SO8
3
2
1
VO2
PQ22
1
2
3
PR85
4.7_1206_5%
2
1
2 BST_3V11
PQ23
PC55
680P_0603_50V8J
2
1
PC53
330U_6.3V_M
+3VALWP
PR82
150K_0402_1%
2
5
6
7
8
EN0
1
2
3
1
PL4
4.7UH_SIL1045R-4R7PF_6.3A_30%
1
2
P PAD
15
25
ENTRIP2
PU6
VS
PR81
150K_0402_1%
1
2
B++
PC49
10U_1206_25V6M
PR80
19.1K_0402_1%
1
2
14
PQ21
AO4466L_SO8
Ipeak=5A
Imax=3.5A
F=305kHZ
Total capacitor
330u
ESR=15m ohm
PR79
20K_0402_1%
1
2
PC50
4.7U_0805_10V6K
8
7
6
5
1
2
PC48
10U_1206_25V6M
1
2
PC61
10U_1206_25V6M
PR78
30K_0402_1%
1
2
ENTRIP1
+3VLP
1
PC121
2200P_0402_50V7K
2
1
1
2
PC64
0.1U_0402_25V6
PC65
0.1U_0402_25V6
B+
PR77
13K_0402_1%
1
2
ENTRIP2
B++
PL20
HCB4532KF-800T90_1812
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
1
45
of
52
VTTPWROK
VTTPWROK_CPU
2
4
PC806
4.7U_0805_10V6K
9
DL_1.05VS_VCCP
G5603RU1U_TQFN14_3P5X3P5
PR812
2.43K_0402_1%
2
1
PR808
4.02K_0402_1%
1
2
PR811
3.4K_0402_1%
1
2
1
2
PC63
10U_1206_25V6M
1
2
PC62
10U_1206_25V6M
PC122
2200P_0402_50V7K
2
1
PC802
4.7U_0805_25V6-K
2
1
PC801
4.7U_0805_25V6-K
2
1
PC803
4.7U_0805_25V6-K
2
1
PR806
0_0402_5%
DL
8.06K_0402_1%
PR804
4.7_1206_5%
10
+5VALW
+VTTP
VDD
BST
TP
14
15
1
7
5,41
ILIM
LX_1.05VS_VCCP
PR805
1
2
PC809
4.7U_0603_6.3V6K
VFB=0.75V
PGOOD
12
11
PC808
680P_0603_50V7K
LX
FB
DH_1.05VS_VCCP
B+
PL802
1.0UH_PCMC104T-1R0MN_20A_20%
1
2
PQ802
TPCA8036-H_SOP-ADV8-5
VCC
13
PC805
0.1U_0603_25V7K
BST_1.05VS_VCCP1
1
2
3
2
1
OUT
PR803
2.2_0603_1%
BST_1.05VS_VCCP
1
2
DH
PGND
EN_SKIP
TON
PR807
100_0603_1%
1
2
AGND
+5VALW
PU800
@ PC804
.1U_0402_16V7K
3
2
1
PR802
0_0402_5%
1
2
VTTP_EN
38
PR801
255K_0402_1%
1
2
PL801
HCB2012KF-121T50_0805
1
2
1.05VS_51117_B+
PQ801
PC807
390U_2.5V_M
+5VS
PR814
4.53K_0402_1%
PR809
10_0402_5%
2
1
VTT_SENSE
PR810
10K_0402_1%
PR813
10_0402_5%
2
1
VSS_SENSE_VTT
PJ20
+VTTP
+1.05VS
@ JUMP_43X79
(7.0A,280mils ,Via NO.=14)
Compal Secret Data
Issued Date
2010/09/05
Deciphered Date
2011/09/05
Title
Size
Date:

SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
D
Sheet
46
of
52
PL21
HCB2012KF-121T50_0805
DL_1.5V
PGOOD
4
1
PGND
G5603RU1U_TQFN14_3P5X3P5
DL
PC98
4.7U_0805_10V6K
10U_1206_25VAK
PC124
2
1
1
+
PC95
330U_6.3V_M
PR130
4.7_1206_5%
PR132
8.06K_0402_1%
+5VALW
+1.5VP
10
VDD
BST
ILIM
FB
15
TP
VCC
LX_1.5V
12
11
AGND
PC96
4.7U_0603_6.3V6K
DH_1.5V
13
LX
PL10
1.0UH_PCMC104T-1R0MN_20A_20%
1
2
PC97
680P_0603_50V8J
OUT
DH
PC94
0.1U_0603_25V7K
1
2
PQ35
3
2
1
TON
EN_SKIP
2
PR131
100_0603_1%
1
2
+5VALW
PU10
2BST_1.5V1
PR129
2.2_0603_1%
3
2
1
BST_1.5V 1
@PC93
@
PC93
.1U_0402_16V7K
B+
14
SYSON
PR128
0_0402_5%
1
2
38
PR127
255K_0402_1%
1
2
PQ34
PC123
2200P_0402_50V7K
2
PC92
4.7U_0805_25V6-K
PC91
4.7U_0805_25V6-K
2
1
1.5V_B+
Ipeak=14A
Imax=9.8A
F=313kHZ
Total capacitor
1110u
ESR=5m ohm
C
PR134
10K_0402_1%
2
1
PR133
10K_0402_1%
1
2
Compal Secret Data
Issued Date
2010/09/05
Deciphered Date
2011/09/05
Title

SCHEMATICS,MB A6847
Custom
Date:
Rev
B
4019AP
Sheet
1
47
of
52
+1.5V
PJ23
@ JUMP_43X79
1
VCNTL
GND
NC
VREF
NC
VOUT
NC
TP
+5VALW
1
2
PC99
1U_0603_10V6K
+0.75VSP
PC102
0.1U_0402_10V7K
1K_0402_1%
1K_0402_1%
1
PR135
2
1
PR138
VIN
APL5336KAI-TRL SOP 8P
@ PC101
.1U_0402_16V7K
2
G
1
41 0.75VR_EN#
PR137
0_0402_5%
1
2
PQ36
SSM3K7002FU_SC70-3
9,41 SUSP
@ PR136
0_0402_5%
1
2
4.7U_0805_6.3V6K
PC100
PU11
PC103
10U_0805_6.3V6M
1
2
PC182
PD5
RB715F_SOT323-3
4.7U_0805_25V6-K
PC181
1U_0603_10V6K
1
2
PJ181
@ JUMP_43X39
+5VALW
+3VALW
3
1
PU180
FB
+1.8VSP
2
1
GND
APL5930KAI-TRG_SO8
PC187
0.1U_0402_10V7K
PR182
3K_0402_1%
3
4
EN
POK
VOUT
VOUT
PR184
2.4K_0402_1%
PC184
22U_0805_6.3V6M
8
7
PC183
0.01U_0402_25V7K
VCNTL
VIN
VIN
PR181
22K_0402_1%
1
2
PR185
2.4K_0402_1%
SUSP#
33,38,41,50
6
5
9
Compal Secret Data
Issued Date
2010/09/05
Deciphered Date
2011/09/05
Title
Size
Date:

SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
D
Sheet
48
of
52
CPU_VID3
CPU_VID4
1@ PR151 1K_0402_1%
CPU_VID4
CPU_VID5
1 PR154 1K_0402_1%
CPU_VID5
1 @ PR155 1K_0402_1%
CPU_VID6
1@ PR157 1K_0402_1%
CPU_VID6
H_DPRSLPVR 2
1 PR160 1K_0402_1%
H_DPRSLPVR 2
1 @ PR161 1K_0402_1%
H_PSI#
PR152 1K_0402_1%
PR158 1K_0402_1%
PQ37
BOOT2_2
PC117
0.22U_0603_25V7K
1
2
PL12
0.36UH_FDU1040J-H-R36M=P3_33A_20%
UGATE2
1
1
3
2
1
PR174
1.91K_0402_1%
1
2
PR177
0_0402_5%
1
PR179
1
8
H_PSI#
PR180
1
2
147K_0402_1%
0_0402_5%
2
40
39
38
37
36
35
34
33
32
31
2
PR195
1
2 1
PC143
0.22U_0603_25V7K
1
2
Layout Note:
Place near Phase1 Choke
PC142
4.7U_0805_25V6-K
2
1
PC140
4.7U_0805_25V6-K
2010/09/05
Issued Date
VSUM+
V2N
B
ISEN1
Deciphered Date
Title
Date:

2011/09/05
Size
C
6
VSUM-
Compal Secret Data
PR213
1_0402_5%
@ PR216
0_0402_5%
1
+CPU_CORE
V1N
1
PR212
10K_0402_5%
PR211
3.65K_0805_1%
2
1
1
2
3
2
1
PR210
4.7_1206_5%
LGATE1
5
PH4
10K_0402_1%_ERTJ0EG103FA
PC139
470P_0603_50V8J
2
1
0.36UH_FDU1040J-H-R36M=P3_33A_20%
PHASE1
VSUM-
@ PR220
100_0402_1%
PL14
PQ44
PC150
680P_0603_50V8J
1
@ PC186
1200P_0402_50V7K
PR214
1.2K_0402_1%
PR207
2.2_0603_1%
1
2 BOOT1_1
PR208
2.61K_0402_1%
2
1
PC145
0.22U_0603_10V7K
2
1
PR215
11K_0402_1%
2
1
PQ43
UGATE1
PC151
.1U_0402_16V7K
2
1
@ PR219 10_0402_5%
1
2
VSSSENSE
@ PC147
0.01U_0402_25V7K
PC149
330P_0402_50V7K
0_0402_5%
2
PC148
1000P_0402_50V7K
PR217
1
PC146
330P_0402_50V7K
VSUM2
0_0402_5%
@ PR206
82.5_0402_1%
1
PR209
PR204
8.87K_0402_1%
+CPU_B+
VSUM+
PC134
0.22U_0603_25V7K
1
2
0_0402_5%
Arrandale -- 2 phase 1H1L
1_0402_5%
2
+5VALW
0_0402_5%
2
IMVP_IMON
3
2
1
PR201
PC135
0.22U_0603_25V7K
0_0402_5%
2
+CPU_B+
PC144
0.047U_0402_16V7K
2
1
PR203
PC133
1U_0603_10V6K
2
1
0_0402_5%
1
2
@ PR205 10_0402_5%
VSSSENSE
ISEN2
0_0402_5%
2
BOOT1
ISEN1
PR186
1
PR198
1
1
ISEN2
Layout Note:
PH3 place near
Phase1 L-MOS
PC128
1U_0603_10V6K
2
1
PC130
2
PC138 0.22U_0402_6.3V6K
PR199
412K_0402_1%
VCCSENSE
VSUM-
+CPU_CORE
V1N
VSUM+
AGND
PC137 0.22U_0402_6.3V6K
2
1
PR171
1_0402_5%
@ PR175
0_0402_5%
1
PR183
0_0402_5%
30
29
28
27
26
25
24
23
22
21
PR202
41
BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1
11
12
13
14
15
16
17
18
19
20
PR194
562_0402_1%
2
1
PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2
PR196
2.43K_0402_1%
1
2
2
PC131
10P_0402_50V8J
PC132
150P_0402_50V8J
390P_0402_50V7K
PC126
22P_0402_50V8J
1
2
3
4
5
6
7
8
9
10
PR188
8.06K_0402_1%
1
2
PC127
1000P_0402_50V7K
2
1
PR189
249K_0402_1%
1
2
+CPU_CORE
V2N
+5VALW
PC119
1U_0603_10V6K
1
2
CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
PU13
ISL62883CHRZ-T_QFN40_5X5~D
ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1
2
1
PR170
3.65K_0805_1%
2
1
LGATE2
PR169
4.7_1206_5%
CLK_ENABLE#
PR172
1.91K_0402_1%
1
PC118
680P_0603_50V8J
PQ38
PHASE2
@ PR178 1K_0402_1%
1
2
+VTT
+3VS
B+
PR166
2.2_0603_1%
1
2
BOOT2
1
21 CLK_ENABLE#
VGATE
PR163 1K_0402_1%
PR168 0_0402_5%
8 H_DPRSLPVR
25,38
VR_ON
+VTT
PR167 0_0402_5%
38
PR149 1K_0402_1%
@ PC115
0.1U_0603_25V7K
2
1
1@ PR148 1K_0402_1%
PC185
68U_25V_M_R0.36
PC111
68U_25V_M_R0.36
CPU_VID3
PL11
HCB4532KF-800T90_1812
1
2
PC114
68U_25V_M_R0.36
1 @ PR147 1K_0402_1%
1 @ PR145 1K_0402_1%
CPU_VID2
PC113
4.7U_0805_25V6-K
2
1
CPU_VID1
1 PR146 1K_0402_1%
PR173
10K_0402_5%
CPU_VID6
1 PR144 1K_0402_1%
PC141
4.7U_0805_25V6-K
2
1
CPU_VID5
CPU_VID2
+CPU_B+
CPU_VID1
CPU_VID4
1 @ PR143 1K_0402_1%
CPU_VID3
CPU_VID2
CPU_VID0
PC116
4.7U_0805_25V6-K
1 PR142 1K_0402_1%
PC120
4.7U_0805_25V6-K
CPU_VID1
PC110
2200P_0402_50V7K
2
1
CPU_VID0
CPU_VID0
PC112
470P_0603_50V8J
2
1
3
2
1
SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
49
1
of
52
PL601
HCB4532KF-800T90_1812
Ipeak =13A
Imax = 9.1A
F = 231K
@ PC125
4.7U_0805_25V6-K
2
1
PQ601
Total capacitor 1170uF

ESR = 3.33mohm
EN
SW
LX_VCORE
VFB
V5IN
RF
DRVL
1
2
0_0603_5%
+5VALW
DL_VCORE
PL602
11
+VGA_COREP
0.56UH_ETQP4LR56WFC_21A_20%
1
2
PR626
PC628
2.2U_0603_6.3V6K
3
2
1
TPS51218DSCR_SON10_3X3
PR623
470K_0402_1%
0.1U_0603_25V7K
PR606
4.7_1206_5%
PC606
1
+
PC602
390U_2.5V_M
DH_VCORE
PR630
DRVH
TRIP
PC605
1
2
PR605
1
2
2.2_0603_1%
1 2
BST_VCORE
10
PQ602
VBST
TP
0_0402_5%
2
@ PC624
.1U_0402_16V7K
33,38,41,48 SUSP#
PGOOD
PR622
3
2
1
PU600
PR621
54.9K_0603_1%
1
2
0_0402_5%
10U_1206_25VAK
PC622
2
1
@
10U_1206_25VAK
PC621
2
1
B+_core
2
10U_1206_25VAK
PC620
2
1
B+
680P_0603_50V7K
PR631
+VGA_CORE
1
1
1
14
VGA_PWRSEL0
VGA_PWRSEL1
PC634
.1U_0402_16V7K
2
G
PC635
.1U_0402_16V7K
14
@PC632
@PC632
1000P_0402_50V7K
PR637
5.1K_0402_1%
2
2
G
SSM3K7002FU_SC70-3
PQ606
1
1
PR635
5.1K_0402_1%
1
2
SSM3K7002FU_SC70-3
PQ605
1
2
@ PC633
1000P_0402_50V7K
PR636
10.7K_0402_1%
PR632
4.22K_0402_1%
1
2
PR634
7.15K_0402_1%
10_0402_1%
PR633
6.98K_0402_1%
B
Rtrip = 27K, OCP = 24.49A
1
2
2
1
PR102
7.32K_0402_1%
PC190
0.1U_0402_10V7K
0.9
0.9
FB
EN
POK
PC192
22U_0805_6.3V6M
33,38,41,48 SUSP#
8
7
PR103
2K_0402_1%
1
2
+1.0VSP
PR101
1.82K_0402_1%
0.95
3
4
VOUT
VOUT
PC191
0.01U_0402_25V7K
APL5930KAI-TRG_SO8
VCNTL
VIN
VIN
PU100
GND
6
5
9
1.12
@ PJ101
JUMP_43X79
Park XT
PC189
4.7U_0805_6.3V6K
SEL1 SEL0 Robson LP
VFB(0.6)=Vout*Rbottom/(Rtop+Rbottom)
+5VALW
+1.5V
Rrf = 470K, FSW = 290KHz
PC188
1U_0603_6.3V6M
Compal Secret Data
Issued Date
2010/09/05
Deciphered Date
2011/09/05
Title

SCHEMATICS,MB A6847
Custom
Date:
Rev
B
PWWAA LA-6847P M/B
Sheet
1
50
of
52
NO DATE
PAGE
MODIFICATION LIST
PURPOSE
-------------------------------------------------------------------------------------------------------------------------------2010/10/14
42
Remove PR2,PR3,PR4,PR5,PR6,PR7,PR8,PD1,PD4,PQ2,PQ3,PQ30
Change PR1 to 0_1206_5%
Remove Pre charge
2010/10/14
44
Change PQ8 to AO4409L,remove PR89,PC30,PQ11
Remove Pre charge
Change PR68 to 24K ohm,add PC107
Circuit modify
2010/10/14
45
Change PU6 to TPS51125A
2010/10/14
46
2010/10/14
48
Change PQ802 to TPCA8036

Change PU11 to APL5336,PR181 to 15K ohm, add PC187(0.22U)
2010/10/14
50
Change PR621 to 54.9k ohm,Delete PR104,PC622
45
48
50
Add PC64(0.1U_0402_25V)
Circuit modify
Circuit modify
Circuit modify
Circuit modify
Add PR606,PC606
2010/10/21
2010/10/21
2010/10/21
EMI request
Change PR181 to 22k ohm,PC187 to 0.1UF,add PD5
HW request
Change PR605 to 2.2 ohm,PR635,PR637 to 5.1Kohm,PR103 to 2Kohm
HW request
Add PC190
Compal Secret Data
Issued Date
2010/09/05
Deciphered Date
2011/09/05
Title
Size
Date:

SCHEMATICS,MB A6847
Document Number
Rev
B
4019AP
Sheet
51
of
52
PIR (Product Improve Record)

PWWAA LA-6847P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 1.0
NO DATE
PAGE
MODIFICATION LIST
PURPOSE
-------------------------------------------------------------------------------------------------------------------------------------------------------D
Compal Secret Data
2010/09/05
Issued Date
Deciphered Date
2011/09/05
Title
Custom
SCHEMATICS,MB A6847
Rev
B
4019AP
Date:
Sheet
1
52
of
52

Compal La-6847p Pwwaa r10

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A

LA-6847P REV 1.0 Schematic

Compal Electronics, Inc.

Compal Secret Data

Model Name : PWWAA

PCIE-Express 16X 2.5GHz

Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2

1.5V DDRIII 800/1066 MT/s

USB port 0,1

Intel Ibex Peak

DC/DC Interface CKT.

Power Circuit DC/DC

Compal Electronics, Inc.

Compal Secret Data

DESIGN CURRENT 0.1A

Ipeak=5A, Imax=3.5A, Iocp min=7.7

DESIGN CURRENT 1.5A

DESIGN CURRENT 15A

Ipeak=18A, Imax=12.6A, Iocp min=19.8

DESIGN CURRENT 18A

Ipeak=7A, Imax=4.9A, Iocp min=7.7

Ipeak=15A, Imax=10.5A, Iocp min=16.5

DESIGN CURRENT 15A

Compal Electronics, Inc.

Compal Secret Data

BTO Option Table

MINI PCI-E SLOT

Camera & Mic

Camera & Mic

S5 S4/AC & Battery

PCH SM Bus Address

SLP_S3# SLP_S4# SLP_S5#

Compal Electronics, Inc.

Compal Secret Data

Tuesday, December 28, 2010

Power has removed VR_TT#

DDR3 Compensation Signals

JTAG & BPM

Unused by Clarksfield rPGA989

R28 unmount for NPS@

For S3 CPU Power Saving

place near JCPU

0715 --> change BOM structure to mount

Compal Electronics, Inc.

Compal Secret Data

Tuesday, December 28, 2010

FAN Control Circuit

PCI EXPRESS -- GRAPHICS

Compal Electronics, Inc.

Compal Secret Data

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY - B

Compal Electronics, Inc.

Compal Secret Data

(Place these capacitors under CPU socket Edge, top layer)

(Place these capacitors between inductor and socket on Bottom)

(Place these capacitors under CPU socket, top layer)

Power team request for F-Din

(Place these capacitors on CPU cavity, Bottom Layer)