Digital Signal Processors

Hardware and software systems are growing everyday in scale and functionality. This increase in complexity increases the number of subtle errors. Moreover, some of these errors may cause catastrophic loss of money, time, or even in many cases human life. A major goal of ...

In this paper, a simple adaptive speed control for induction motor is described and implemented using dedicated Digital Signal Processor (DSP). The controller structure design is based on voltage/frequency (V/Hz) control scheme that transforms the three phase motor speed into voltage and generating input of sine wave of PWM. Using these voltage components, the AC induction motor can be handled in the similar way with that of DC motor. Hence, the motor control system consists of voltage control loop and PWM control loop. To realize the speed controller, the speed reference is calculated as the output of speed sensor. From the experimental results it is shown that the overall induction motor speed control system gives good transient and the steady state responses tracks the motion profile given to the system.

SPEAKeasy is a successful implementation of a software-defined radio (SDR) for military applications. It permits general-purpose digital hardware to communicate over a wide range of frequencies, modulation techniques, data encoding methods, cryptographic types, and other communication parameters.

Digital audio processing plays an important role in many applications where the audio requires specific formats for reproduction, transmission or storage.
The fundamental function of the Mini Stereo Digital Audio Processor (MSDAP) is to implement a finite impulse response (FIR) digital filter.

Signal & Image Processing : An International Journal is an Open Access peer-reviewed journal intended for researchers from academia and industry, who are active in the multidisciplinary field of signal & image processing. The scope of the journal covers all theoretical and practical aspects of the Digital Signal Processing & Image processing, from basic research to development of application.

Authors are solicited to contribute to the journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the areas of Signal & Image processing.

Improving the conversion efficiency of solar panels has become a challenging area of study for researchers. Solar trackers are an alternative to reach this goal, as has been shown in many cases, by tracking the position of the sun changes, the productivity of the panel increases. This paper presents a new design of a dual-axis solar tracker system based on a real-time measurement of solar radiation in order to improve the conversion efficiency. As a first design stage, the dynamic models for solar radiation, solar panel and electromechanic system, were obtained using Matlab-Simulink. Then a control unit for capturing the signals from radiation sensors and an inertial measurement unit, was implemented in a High-Performance 16-Bit Digital Signal Controller DSPIC33FJ202MC. The acquired data are compared with a mathematical algorithm to calculate sun's position and set the control action to orient the panel. An embedded system with real-time sampling was developed. It does not rely on external databases and takes into account the relative position between the radiation sensor and solar panel to improve the efficiency of the system. Results show an increase of 9.87% in the energy obtained with the solar tracker compared to a static solar panel oriented optimally. The tests were performed using two solar 200W panels operating simultaneously under the same climatic conditions.

This paper presents a predictive current control method and its application to a voltage source inverter. The method uses a discrete-time model of the system to predict the future value of the load current for all possible voltage vectors generated by the inverter. The voltage vector which minimizes a quality function is selected. The quality function used in this work evaluates the current error at the next sampling time. The performance of the proposed predictive control method is compared with hysteresis and pulsewidth modulation control. The results show that the predictive method controls very effectively the load current and performs very well compared with the classical solutions.

Workloads drive architecture design and will change in the next two decades. For high-performance, general-purpose processors, there is a consensus that multimedia will continue to grow in importance. The authors predict these processors will incorporate more media processing capabilities, eventually bringing about the demise of specialized media processors, except perhaps, in embedded applications. These enhanced general-purpose processor capabilities will arise from multimedia applications that require real-time response, continuous-media data types and significant fine-grained data parallelism

—This paper deals with a video content classification based on spatial and temporal information. The main goal of the paper is to find out whether the non-expert test subjects are able to correctly recognize the spatial and temporal information and how precise is the corresponding parameterization of video content based on these two attributes. Moreover, how well do the objective values provided by the tool deployed in this experiment correlate with the subjective ones. The subjective measurement has shown that the non-expert test subjects are able to correctly recognize the spatial and temporal information only for the extreme scenes in terms of the spatial and temporal information but have experienced some problems when it comes to a more granular classification. When it comes to the objective assessment, the SI and TI values provided by the tool used in this experiment correlate quite well with the subjective data obtained from the basic test for the spatial information.

In this paper, we discuss how asynchronous design techniques can be used in the implementation of continuous-time signal processors. Such processors are presented by signals developed by continuous-time analog-to-digital converters which involve no sampling, and thus do not exhibit aliasing; in addition, the resulting in-band quantization error is lower than in conventional techniques. Several design considerations are given, and preliminary experimental results are presented.

A new predictive strategy for current control of a three-phase neutral point clamped inverter is presented. It is based on a discrete-time model of the system, used to predict future values of the load current and voltage of the capacitors in the DC-link, for each possible switching state generated by the inverter. The state that minimizes a given quality function "g" is selected to be applied during the next sampling interval. Several compositions of g are proposed, including terms dedicated to achieve reference tracking, balance in the DC-link and reduction of the switching frequency. The algorithm uses the redundancy of switching states, typical of a three-level inverter, by means of a simple strategy. In comparison with classic PWM current control, the strategy presents a remarkable performance. The proposed method achieves comparable reference tracking with lower switching frequency per semiconductor and a slightly improved transitory behavior. It requires a greater sampling frequency, which should not be a problem, considering the present technologies available in digital signal processors. The main advantage of the method is that it does not require any kind of linear controller or modulation technique, achieving a different approach to control a power converter.

Maximum power point tracking (MPPT) techniques are employed in photovoltaic (PV) systems to make full utilization of PV array output power which depends on solar irradiation and ambient temperature. Among all the MPPT strategies, the incremental conductance (INC) algorithm is widely used due to the high tracking accuracy at steady state and good adaptability to the rapidly changing atmospheric conditions. In this paper, a modified variable step size INC MPPT algorithm is proposed, which automatically adjusts the step size to track the PV array maximum power point. Compared with the conventional fixed step size method, the proposed approach can effectively improve the MPPT speed and accuracy simultaneously. Furthermore, it is simple and can be easily implemented in digital signal processors. A theoretical analysis and the design principle of the proposed method are provided and its feasibility is also verified by simulation and experimental results.

Immersive-Audio technologies are widely used to build experimental and commercial audio systems. However, most of them are based on standard PCs, which introduce performance limitations and excessive power consumption. To address these drawbacks, we explore the implementation prospectives of two Immersive-Audio technologies; the beamforming (BF) and the Wave Field Synthesis (WFS). We target two popular multicore platforms, namely Graphic Processor Units (GPUs) and Field Programmable Gate Arrays (FPGAs). We identify the most computationally intensive parts of both applications and employ the CUDA environment to map them onto a Quadro FX1700, a GeForce 8600GT, a GTX275 and a GTX460 GPU. Furthermore, we design our custom multi-core hardware accelerators for both algorithms and map them onto Virtex6 FPGAs. Both GPU and FPGA implementations are compared against OpenMP-annotated software running on a Core2 Duo at 3.0 GHz. Experimental results suggest that middle-range GPUs process data equally well as the Core2 Duo for the BF, and approximately two times faster for the WFS. However, high-end GPU and FPGA solutions provide an order of magnitude better performance for BF, and approximately two orders of magnitude better performance for WFS than the Core2 Duo. Ultimately, single-chip GPU and FPGA implementations can provide more power-effective solutions, since they can drive more complex microphone and loudspeaker setups than PC-based approaches.

This research paper aims at comparing two multi-core processors machines, the Intel core i7-4960X processor (Ivy Bridge E) and the AMD Phenom II X6. It starts by introducing a single-core processor machine to motivate the need for multi-core processors. Then, it explains the multi-core processor machine and the issues that rises in implementing them. It also provides a real life example machines such as TILEPro64 and Epiphany-IV 64-core 28nm Microprocessor (E64G401). The methodology that was used in comparing the Intel core i7 and AMD phenom II processors starts by explaining how processors' performance are measured, then by listing the most important and relevant technical specification to the comparison. After that, running the comparison by using different metrics such as power, the use of HyperThreading technology, the operating frequency, the use of AES encryption and decryption, and the different characteristics of cache memory such as the size, classification, and its memory controller. Finally, reaching to a roughly decision about which one of them has a better over all performance.

It is anticipated that there will shortly be a requirement for multimedia terminals that operate via mobile communications systems. This paper presents a functional specification for such a terminal operating at 32 kb/s in a digital European cordless telecommunications (DECT) and universal mobile telecommunications system (UMTS) radio network. A terminal has been built, based on a PC with digital signal processor (DSP) boards for audio and video coding and decoding. Speech coding is by a phonetically driven code-excited linear prediction (CELP) speech coder and video coding by a block-oriented hybrid discrete cosine transform (DCT) coder. Separate channel coding is provided for the audio and video data. The paper describes the techniques used for audio and video coding, channel coding, and synchronization. Methods of subjective testing in a DECT network and in a UMTS network are also described. These consisted of subjective tests of first impressions of the mobile audio-visual terminal (MAVT) quality, interactive tests, and the completion of an exit questionnaire. The test results showed that the quality of the audio was sufficiently good for comprehension and the video was sufficiently good for following and repeating simple mechanical tasks. However, the quality of the MAVT was not good enough for general use where high-quality audio and video was needed, especially when transmission was in a noisy radio environment.

We developed an embedded vision system that can accelerate the basic image processing functions for mobile robot navigation with compact hardware featuring low power consumption. The system is composed of a Digital Signal Processor (DSP) and a dedicated LSI for low-level image processing, specifically for spatial filtering, feature extraction, and block matching operations. The image processing LSI has a dedicated systolic array processor consisting of 64 processing elements to accelerate basic block operations for image feature calculation and correlation-based image matching. The power consumption is only 10 W, about one-seventh that of a typical Pentium 4 personal computer, but the processing speed for correlation matching is roughly three times faster than such a system. With this vision system, we implemented a stereo-visionbased navigation algorithm on our mobile service robot and performed a visual navigation experiment in a building hallway.

Overcurrent protection is a very important element in power systems. This protection is essential in order to minimize disturbances caused by any failure in the system and to ensure continuous power delivery. Overcurrent relays are one of the devices used to achieve these purposes. The overcurrent relays initiate the corrective mechanism to determine the operation time of the relay. Thus, the overcurrent relays must have high reliability and accuracy to detect any fault currents present and determine the operation time. The entire system will be tremendously affected if the relays fail to trip or cause mal-tripping. An overcurrent relay is implemented on a high speed and high performance digital signal processor (DSP). The simulation was carried out using MATLAB/Simulink. Then, the relay was implemented on TMS320F2812 based on two different methods. In the first method, the relay simulation model from MATLAB/Simulink is downloaded into the DSP whereas in the second method, code in C is directly written on the DSP to represent the relay. The relay performance was compared with the IEC 255-3 standard and the outcomes obtained are encouraging.

Ahtract -Systems modems intended for use in relatively large private networks are characterized by high performance, reliability and flexibility to support network management, and multiple modes of operation and user features. This paper describes a programmable digital signal processor which is teamed with a 16-bit microprocessor in a dual processor architecture satisfying the requirements of high-speed voiceband systems modems. The architecture of the two custom integrated circuits which form the basis of the signal processor is presented. This processor has novel arithmetic, data structure address generation, and program flow-control capabilities, which result in a high utilization of the arithmetic unit and a low program overhead for housekeeping tasks. Some of these features are illustrated by programming examples.

High performance general purpose Digital Signal Processor (DSP) provides a cost efficient solution for broadband Digital Subscriber Line (DSL) transceiver. A DSL modem with a transmission throughput between 400 kbps and 2 Mbps operating over most of existing telephone subscriber loops has been implemented on a single TI TMS320c548 DSP for consumer multimedia applications such as internet access. Except the Analog Front End (AFE), all the Discrete Multitone Modem (DMT) algorithms are implemented with DSP software. DSP based software DSL modem also provides a convenient interface to Microsoft point-to-point protocol (PPP) for network access.

The work aims to investigate into the modern concept of cognitive radio and details about its functioning. The ideas that led to its invention and the thoughts that led to this modern technology of using white spaces in the most efficient way. It aims to take a dig into the earlier radios namely the conventional radio and the software defined radio and later on modifications of those that ultimately led to cognitive radio. Not only that but it deals with every nuance between each of them. Various persons including the person who was the propagator of the concept of cognitive radio technology Dr. Joseph Mitola and various organizations have tried to define cognitive radio and the discussion considers all those definitions to let the reader get a clear picture regarding their understanding as far as defining cognitive radio is concerned. The requirements of cognitive radio in various fields and the future scope of the technology are profoundly dealt with. A network of cognitive radios known as cognitive radio network (CRN) is also the matter of discussion in the latter half of the work. Various components of the CRN and certain details regarding it are included with appropriate diagrams as per requirements

Due to their system complexity and high component cost, stepped frequency continuous wave radars have not been popular in the ground penetrating radar industry. However, over the last decade the cost of RF technologies has decreased considerably, making it more feasible to make SFCW GPRs. This paper discusses the implementation and development of a low cost SFCW GPR using digital radio technology, a homodyne single channel receiver and a digital signal processor. The radar operates over a bandwidth from 490 MHz to 780 MHz and is capable of taking a single depth profile measurement using 256 frequency steps in less than 0.5 seconds. The results of field trials are also presented

An effective scheme of induction motor control without using stator sensor is proposed in this paper. The effective scheme consist of speed calculation algorithm and voltage/frequency control. The speed calculation algorithm is achieved by sensoring the current of stator and compared with the prospective speed then calculation by DSP. The principles of constant voltage/frequency (V/Hz) control for AC Induction motor and sine wave generation of PWM technique are used. The control system has been tested at the real time operating conditions and the experimental results have shown that the system has good characteristic in steady state and during transient as well.

http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=04795975

A programmable/reconfigurable baseband chain with filter and amplifier sections that can be shared by two different wireless standards, GSM and DECT, is presented in this paper. This results in a simplified, low power and cost-effective design solution. Filters and amplifiers of the baseband chain were implemented using a fully balanced differential difference amplifier (FBDDA). A new approach is used to implement an analog to digital converter using the FBDDA in order to enhance the design regularity. The noise and linearity performance of individual stages was investigated, and simulations of the overall system showed that it complies with both standards under consideration. Using a suitable algorithm implemented by the digital signal processor (DSP) of the receiver, the chain could be configured to operate efficiently in different environments.

A novel method of estimating the rotor position and speed of a permanent magnet (PM) synchronous motor using a high-speed digital signal processor by measuring stator quantities is described. The basic idea of this method stems from exploiting the saliency characteristics of a PM synchronous machine. A complete vector control drive of a PM synchronous machine with position estimator has been simulated using the PC-based SIMNON program. The simulation results show that the performance of the machine with position estimator is in close agreement with that of a position sensor. Since the estimation algorithm needs few instructions, such as multiplications and additions and subtractions, it is well suited for real-time application using a high-speed digital signal processor

Sigma-delta modulation (Σ∆M) techniques provide a range of opportunities in a signal processing system for both increasing performance and datapath optimization along the siliconarea axis in the design space. Σ∆M technology, together with FPGA based signal processing hardware, can be combined to produce creative, high-performance and area efficient solutions to many signal processing problems.This paper presents several such examples. Σ∆M based DSP is employed to generate FPGA hardware implementations of narrow-band filters, a DC canceler and hybrid digital-analog control loops for a software defined radio architecture.

This paper presents an analytical framework for the implementation of digital infinite impulse response filters in fixed-point hardware on field programmable gate arrays. This analysis is necessary because FPGAs, unlike fixed register size digital signal processors, allow custom bit widths. Within the framework, the designer determines the number of bits necessary for representing the constant coefficients and the internal signals in the filter. The coefficient bit widths are determined by accounting for the sensitivity of the filter's pole and zero locations with respect to the coefficient perturbations. The internal signal bit widths are determined by calculating theoretical bounds on the ranges of the signals, and on the errors introduced by truncation in the fixed-point hardware. The bounds tell how many bits are required at any point in the computation in order to avoid overflow and guarantee a prescribed degree of accuracy in the filter output. The bounds form the basis for a methodology for the fixed-point digital filter implementation. The methodology is applied to the implementation of a second-order filter used as a compensator in a magnetic bearing control system.

Hardware and software needed to implement a 16-bit microprocessor-based, single-board digital signal processing system are outlined and discussed. As described, the system can perform high-speed dirital filtering and fast Fourier transforms in real time for signals of up to 35 kHz, and the basic architecture can be extended readily to handle higher frequency signals in real time.

This paper describes the proposed active power filter with the control circuit based on the modified instantaneous reactive power control algorithm. The control circuit was realized using digital signal processor ADSP-21065. In the proposed circuit a advanced current controller algorithm realized using the digital signal processor ADSP-21065 is employed. The active power filter circuit was build and tested. Some illustrative, experimental results are also presented in the paper.

Steganography is a science that focuses on hiding specific messages using specialized techniques in such a way as only the sender and the intended receiver are able to decipher it, as well as knowing of its existence. Important domains, besides classic computing, where steganography can be applied are domains using mobile and embedded devices especially mobile phones. This paper tries to state the fact that steganography can be successfully implemented and used into a next generation of mobile phones with image and video processing abilities. Important results presented in this article suggest the fact that steganography can be used inside mobile phones and tablets.

Problem statement: The Software Communications Architecture (SCA) was developed to improve software reuse and interoperability in Software Defined Radios (SDR). There had been performance concerns since its conception. Arguably, the majority of the problems and inefficiencies associated with the SCA can be attributed to the assumption of modular distributed platforms relying on General Purpose Processors (GPPs) to perform all signal processing. Approach: Significant improvements in cost and power consumption can be obtained by utilizing specialized and more efficient platforms. Digital Signal Processors (DSPs) present such a platform and have been widely used in the communications industry. Improvements in development tools and middleware technology opened the possibility of fully integrating DSPs into the SCA. This approach takes advantage of the exceptional power, cost and performance characteristics of DSPs, while still enjoying the flexibility and portability of the SCA. Results: This study presents the design and implementation of an SCA Core Framework (CF) for a TI TMS320C6416 DSP. The framework is deployed on a C6416 Device Cycle Accurate Simulator and TI C6416 Development board. The SCA CF is implemented by leveraging OSSIE, an open-source implementation of the SCA, to support the DSP platform. OIS's ORBExpress DSP and DSP/BIOS are used as the middleware and operating system, respectively. A sample waveform was developed to demonstrate the framework's functionality. Benchmark results for the framework and sample applications are provided. Conclusion: Benchmark results show that, using OIS ORBExpress DSP ORB middleware has an impact for decreasing the Software Memory Footprint and increasing the System Performance compared with PrismTech's e*ORB middleware.

In this paper, a novel wireless load-sharing controller for islanding parallel inverters in an ac-distributed system is proposed. The paper explores the resistive output impedance of the parallel-connected inverters in an island microgrid. The control loops are devised and analyzed taking into account the special nature of a low voltage microgrid, in which the line impedance is mainly resistive and the distance between the inverters makes the control intercommunication between them difficult. In contrast with the conventional droop control method, the proposed controller uses resistive output impedance, and as a result a different control law is obtained. The controller is implemented by using a DSP board, which only uses local measurements of the unit, thus increasing the modularity, reliability, and flexibility of the distributed system. Experimental results are provided from two 6 kVA inverters connected in parallel, showing the features of the proposed wireless control.

This paper presents a reconfigurable processor for different digital signal processing applications. The performance of the proposed architecture has been evaluated by taking different dsp applications like Low pass filter, high pass filter, finite impulse response (FIR) filter and FFT module. We designed the architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate it in the FPGA, which show that the hardware scheme is feasible for practical application. The experimental results clearly reveal the novelty of the architecture for dsp applications. This paper investigates the potential use of FPGAs for implementing efficient " Reconfigurable Processor " for different dsp applications. The proposed processor is based on parallel re-configurable which is implemented on FPGA. FPGAs have become an important component for implementing these functions with respect to cost, performance and flexibility. The general purpose SPARTAN 3AN FPGA kit has been employed for developing reconfigurable processor, with all the coding done using the hardware description language VERILOG.

This paper describes the design and the implementation of a self-tuning integral-proportional (IP) speed controller for a rolling mill dc drive system, based on a 32-bit floating point Digital Signal Processor @SP)-TMS 3 2 0 0 . To get a better transient response than conventional proportional-integral (PI) and/or integral-proportional (IP) speed control in the presence of transient disturbance and/or parameter variations, an adaptive self-tuning IP speed control with load torque feedforward compensation was used. The model parameters, related to motor and load inertia and damping coefficient, were estimated online by using recursive extended least squares (RELS) estimation algorithm. On the basis of the estimated model parameters and a pole-placement design, a control signal was calculated. Digital simulation and experimental results showed that the proposed controller possesses excellent adaptation capability under parameter change and a better transient recovery characteristic than a conventional PYIP controller under load change. The operation of the Laplace transform yields the following transfer function relationship: (2) out in a DSP and the estimated parameters correspond, of KtIdC(S) -T L ( S ) J s + B w,(s) = where . J.-K. Ji is with the DeDartment of Control and Instrumentation. Soonchun-J motor and load inertia, B viscous friction, hyang University, Chungnam, Korea 337-745. Universitv, Seoul, Korea 15 1-742. Kt motor torque constant, T, mechanical time constant (= J I B ) , and S.-K. Sul is with the Department of Electrical Engineering, Seoul National IEEE L g Number 9412496.

In this paper, a digital signal processor-based phasesensitive motor fault signature detection technique is presented. The implemented method has a powerful line current noise suppression capability while detecting the fault signatures. Because the line current of inverter-driven motors involve low-order harmonics, high-frequency switching disturbances, and the noise generated by harsh industrial environment, the real-time fault analyses yield erroneous or fluctuating fault signatures. This situation becomes a significant problem when the signal-to-noise ratio of the fault signature is quite low. It is theoretically and experimentally shown that the proposed method can determine the normalized magnitude and phase information of the fault signatures even in the presence of noise, where the noise amplitude is several times higher than the signal itself. Since it has low computational burden, the developed algorithm is embedded to the motor control program without degrading drive performance. Therefore, it is implemented without any additional cost using readily available drive processor and current sensors.

This paper describes a digital control method for single-phase grid-connected inverter system with an LCL filter for distributed generation application. Digital PI Current Controller is applied as the control method. The control algorithm is implemented in low cost Digital Signal Processor (DSP) TMS320F2812 eZdsp board. The control method provides robust current regulation and achieve unity power factor. Simulation and experimental results are provided to demonstrate the effectiveness of the design.

In this paper, a new nonlinear control strategy is proposed for a permanent-magnet salient-pole synchronous motor. This control strategy simultaneously achieves accurate torque control and copper losses minimization without recurring to an internal current loop nor to any feedforward compensation. It takes advantage of the rotor saliency by allowing the current (i d ) to have nonzero values. This, in turn, allows us to increase the power factor of the machine and to raise the maximum admissible torque. We apply input-output linearization techniques where the inputs are the stator voltages and the outputs are the torque and a judiciously chosen new output. This new output insures a well-defined relative degree and is linked to the copper losses in such a way that, when forced to zero, it leads to maximum machine efficiency. The performance of our nonlinear controller is demonstrated by a real-time implementation using a digital signal processor (DSP) chip on a permanent-magnet salient-pole synchronous motor with sinusoidal flux distribution. The results are compared to the ones obtained with a scheme which forces the i d current to zero.

This paper addresses the problem of improving the execution performance of saturated reduction loops on fixed-point instructionlevel parallel Digital Signal Processors (DSPs). We first introduce "bitexact" transformations, that are suitable for use in the ETSI and the ITU speech coding applications. We then present "approximate" transformations, the relative precision of which we are able to compare. Our main results rely on the properties of the saturated arithmetic.

This paper presents simulation and hardware implementation of incremental conductance (IncCond) maximum power point tracking (MPPT) used in solar array power systems with direct control method. The main difference of the proposed system to existing MPPT systems includes elimination of the proportional-integral control loop and investigation of the effect of simplifying the control circuit. Contributions are made in several aspects of the whole system, including converter design, system simulation, controller programming, and experimental setup. The resultant system is capable of tracking MPPs accurately and rapidly without steady-state oscillation, and also, its dynamic performance is satisfactory. The IncCond algorithm is used to track MPPs because it performs precise control under rapidly changing atmospheric conditions. MATLAB and Simulink were employed for simulation studies, and Code Composer Studio v3.1 was used to program a TMS320F2812 digital signal processor. The proposed system was developed and tested successfully on a photovoltaic solar panel in the laboratory. Experimental results indicate the feasibility and improved functionality of the system. Index Terms-Digital signal processor (DSP), incremental conductance (IncCond), maximum power point tracking (MPPT), photovoltaic (PV) system. I. INTRODUCTION R ECENTLY, energy generated from clean, efficient, and environmentally friendly sources has become one of the major challenges for engineers and scientists [1]. Among all renewable energy sources, solar power systems attract more attention because they provide excellent opportunity to generate electricity while greenhouse emissions are reduced [1]-[3]. It is also gratifying to lose reliance on conventional electricity generated by burning coal and natural gas. Regarding the endless aspect of solar energy, it is worth saying that solar energy is a unique prospective solution for energy crisis. However, despite all the aforementioned advantages of solar power systems, they do not present desirable efficiency [4], [5]. The efficiency of solar cells depends on many factors such as temperature, insolation, spectral characteristics of sunlight, dirt, shadow, and so on. Changes in insolation on panels due to fast climatic changes such as cloudy weather and increase Manuscript

Problem statement: The Software Communications Architecture (SCA) was developed to improve software reuse and interoperability in Software Defined Radios (SDR). There had been performance concerns since its conception. Arguably, the majority of the problems and inefficiencies associated with the SCA can be attributed to the assumption of modular distributed platforms relying on General Purpose Processors (GPPs) to perform all signal processing. Approach: Significant improvements in cost and power consumption can be obtained by utilizing specialized and more efficient platforms. Digital Signal Processors (DSPs) present such a platform and have been widely used in the communications industry. Improvements in development tools and middleware technology opened the possibility of fully integrating DSPs into the SCA. This approach takes advantage of the exceptional power, cost and performance characteristics of DSPs, while still enjoying the flexibility and portability of the SCA. Results: This study presents the design and implementation of an SCA Core Framework (CF) for a TI TMS320C6416 DSP. The framework is deployed on a C6416 Device Cycle Accurate Simulator and TI C6416 Development board. The SCA CF is implemented by leveraging OSSIE, an open-source implementation of the SCA, to support the DSP platform. OIS's ORBExpress DSP and DSP/BIOS are used as the middleware and operating system, respectively. A sample waveform was developed to demonstrate the framework's functionality. Benchmark results for the framework and sample applications are provided. Conclusion: Benchmark results show that, using OIS ORBExpress DSP ORB middleware has an impact for decreasing the Software Memory Footprint and increasing the System Performance compared with PrismTech's e*ORB middleware.

As the performance of digital signal processors has increased rapidly during the last decade, there is a growing interest to replace the analog controllers in low power switching converters by more complicated and flexible digital control algorithms. Compared to high power converters, the control loop bandwidths for converters in the lower power range are generally much higher. Because of this, the dynamic properties of the uniformly-sampled pulse-width modulators used in low power applications become an important restriction to the maximum achievable bandwidth of control loops. Though frequency-and Laplace-domain models for uniformly-sampled pulse-width modulators are very valuable as they improve the general perception of the dynamic behavior of these modulators, the direct discrete design of the digital compensator requires a zdomain model for the combination modulator and converter. For this purpose a new exact small-signal z-domain model is derived. In accordance with the zero-order-hold equivalent commonly used for 'regular' digital control systems, this z-domain model gives rise to the development of a uniformly-sampled pulse-widthmodulator equivalent of the converter. This z-domain model is characterized by its capability to quantify the different dynamics of the converter for different modulators, its ease of use and its ability to predict the values of the control variables at the true sampling instants of the real system.

A digital signal processor (DSP)-based FFT analyzer capable of adapting its behavior according to specific application requirements was set up. A suitably designed user-interface allows both the specific application to be chosen and its main parameters to be defined. An automatic optimization procedure then reorganizes the instrument configuration in order to meet user requirements. Multi-DSP architecture implementation ensures real-time behavior. The experimental test results indicate that the instrument is capable of optimally operating in a large number of typical applications.