Damping factor

The increasingly demanding performance requirements of communications systems, as well as problems posed by the continued scaling of silicon technology, present numerous challenges for the design of frequency synthesizers in modern transceivers. This book contains everything you need to know for the efficient design of frequency synthesizers for today's communications applications. If you need to optimize performance and minimize design time, you will find this book invaluable. Using an intuitive yet rigorous approach, the authors describe simple analytical methods for the design of phase-locked loop (PLL) frequency synthesizers using scaled silicon CMOS and bipolar technologies. The entire design process, from system-level specification to layout, is covered comprehensively. Practical design examples are included, and implementation issues are addressed. A key problem-solving resource for practitioners in integrated-circuit design, the book will also be of interest to researchers and graduate students in electrical engineering.

A phase-locked optical heterodyne receiver was constructed using a 1320 nm diode-pumped miniature Nd:YAG ring laser. Using that receiver and a transmitter based on another Nd:YAG laser, a 560 Mbh PSK synchronous heterodyne transmission was demonstrated over 78 km of single-mode fiber. With an optical phase-locked loop natural frequency of 32 kHz and a damping factor of 1.46, the receiver sensitivity, measured at the output of the transmission link, was-48.7 dBm or 159 photonshit. The corresponding sensitivity, measured on the surface of the p-in diode, was-51.8 dBm or 78 photonshit. This result suggests that the receiver sensitivity would have been about 80 photonshit if a balanced receiver, with 0.1 dB excess coupler loss, had been used. We investigated, for the first time, the impact of the finite intermediate frequency (IF) on heterodyne system performance and showed that an IF of at least twice the bit rate is needed for a negligibly small penalty.

To enhance the performance and to minimize the limited bandwidth error occurred in phase - locked loop, we proposed a method for modelling and behavioural simulation of a 3rd order phase - locked loop by considering two 2nd order active filter topologies, namely: (i) ideal multiple feedback approach, and (ii) filter with compensated multiple feedback approach in the loop. The s – domain transfer functions are simulated by using MATLAB to study the stability and different design aspects of the system. In ideal multiple feedback approach, the operational amplifier produces errors into the magnitude and phase responses of the filter because of limited gain bandwidth. To overcome this problem, we have proposed a filter with compensated multiple feedback approach in the loop.