Sapphire Nanopores for Low-Noise DNA Sensing

1 Sapphire Nanopores for Low-Noise DNA Sensing 2 3 4 5 6 7 8 9 10 11 Pengkun Xia1,2,3, Jiawei Zuo1,2,3, Pravin Paudel1,2, Shinhyuk Choi1,2,3, Xiahui Chen1,2,3, Weisi Song4, JongOne Im4, 5, Chao Wang1,2,3* 1 School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA 2 Center for Photonic Innovation, Arizona State University, Tempe, AZ, USA 3 Biodesign Center for Molecular Design & Biomimetics, Arizona State University, Tempe, AZ, USA 4 Biodesign Center for Single Molecule Biophysics, Arizona State University, Tempe, AZ, USA 5 Curent Address: INanoBio Inc., Scottsdale, AZ, USA *E-mail: [email protected] 12 Abstract 13 Solid-state nanopores have broad applications in single-molecule biosensing and diagnostics, but 14 their high electrical noise associated with a large device capacitance has seriously limited both 15 their sensing accuracy and recording speed. Current strategies to mitigate the noise has focused on 16 introducing insulating materials (such as polymer or glass) to decrease the device capacitance, but 17 the complex process integration schemes diminish the potential to reproducibly create such 18 nanopore devices. Here, we report a scalable and reliable approach to create nanopore membranes 19 on sapphire with triangular shape and controlled dimensions by anisotropic wet etching a 20 crystalline sapphire wafer, thus eliminating the noise-dominating stray capacitance that is intrinsic 21 to conventional Si based devices. We demonstrate tunable control of the membrane dimension in 22 a wide range from ~200 μm to as small as 5 μm, which corresponds to <1 pF membrane capacitance 23 for a hypothetical 1-2 nm thick membrane. Further, we have demonstrated that a sapphire nanopore 24 chip (~7 nm pore diameter in a 30 nm thick and 70 µm wide SiN membrane) has more than two- 25 order-of-magnitude smaller device capacitance (10 pF) compared to a float-zone Si based 26 nanopore chip (4 nm pore in 23 nm thick and ~4 µm wide SiN membrane, ~1.3 nF), despite having 27 a 100 times larger membrane area. The sapphire chip has a current noise of 18 pA over 100 kHz 28 bandwidth at a 50 mV bias, much smaller than that from the Si chip (46 pA) and only slightly 1 29 larger than the open-headstage system noise (~11 pA). Further, we demonstrate that the sapphire 30 nanopore chip outperforms the Si chip with a higher signal-to-noise ratio (SNR, 21 versus 11), 31 despite of its thicker membrane and larger nanopore size. We believe the low-noise and high-speed 32 sensing capability of sapphire nanopore chips, together with their scalable fabrication strategy, 33 will find broad use in a number of applications in molecular sensing and beyond. 2 34 35 Introduction Solid-state nanopores have attracted a lot of interest as a potentially high-speed, portable and 1, 2, 3, 4 , RNA 5, 6, 7 and 36 low-cost solution for detecting a variety of biomolecules, such as proteins 37 DNA 8, 9, 10, and studying molecular interactions 11, 12. However, fundamental limitations in design 38 and manufacturing of low-noise nanopore devices still remain. Currently, a major challenge in 39 prevalent silicon (Si) based solid-state nanopore sensing is associated with a large device 40 capacitance resulted from the Si conductivity. This capacitance introduces a large noise current 41 that becomes particularly dreadful at high recording frequency, thus causing serious reading errors. 42 To mitigate the noise, molecular sensing is often performed at a low bandwidth (e.g. 1 to 10 kHz), 43 despite the availability of low-noise, low-current amplifiers operating at much higher (100 kHz 44 and 1 MHz) bandwidth 45 temporal resolution to ~100 microseconds, in face of the fact that the typical translocation time of 46 a single DNA base pair lies in the range 10-1,000 nanoseconds 13, 14. To resolve the signals with a 47 high fidelity, a number of methods have been proposed to slow down the DNA translocation speed 48 by reducing its mobility 49 resorting to these methods would introduce high complexity in experiments and decrease the 50 signal-collecting throughput. . Yet, demoting recording bandwidth seriously limits the signal 25, 26, 34 15, 16 or the effective external DNA-driving force 15, 17, 18, 19 . However, 51 In fact, an alternative is to reduce the noise from the sensing system and the nanopore device 52 (more details in supplementary note 1). For instance, a recent demonstration using a customized 53 CMOS amplifier and a small-capacitance chip has demonstrated high-speed response of sub- 54 microsecond temporal resolution 20. Indeed, the Si chip capacitance can be as large as nano-farad 55 range if not carefully engineered (Figure S1c and Table S1). To minimize the stray capacitance, 56 conventional techniques (Table S2) introduce a thick insulating material at the nanopore vicinity 3 57 20, 21, 22, 23, 24 58 surrounding areas, or a combination of the two. However, many critical fabrication steps require 59 complex fabrication and manual operation, such as thick dielectric deposition, selective membrane 60 thinning, electron beam lithography, silicone/photoresist printing, glass bonding, etc, and thus are 61 very expensive, slow, and difficult to reproduce. An alternative is to replace conductive silicon by 62 an insulating material, such as glass 63 substrate presents complex fabrication schemes involving multiple steps of lithography, laser 64 pulling or glass etching. Even then, the process lacks precise control of the membrane 65 characteristics, causing problems in low fabrication yield, poor reproducibility, and low 66 throughput. , e.g. by selective thinning a thick membrane, dielectric coating at nanopore- 25, 26, 27, 28 . However, the amorphous nature of the glass 67 In this study, we demonstrate a manufacturable approach to create thin membranes with well- 68 controlled dimension and shape on a crystal sapphire wafer, which completely eliminates the stray 69 capacitance from conventional Si substrate. Here, we design a triangular membrane by leveraging 70 the three-fold symmetry of the sapphire lattice, and employ a batch-processing compatible 71 anisotropic sapphire wet etching process to create sapphire chips over a wafer scale. We 72 demonstrate controlled membrane dimension in a wide range from ~200 μm to as small as 5 μm, 73 which theoretically corresponds to pico-Farad level total chip capacitance even considering 74 nanometer-thin membranes needed in high-sensitivity DNA detection. Comparing to a float-zone 75 Si based nanopore chip, a sapphire nanopore chip with a 100 times larger membrane area still has 76 more than two-order-of-magnitude smaller device capacitance and only about one third of current 77 noise measured over 100 kHz bandwidth. Further, the sapphire nanopore outperforms the Si 78 nanopore in high-frequency detection of DNA molecules, demonstrating twice as high SNR 79 despite of having about twice as large pore diameter and 30% thicker membrane. Clearly, further 4 80 decreasing the membrane area and thickness and creating smaller nanopores will greatly improve 81 the detection SNR of sapphire nanopores for high-speed molecular diagnostics in a wide range of 82 applications. 83 84 Results and discussion 85 Silicon oxide (SiO2) supporting membrane formation 86 We have devised a new strategy to create suspended dielectric membranes on sapphire by 87 anisotropic wet etching (details in Methods section). Briefly, we started with cleaning a bare 2- 88 inch c-plane (0001) sapphire wafer (Figure 1a) by RCA2 prior to depositing silicon dioxide (SiO2) 89 by plasma-enhanced chemical vapor deposition (PECVD) on both sides (Figure 1b). SiO2 is used 90 here for its high-selectivity in sapphire etching, experimentally determined by us as ~500:1. This 91 was followed by thermal annealing to release the SiO2 stress, which otherwise would result in film 92 crack during high-temperature sapphire etching (Figure S2). Then we patterned one side (cavity 93 side) of the SiO2 by photolithography and reactive-ion etching (RIE) into a triangular shaped mask 94 layer (Figure 1c). Subsequently, hot sulfuric acid and phosphoric acid were used to etch through 95 the sapphire wafer to suspend the SiO2 membrane as a supporting layer (Figure 1d). 96 Considering the three-fold symmetric crystal structure of c-plane sapphire wafer, we designed 97 the SiO2 etching window as a triangle to control the membrane shape and dimension. The sapphire 98 facet evolution is highly dependent on the alignment of the etching mask to the sapphire crystal, 99 similar to anisotropic Si etching, but more complex given its hexagonal lattice nature 29, 30 . We 100 studied the geometry evolution of the SiO2 membrane by rotating the SiO2 membrane relative to 101 the sapphire crystal (Figure S3). In another word, we kept the triangular mask dimension the same 102 but changed its alignment angle to the sapphire flat (A-plane), denoted as window-to-flat angle 𝛼, 5 103 and indeed found intriguing formation of membranes. For example, two different sets of triangular 104 105 membranes were formed when 0 < 𝛼 < 20° and 40° < 𝛼 < 60°, with a rotational angle offset 106 when 20° <𝛼< 40°, where six of the sides were parallel to the sides of the above-mentioned two 107 triangular membranes. Additionally, the membrane area was also found sensitive to 𝛼, yielding an 108 between the two at ~30°. In contrast, complex polygon membranes with up to nine sides emerged area of more than three orders of magnitude larger when 𝛼~30° compared to 𝛼~0°. Here we 109 believe the facet evolution is related to the etching rate differences between different sapphire 110 crystal planes. Given that the M- and A- planes have very slow etching rates and are perpendicular 111 to the c-plane, they are believed to be less relevant in the observed cavity formation. We suspect 112 that the R- and N-planes of the sapphire crystals are most relevant 31, and their competition could 113 result in the angle-dependent evolution into membranes in triangles or nonagon. Drastically 114 different from the triangular design, square window design produced irregular and complex 115 membranes that are much more difficult to control (Figure S4). 116 Here we chose a designed alignment angle of 𝛼~0° and we performed theoretical calculation 117 to estimate the relationship between the membrane and the mask dimensions (details in 118 supplementary note 2), and determined that the membrane triangle length 𝐿2 could be simply 120 engineered by the mask triangle length 𝐿1 following 𝐿1 = 𝐿2 + 2√3ℎ/ 𝑡𝑎𝑛 𝜃 (Figure 2a), where 121 cavity and sapphire c-plane that can be empirically determined. 119 ℎ is the sapphire wafer thickness and 𝜃 is an effective angle between the exposed facets in the 122 We also intentionally included rectangular dicing marks surrounding the cavity etching 123 windows during lithography, creating trenches in sapphire after acid etching that allowed us to 124 hand-dice sapphire into 5 mm by 5 mm square chips (Figure 2c), which would otherwise be very 125 challenging given the hexagonal lattice of sapphire. This 5 mm chip size was designed to fit into 6 126 our fluidic jig and transmission electron microscopy (TEM) holder for nanopore drilling and 127 electrical characterization. The final obtained SiO2 membrane on sapphire was 3 µm thick, and 128 intact during the etching and chip dicing process (Figure 2d-e). The SiO2 thickness was only 129 reduced slightly from the original 3.5 µm while masking the etching of 250 μm sapphire, indicating 130 131 an ultra-high etching selectivity of ~500:1. The SiO2 membrane size 𝐿2 was also found tunable in 132 corresponds to a theoretical pico-farad chip capacitance even for nanometer-thin membranes (e.g. 133 ~0.3 pF membrane capacitance for a hypothetical 2 nm thick SiN membrane (dielectric constant 134 = 6.5), ~0.2 pF sapphire cavity capacitance and ~1.4 pF sapphire substrate capacitance within the 135 o-ring area. Details in Table S3), which are highly desired for high-SNR 6, 32 DNA detection. We 136 137 further fitted the correlation between 𝐿1 and 𝐿2 using our theoretical model, and determined an 138 effective facet angle 𝜃~50° (Figure S5d). This experiment proved that it was possible to control and create ultrasmall membranes for functional sapphire chips. It was also intriguing to notice the 139 complex sapphire facets from scanning-electron microscope (SEM) image of the formed cavity 140 (Figure S6a), attributed to the complex crystal structure of sapphire and particularly possibly due 141 to the competition between R- and N-planes of the sapphire crystals. a wide range from 5 to 200 µm (Figure 2f-g, more images in Figure S5a). The 5 µm membrane 142 143 SiN thin membrane formation 144 Using the triangular SiO2 membranes formed by sapphire etching, we have developed a process 145 to create thin SiN membranes suitable for nanopore formation and DNA sensing 6. Briefly, we 146 deposited low-stress SiN film on the suspended SiO2 membranes by low-pressure chemical vapor 147 deposition (LPCVD), and then removed the SiO2 film within the triangular aperture via selective 148 dry etching and HF based wet etching from the cavity side (Figure 1f). Using the SiN film instead 7 149 of the remaining SiO2 mask layer as the membrane material allows us to precisely control the 150 membrane thickness, and largely eliminates high compressive stress from the SiO2 layer that 151 negatively affects the membrane integrity. To thin down the SiN membrane to desired thickness, 152 we evaluated both reactive ion etching (RIE) and hot phosphoric acid based wet etching. We found 153 that RIE could cause non-uniformity (Figure S7a) and might damage the membrane, causing 154 current leakage, as shown by current-voltage (IV) characteristics using one molar potassium 155 chloride solution (1M KCl) (Figure S7b). In contrast, hot phosphoric acid wet etching yielded 156 uniform SiN membrane (Figure S7c and Figure S8b) without current leakage (Figure S7d), thus 157 preferable for the DNA sensing test. Finally, a nanopore was drilled on the SiN membrane on the 158 sapphire chip (Figure 3 a-b) and a float-zone Si chip (SiMPore Inc., Figure S9), the best high- 159 resistivity chips available to us as a reference, by TEM (Figure 1g) for electrical characterization 160 and DNA sensing test. 161 162 Noise characterization 163 First we experimentally characterized the device capacitance of the sapphire and Si nanopore 164 chips. Noticeably, the sapphire chip had a 100 times larger membrane area (68 μm triangular side 165 length, or ~2000 μm2) than the Si chip (4.2 × 4.7 μm square, or ~20 μm2) and slightly thicker SiN 166 (30 nm for sapphire and 23 nm for Si). Following 𝐶𝑚 = 𝜀𝑟 𝜀0 , where 𝐶𝑚 is the membrane 167 𝐴 𝑑 capacitance, 𝜀𝑟 is the relative permittivity of SiN, 𝜀0 is the vacuum permittivity, 𝐴 is the 169 membrane area and 𝑑 is the membrane thickness, we calculated the sapphire membrane 170 sapphire chip was experimentally found to have a much smaller total capacitance (~10 pF) 171 compared to the Si chip (1.34 nF) using the Clampex software (Molecular Devices, LLC). This 168 capacitance as 3.8 pF, more than 70 times bigger than that of the Si chips (0.05 pF). However, the 8 172 clearly demonstrated that the use of insulating sapphire successfully eliminated the dominant 173 capacitance resulted from substrate conductivity, thus appealing to low-noise measurement. 174 We further analyzed the ionic current noise for the sapphire nanopore, the Si nanopore and the 175 open-headstage system (Axopatch 200B) under 10 kHz and 100 kHz low-pass filter (Figure 3c). 176 The root-mean-square (RMS) of the measured current of the sapphire nanopore chip is ~5 and 18 177 pA using 10 and 100 kHz filters, only slightly higher than the open-stage values of 3 and 11 pA 178 but much better than those from Si nanopore (~16 and 46 pA). Additionally, the power spectral 179 density (PSD) of Si and sapphire nanopores (Figure 3d) demonstrated that the noise power of 180 sapphire nanopore was about one order larger than the Si nanopore for a wide range of bandwidth, 181 consistent with its low-current-noise performance. The noise power of the sapphire nanopore at 182 low frequency range (<100 Hz) was slightly higher than Si, which could result from the flicker 183 noise and the large dielectric noise due to the large membrane size in the sapphire nanopore 184 Comparing with the existing noise-mitigating techniques 22, 24, 27, 28, 34, 35 (Table S2), our sapphire 185 nanopore requires no additional or manual fabrication steps to reduce the device capacitance. This 186 batch-processing-compatible design and fabrication strategy makes sapphire an excellent 187 candidate for low-noise and high-frequency nanopore sensing at a low cost. 33 . 188 189 DNA detection 190 To evaluate the performance in the detection of DNA molecules by our sapphire nanopore, 191 1kbp ds-DNA translocation events were measured under 100 kHz (Figure 4) and 10 kHz (Figure 192 S10) low-pass filter for both the sapphire and the Si nanopore under 50 mV, 100 mV and 150 mV 193 bias. Comparing representative ionic current traces of 1kbp dsDNA (Figure 4b) for both Si and 194 sapphire nanopores, we note that the DNA signals collected by Si nanopore were more irregular, 9 195 particularly at lower bias voltages. These irregular signals, together with the high baseline noise, 196 made it very challenging to faithfully distinguish DNA signals from the background. In 197 comparison, the sapphire nanopore produced much cleaner DNA signals at 100 kHz bandwidth 198 that can be easily separated from the noise. Additionally, we also show that recording at lower 199 frequencies (such as 10 kHz) would result in serious data loss of the fast DNA signals, thus 200 presenting only longer and in some occasions distorted signals 34, 36. Clearly, sapphire nanopores 201 enable preferable high-speed, high-throughput, and high-fidelity detection of DNA signals. 202 To study the DNA translocation mechanism, we extracted the DNA signals by OpenNanopore 203 Program 37. We scatter-plotted the fractional blockade current IB (=ib/i0) and the dwelling time ∆t 204 of all the DNA events from the sapphire chip under 50 mV (Figure 4c). Here ib is the blocked-pore 205 current and i0 is the open pore current. The use of IB allowed us to eliminate the impact of bias 206 difference on DNA signal analysis. Two distinct populations were observed (separated by the red 207 dashed line in Figure 4d) and recognized as the translocation events (green oval) and the collision 208 events (pink oval) 209 Gaussian function (Figure 4d), producing two distinct IB populations attributed to translocation 210 and collisions. We further analyzed the dwelling time ∆t of each of the two event populations and 211 fitted with exponential decay function (black lines, Figure 4e). It showed that the translocation 212 events (green, top panel) had a longer tail (decay constant=16.19 µs) than the collision events 213 (decay constant=8.45 µs), consistent with previous studies 11. 11 . Further, we analyzed the current blockade distribution and fitted with 214 We further applied this signal segregation approach to analyze all the DNA signals collected 215 from the Si and sapphire nanopores (Figure 5 a-d). By scatter-plotting the normalized DNA 216 blockade signal (1-IB =∆I/i0) and marking the current noise (IRMS, dash-dot lines) at each bias 217 voltage (black: 50 mV, red: 100 mV, blue: 150 mV, Figure 5e-f), we could investigate the SNR 10 218 219 1−𝐼𝐵 (defined here as 𝐼 𝑅𝑀𝑆 ) of the true DNA translation signals. The short solid lines represented the average DNA signals (1-IB) determined from the Gaussian distribution of the translocation events 220 (Figure 5b, d). The sapphire nanopores produced slightly smaller DNA signal amplitude than Si 221 nanopores, because of their larger pore size and thicker membrane. However, given the suppressed 222 noise current, the sapphire nanopore still evidently outperformed Si nanopore in SNR. For example, 223 the sapphire nanopore had a SNR of 21 at 150 mV bias, almost twice as good as the Si nanopore. 224 We further attempted to detect short single-stranded (ss) DNA molecules using sapphire 225 nanopores (Figure 6). Here ionic current traces of Poly(A)40 ssDNA translocation events were 226 recorded under 100 kHz low-pass filter with the voltages from 100 mV to 150 mV. We performed 227 the same analysis to investigate the SNR of this ssDNA (Figure 6b and Figure S11), and obtained 228 a SNR of ~6 for both 100 mV and 150 mV bias voltages. This provided evidence that the sapphire 229 nanopores can detect a wide range of biomolecules of different sizes. We expect the SNR can be 230 remarkably enhanced by using thinner membrane thickness and small nanopore in future studies. 231 232 Conclusion 233 In conclusion, we demonstrate a novel design and manufacturable approach to create sapphire 234 nanopores featuring triangular membranes with well-controlled dimensions and shapes. 235 Completely eliminating the stray capacitance, the sapphire nanopores convincingly produced two- 236 order-of-magnitude smaller device capacitance compared to a float-zone Si based nanopore (10 237 pF versus ~1.3 nF) despite having a 100 times larger membrane area. Accordingly, the sapphire 238 nanopores generated ~5 times smaller RMS ionic current noise than a Si nanopore at 100 kHz 239 bandwidth, and resulted in high-fidelity DNA sensing with a twice higher SNR while having a 240 larger nanopore size and thicker SiN membrane. This novel sapphire nanopore sensor architecture 11 241 will enable a new way of high-volume and cost-effective manufacturing of low-noise solid-state 242 nanopores for detecting a wide range of biomolecules and studying the fundamental biophysics 243 and molecule-molecule interactions at single-molecule level. 12 244 Methods 245 (1) Sapphire nanopore membrane fabrication 246 Firstly, a 250 μm thick 2-inch c-plane sapphire wafer (Precision Micro-Optics Inc.) was treated by 247 RCA2 cleaning (deionized water: 27% hydrochloric acid: 30% hydroperoxide = 6: 1: 1, 70 °C) for 248 15 min followed by 3.5 μm PECVD SiO2 deposition (Oxford PECVD, 350 °C, 20 W, 1000 mTorr, 249 SiH4 170 sccm, N2O 710 sccm, deposition rate: 68 nm/min) on both sides. Then the wafer was 250 brought in a furnace for thermal annealing (400 °C, 2 hrs, air ambient) to release the stress in SiO2 251 film, followed by photolithography (Heidelberg Instruments μPG 101 laser writer, 600 nm AZ 252 1505 photoresist) and RIE (PlasmaTherm 790 RIE Fluorine, 250 W bias, 40 mTorr, CHF3 40 sccm, 253 O2 3 sccm, etching rate: 46 nm/min) etching on SiO2 to form a triangular etching window. Next, 254 hot sulfuric acid and phosphoric acid (3:1, hot plate 540 °C) were used to etch through the sapphire 255 wafer (etching rate: 12 µm/hr) and suspend the SiO2 membrane. To ensure the safety of handling 256 hot and concentrated acids, we custom-designed a quartz glassware setup suitable for high- 257 temperature acid-based sapphire etching process. We intentionally placed the sapphire wafer 258 vertically in a 2-inch glass boat in the etching container to minimize possible damage to the 259 membrane by the boiling acids (Figure S12). After the acid was added into the quartz glassware, 260 we loaded the 2-inch glass boat with the wafer into the quartz glassware, and installed a clamp seal 261 and a condenser column to minimize acid vapor leakage. Finally we raised up the temperature of 262 the hot plate to 540 °C (100-200 °C/min) to start the etching. Following that, the SiO2 membrane 263 was thinned down by RIE (PlasmaTherm 790 RIE Fluorine, 250 W bias, 40 mTorr, CHF3 40 sccm, 264 O2 3 sccm, etching rate: 46 nm/min) to 1.45 µm, and a layer of SiN (320 nm) was deposited onto 265 the SiO2 membrane by LPCVD (Tystar TYTAN 4600, 250 mTorr, DCS flow 25 sccm, NH3 flow 266 75 sccm, 750 °C, deposition rate: 6 nm/min). SiN unintentionally deposited in the back cavity of 13 267 the chip was removed by a RIE etching step (PlasmaLab 80 Fluorine, 100 W bias, 100 mTorr, CF4 268 50 sccm, O2 2 sccm, etching rate: 61 nm/min). Then hydrofluoric acid (8%) was used to remove 269 the SiO2 layer to suspend the SiN layer (90 nm/min). The final SiN membrane was thinned down 270 by hot 85% phosphoric acid (hot plate 245 °C, etching rate: ~25 nm/min) to desired thickness. 271 272 (2) Si nanopore membrane fabrication 273 The Si nanopore membranes were purchased from SiMPore Inc. A 100 mm diameter 200 µm thick 274 float-zone Si wafer with ~100 nm thermal SiO2 and ~20 nm LPCVD SiN was etched by alkali to 275 create a Si cavity array. Then the thermal SiO2 was removed to produce an array of 4-5 µm 276 suspended SiN membranes. Then SiO2 and SiN film thicknesses were confirmed by M-2000 277 ellipsometer (J.A. Woollam Co.) as 99nm and 23nm by us. 278 279 (3) Thickness characterization on the small membranes 280 The thicknesses of membranes were measured by Filmetrics F40 (Filmetrics Inc.), which has the 281 capability to measure small area and is based on the reflectance and the refractive index of the 282 measured material. For the LPCVD SiN membranes, the refractive index was first fitted using the 283 same-batch LPCVD SiN deposited on Si by Woollam Spectroscopic Ellipsometer (J.A. Woollam 284 Co.). Then the refractive index list was exported to Filmetrics F40 to measure the thickness of the 285 SiN suspended membrane (film stack: air-SiN-air). A well-fitting curve of the central region of the 286 triangular membrane was shown in Figure S8a. 287 288 (4) Nanopore drilling 14 289 The nanopore was drilled by JEOL 2010F TEM. The 5 mm by 5 mm nanopore chip was placed in 290 a customized 5 mm TEM sample holder. The largest condenser aperture and spot size 1 were used 291 for maximum beam current output. After the alignment was finished, the imaging magnification 292 was increased to 1.5M (maximum). The beam spot was spread to 3 inch and held for 5-15 min for 293 stabilization. If the beam spot drifted, the focus needed to be re-adjusted under 250K magnification 294 and the stabilization needed to be re-monitored under 1.5M magnification. Once the beam got 295 stabilized, the 3-inch beam spot was reduced to ~7 mm and the condenser astigmatism was quickly 296 adjusted to make the spot as round as possible. At this stage, from the eyepiece, the material being 297 bombarded could be observed. Once it was clear, a successful drilling was identified. Under the 298 condition of 7 kV A2 and 30 nm membrane, it took 75-90 sec to drill through the membrane. 299 300 (5) Noise characterization, DNA preparation and DNA sensing 301 The TEM-drilled nanopore chip was treated with UV ozone cleaner (ProCleanerTM, BioForce 302 Nanosciences Inc.) for 15 min to improve the hydrophilicity of the surface and mounted into a 303 customized flow cell (Figure S13). Then a solution of 1:1 mixed ethanol and DI water was injected 304 into the flow cell to wet the chip for 30 min. The solution was subsequently flushed away by 305 injection of DI water. Next, 100 millimolar (mM) KCl was injected into the flow cell to test the 306 current-voltage (IV) curve using Axopatch 200B amplifier and Digidata 1440A digitizer 307 (Molecular Devices, LLC.), and then 1M KCl solution was injected to characterize the device 308 current. To do DNA sensing, the 1kbp as-ordered dsDNA (Thermo Scientific NoLimits, Thermo 309 Fisher Scientific Inc.) was diluted using 1M KCl to 5 ng/µL or the Poly(A)40 ssDNA (Standard 310 DNA oligonucleotides, Thermo Fisher Scientific Inc.) was diluted using 1M KCl to 50nM, and 311 stirred using a vortex mixer. Finally, the DNA solution was injected into the flow cell to collect 15 312 DNA signals under 10 kHz and 100 kHz low-pass filter at 50, 100 and 150 mV using Axopatch 313 200B amplifier and Digidata 1440A digitizer (Molecular Devices, LLC.). The flow cell was kept 314 in a customized Faraday cage on an anti-vibration table (Nexus Breadboard, Thor labs) to isolate 315 the environment noise during measurement. 316 317 (6) DNA signal collection and analysis 318 After the injection of the DNA solution, once the external voltage was applied, DNA signal could 319 be observed from the Clampex software. The DNA signals were recorded for sufficient time at 320 each voltage (50, 100, 150 mV) and each frequency (10 and 100 kHz) to ensure a relatively large 321 data set for analysis. The collected DNA signals were analyzed by OpenNanopore program 322 Firstly we edited a MATLAB program to convert all the .abf files to .mat files in a batch. Then 323 these .mat files were imported to OpenNanopore program to generate the dwelling time and 324 blockade current amplitude data of each DNA signal for subsequent analysis. 37 . 16 325 Acknowledgments 326 This work is partially supported by the Arizona State University (ASU) startup funds to Prof. 327 Chao Wang and National Science Foundation under award no. 1711412, 1809997, 1838443 and 328 1847324. We thank Prof. Amit Meller at Technion - Israel Institute of Technology, Dr. Yann 329 Astier and Dr. Juraj Topolancik from Roche Sequencing Solutions, Dr. Stuart Lindsay at ASU, 330 and Dr. Pei Pang (currently with Roswell Biotechnologies) at ASU for fruitful discussions. 17 331 References 332 1. a nanopore: a tutorial. Chemical Society Reviews 2018, 47(23): 8512-8524. 333 334 2. Li W, Bell NA, Hernández-Ainsa S, Thacker VV, Thackray AM, Bujdoso R, et al. Single protein molecule detection by glass nanopores. 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Fast and automatic processing 426 of multi-level events in nanopore translocation experiments. Nanoscale 2012, 4(16): 427 4916-4924. 22 428 429 Figure 1. Schematics showing the key steps for creating the membrane and the nanopore on a 430 sapphire substrate. (a) A 250 μm sapphire wafer is cleaned by solvents and RCA2. (b) A layer of 431 PECVD SiO2 is deposited on both sides of the sapphire wafer, followed by thermal annealing. (c) 432 A window is formed in the top SiO2 by photolithography and RIE. (d) The sapphire is etched 433 through in hot sulfuric acid and phosphoric acid, forming the suspended SiO2 membrane at the 434 bottom. (e) A thin layer of LPCVD SiN is deposited on the bottom SiO 2 membrane, and the 435 unintentionally deposited SiN in the cavity is etched by RIE to expose the SiO2 membrane in the 436 cavity (not shown). (f) The thin SiN membrane is formed by firstly selectively removing the SiO2 437 membrane in the cavity using hydrofluoric acid and then thinning the SiN using hot phosphoric 438 acid. (g) A nanopore is drilled by transmission electron microscope (TEM) on the SiN membrane. 439 One corner of the chip was hidden in schematic d-g to better show the central etching cavity. 23 440 441 Figure 2. The formation of the SiO2 supporting membrane after sapphire etching. (a) Side-view 442 schematic of the chip. L1 and L2 are the window size and the membrane size respectively. θ is the 443 effective facet angle after etching. (b) Top-view schematic of the chip. (c) An optical image of a 5 444 mm by 5 mm sapphire chip with intact SiO2 membrane. (d) Optical image showing both the 445 triangular window and the SiO2 membrane. (e) Optical image of a representative triangular SiO2 446 membrane (123 μm side length). (f) Quasi-linear relation between the membrane size (L2) and the 447 window size (L1). (g) Optical image of a representative small SiO2 membrane (5 μm). 24 448 449 Figure 3. Ionic current noise analysis of the sapphire nanopore and the Si nanopore chips. (a) A 450 schematic of the measured sapphire nanopore chip. (b) An optical image of the SiN membrane of 451 the sapphire nanopore chip and a TEM image of the drilled nanopore. (c) The ionic current noise 452 for the Si nanopore (black traces), the sapphire nanopore (red traces), and the open-headstage state 453 (green traces) under 10 kHz (left three traces) and 100 kHz (right traces) low-pass filter 454 respectively. The two chips were both measured under 50 mV voltage. The RMS ionic current 455 values are given for each measurement. (d) Power spectra of the current noise of the sapphire 456 nanopore and the Si nanopore versus frequency under 100 kHz low-pass filter. The two chips were 457 both measured under 50 mV voltage. 25 (a) Si ∆t (b) Si 100kHz ib Sapphire 0.3nA Sapphire 100kHz ∆I i0 300pA 100μs Sapphire 10kHz 5s (c) Sapphire, 50mV (d) (e) 458 459 Figure 4. Analysis of 1kbp dsDNA translocation events for the sapphire nanopore (2002 µm2 460 membrane area) and the Si nanopore (31 µm2 membrane area) under 100 kHz filter frequency. (a) 461 The current traces of the DNA translocation events of the Si nanopore and the sapphire nanopore 462 under different voltages (black: 50 mV, red: 100 mV, blue: 150 mV). (b) Representative DNA 463 events for the Si nanopore and the sapphire nanopore at different voltages (black: 50 mV, red: 100 464 mV, blue: 150 mV) and different recording bandwidth (top two rows: 100 kHz, bottom row: 10 465 kHz). ∆t: event dwelling time; i0: open-pore current baseline; ib: block-pore current level; ∆I: 466 blockade current amplitude. (c) Scatter plot of the fractional blockade current IB (=ib/i0) versus the 467 dwelling time ∆t of all the DNA events from the sapphire nanopore under 50 mV. Two distinct 468 populations are separated by the red dashed line as the translocation events (green oval) and the 469 collision events (pink oval). (d) The histograms of IB of the sapphire nanopore under 50 mV 470 displaying two distinct peaks corresponding to the translocation events (green bars) and the 471 collision events (pink bars). The solid and dash black lines indicate the fitting by Gaussian function. 472 (e) Histograms of ∆t of the segregated events based on two IB populations, fitted by exponential 26 473 function. The translocation events (top panel) has a longer tail (decay constant 16.19 µs) than the 474 collision events (lower panel, decay constant 8.45 µs). 27 (a) Sapphire (b) (c) Si 50 mV 150 mV 100 mV 150 mV (d) 50 mV (e) 100 mV (f) 475 476 Figure 5. Signal-to-noise ratio (SNR) comparison between the sapphire nanopore and the Si 477 nanopore under 100 kHz filter frequency. (a) Scatter plot of the fractional blockade current IB 478 (=ib/i0) versus the dwelling time ∆t of all the DNA events from the sapphire nanopore under 479 different bias voltages from 50 mV to 150 mV. (b) The histograms of IB of the sapphire nanopore. 480 Two distinct peaks are observed and fitted by Gaussian function, corresponding to the 481 translocation events (green bars) and the collision events (pink bars). (c) Scatter plot of the 482 fractional blockade current IB (=ib/i0) versus the dwelling time ∆t of all the DNA events from the 483 Si nanopore. (d) The histograms of IB of the Si nanopore. Two distinct peaks are observed for 100 484 mV and 150 mV biases and fitted by Gaussian function, corresponding to the translocation events 28 485 (green bars) and the collision events (pink bars). The signals at 50 mV bias displayed only one 486 obvious peak and not further segregated. (e-f) Scatter plot of 1-IB (=∆I/i0) versus the dwelling time 487 ∆t of all the DNA translocation events (collision events removed) from the sapphire nanopore (e) 488 and Si nanopore (f). The dashed lines at the bottom are the values of IRMS/i0, in which IRMS is the 489 root-mean-square noise at open-pore state. The short solid lines are the peak values of (1-IB) in the 490 Gaussian distribution of the translocation events in (b) and (d). The error bars of the distribution 491 are added at the left edge of each short solid line. The SNR for each bias voltage is determined by 492 the ratio between the values of the DNA signals, indicated by the short solid lines, and their 493 corresponding noises, represented by the dashed lines of the same color. The values of SNR are 494 also given in the figures. DNA data are represented by black, red and blue dots in figure a, c, e, 495 and f for the collecting bias voltages as 50 mV, 100 mV, and 150 mV. 29 496 497 Figure 6. Analysis of Poly(A)40 single-stranded (ss) DNA translocation events for the sapphire 498 nanopore under 100 kHz filter frequency. (a) The current trace of the DNA translocation events 499 under 100 kHz filter frequency. (b) Scatter plot of 1-IB (=∆I/i0) versus the dwelling time ∆t of all 500 the DNA translocation events (collision events removed). The dashed lines at the bottom are the 501 values of IRMS/i0, in which IRMS is the root-mean-square noise at open-pore state. The short solid 502 lines are the peak values of (1-IB) in the Gaussian distribution of the translocation events. The 503 error bars of the distribution are added at the left edge of each short solid line. The SNR is given 504 by the ratio of the DNA signal (short solid lines) and the noise (dashed lines) for each tested 505 voltage. (c) Representative DNA events under 100 kHz filter frequency. Here the signals are 506 indicated by red and blue for bias voltages at 100 mV and 150 mV, respectively. 30 507 31 508 509 510 511 512 513 514 515 516 517 518 Supplementary information for Sapphire Nanopores for Low-Noise DNA Sensing Pengkun Xia1,2,3, Jiawei Zuo1,2,3, Pravin Paudel1,2, Shinhyuk Choi1,2,3, Xiahui Chen1,2,3, Weisi Song4, JongOne Im4, 5, Chao Wang1,2,3* 1 School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA 2 Center for Photonic Innovation, Arizona State University, Tempe, AZ, USA 3 Biodesign Center for Molecular Design & Biomimetics, Arizona State University, Tempe, AZ, USA 4 Biodesign Center for Single Molecule Biophysics, Arizona State University, Tempe, AZ, USA 5 Curent Address: INanoBio Inc., Scottsdale, AZ, USA 32 519 Supplementary Note 1 The power spectral density (PSD) of a solid-state nanopore can be described as 1, 2, 3 520 𝑆 = 𝑎1 521 522 523 524 𝑎1 𝑓𝛽 1 + 𝑎2 + 𝑎3 𝑓 + 𝑎4 𝑓 2 𝑓𝛽 (1) where f is frequency and 𝑎1,2,3,4 are coefficients. 𝑆 consists of the low-frequency flicker noise (1< 𝛽 <2) 4, white thermal noise 𝑎2 , dielectric noise 5, 6 𝑎3 𝑓, and capacitive noise 7 𝑎4 𝑓 2 . The noise current at high frequencies (e.g. >10 kHz) is mainly contributed by the capacitive noise 𝑎4 𝑓 2 526 (Figure S1b). This noise is proportional to total input capacitance 𝐶𝑡𝑜𝑡𝑎𝑙 with a PSD growing with 527 input equivalent voltage thermal noise of the input amplifier 8. And in this high-frequency sensing 525 528 529 530 the square of frequency - 𝑆𝑎𝑚𝑝 = (2𝜋𝑓𝐶𝑡𝑜𝑡𝑎𝑙 𝑣𝑛 )2 , where 𝑣𝑛 is the voltage noise density of the regime, 𝐼𝑅𝑀𝑆 (𝐵) = 2𝜋 √3 𝐵 3/2 𝐶𝑡𝑜𝑡𝑎𝑙 𝑣𝑛 √𝑆(𝐵) 7, 9. The total input capacitance is estimated as 𝐶𝑡𝑜𝑡𝑎𝑙 = 𝐶𝑠𝑦𝑠 + 𝐶𝑐ℎ𝑖𝑝 7, in which 𝐶𝑠𝑦𝑠 is the capacitance from the measurement setup and 𝐶𝑐ℎ𝑖𝑝 is the nanopore chip capacitance. 𝐶𝑠𝑦𝑠 is 531 generally on the order of 10-20 pF and the optimized CMOS amplifier design can decrease it down 532 to less than 5pF 9, 10. Whereas, 𝐶𝑐ℎ𝑖𝑝 , which is composed of 𝐶𝑚 + 𝐶𝑠 , can be as large as hundreds 533 534 of pF or even a few nF. 𝐶𝑚 is the membrane capacitance, which becomes negligible for small membranes. However, 𝐶𝑠 (stray capacitance), which is expressed as 𝐶𝑆𝑖−𝐵1 || (𝐶𝑆𝑖−𝐵1 + 𝐶𝑆𝑖−𝐵3 ) 535 (Figure S1c) for first-order estimation, can be significant due to the significant amount of free 536 carriers in silicon (Si) substrate 9. 33 537 538 539 540 541 542 Supplementary Note 2 To estimate the relationship between the membrane and the mask dimensions, we assume 𝐿2 is parallel to 𝐿1 and the etching follows an effective facet angle 𝜃 (Figure S5c), which is between the exposed facets in the cavity and sapphire c-plane that can be empirically determined (Figure 2a). It can be easily determined that 𝐿1 = 𝐿2 + 2√3ℎ/ 𝑡𝑎𝑛 𝜃, where ℎ is the sapphire wafer thickness and 𝜃 is an effective facet angle between. 34 543 Table S1. The calculation of the Si nanopore capacitance in Figure S1c. Dielectric Capacitance Material constant type (ε) CSi-B1 (1) (1) Calculation Method Capacitance Silicon 1 nitride 𝐶 = 𝑆𝑖−𝐵1 6.5 (ε1) (2400µm/2)2×π- 23nm (t1) 1/𝐶1 + 1/𝐶2 (C1) and (#) and 99nm and 3.9 silicon 𝐶1 = 𝜀1 ∙ 𝜀0 ∙ 𝐴/𝑡1 (4.2×4.7𝜇𝑚)2 (ε2) (t2) oxide 𝐶2 = 𝜀2 ∙ 𝜀0 ∙ 𝐴/𝑡2 (C2) CSi-B2 +CSi-B3 Silicon oxide 3.9 ≈(2400µm/2) Cm Silicon nitride 6.5 (4.2×4.7𝜇𝑚)2 Ctotal 544 Thickness (t) Area (A) (##) 2×π (###) (2) 2nm 23nm 𝐶𝑆𝑖−𝐵2 + 𝐶𝑆𝑖−𝐵3 𝐴 = 𝜀 ∙ 𝜀0 ∙ 𝑡 𝐶𝑚 = 𝜀 ∙ 𝜀0 ∙ 𝐴 𝑡 𝐶𝑡𝑜𝑡𝑎𝑙 = 𝐶𝑚 + 𝐶𝑆𝑖−𝐵1|| (𝐶𝑆𝑖−𝐵2+ 𝐶𝑆𝑖−𝐵3 ) 1384pF 70106pF 0.049pF 1360pF 545 CSi-B1, CSi-B2+CSi-B3, Cm and Ctotal of the 4.2×4.7𝜇𝑚 (23 nm thick) membrane Si nanopore. 546 2400 𝜇m is the real o-ring opening diameter, which was measured by stamping an o-ring pattern 547 (#) on a piece of paper using some ink. 4.2×4.7𝜇𝑚 is the square membrane side length. (##) 2400 𝜇m 549 is the o-ring opening diameter. (###) 4.2×4.7𝜇𝑚 is the side length of the square membrane. (1) 𝜀0 is 550 side) has the same thickness with the oxide in the back cavity (2 nm). 548 the vacuum permittivity, 8.854 pF/m. (2) For this chip, the bottom surface oxide layer (at the cavity 35 551 Table S2. Comparison of different methods to make low-noise solid-state nanopore chips. Methods HF etching glass & SiN membrane transfer HF etching glass & SiN membrane transfer Two-step HF etching glass & Silicone painting Schematic Substrate/ membrane Glass/ Silicon nitride Glass/ Boron nitride Membrane Chip size/ capacitance thickness 25µm2/ 20nm Silicon/ Silicon nitride Manual painting and bonding & EBL Silicon/ Silicon nitride EBL Silicon/ Silicon nitride This work: Sapphire substrate Sapphire/ Silicon nitride 12.58pA 70pF @4.5nA, (measured) 10kHz 4.3pA @0nA, 0.0025µm2/ 5-10pF 10kHz; 2-3nm (measured) 12.8pA @0nA, 100kHz Glass/ 0.071µm2/ Graphene 0.34nm CMOS amplifier & EBL & Silicone painting RMS noise 0.551.25pF (calculated) NA Scalability and comments Not scalable. ■ Manual transfer of SiN needed to keep the membrane dimension uniform. Not scalable. ■ Same as above. ■ Additional FIB drilling step is required to make the tiny window for suspending h-BN. Not scalable. ■ Uniformity and controllability are unknown for twostep etching. ■ Manual painting. 7.2pA Not scalable. @10kHz; ■ Manual painting. 0.25µm2/ 6pF 12.9pA ■ Using EBL to 10-15nm (calculated) @100kHz pattern a small (Bias info: membrane is NA) expensive. Not scalable. 119■ Manual painting 100149pA 1.9-5.8pF and bonding. 1600µm2/ @1MHz (measured) ■ EBL for small sub 10nm (Bias info: membrane. NA) (expensive) 70-80pA Not scalable. 0.0625µm2/ @100kHz ■ EBL for small NA 6nm (Bias info: membrane. NA) (expensive) ■ 10kHz: 10pF 4.7pA Scalable. 2002µm2/ (measured)/ @50mV ■ Anisotropic 30nm 5.4pF ■ 100kHz: etching of sapphire (calculated) 17.7pA @50mV 36 552 Table S3. The calculation of the sapphire nanopore capacitance in Figure S1d. Dielectric Thickness Capacitance Material constant Area (A) type (t) (ε) Csub Cslope Cm Sapphire Sapphire Silicon nitride 9.3 9.3 6.5 (2400𝜇𝑚/2 )2×π(762𝜇𝑚/2)2 250𝜇m ×√3 L2 edge to L1 edge (**) (***) 553 554 555 556 557 250𝜇m (5𝜇𝑚/2)2× √3 or 2nm or (68𝜇𝑚/2)2× 30nm √3 Ctotal (*) (1) Calculation Method 𝐶𝑠𝑢𝑏 = 𝜀 ∙ 𝜀0 ∙ 𝐶𝑠𝑙𝑜𝑝𝑒 = 𝐿1 𝑒𝑑𝑔𝑒 ∫ 𝐿2 𝑒𝑑𝑔𝑒 𝐴 𝑡 𝜀 ∙ 𝜀0 ∙ 𝐶𝑚 = 𝜀 ∙ 𝜀0 ∙ Capacitance 1.4pF 𝐴 (𝑥) 𝑑𝑥 𝑡(𝑥) 𝐴 𝑡 𝐶𝑡𝑜𝑡𝑎𝑙 = 𝐶𝑠𝑢𝑏 + 𝐶𝑠𝑙𝑜𝑝𝑒 + 𝐶𝑚 0.2pF 0.3pF or 3.8pF 1.9pF or 5.4pF Csub, Cslope, Cm and Ctotal of the 5 𝜇𝑚 wide (2 nm thick) or 68 𝜇𝑚 wide (30 nm thick) membrane sapphire nanopore. (*) 2400 𝜇m is the o-ring opening diameter, and 762 𝜇m is L1. (**) Top-view area between L2 edge to L1 edge. (***) 5 𝜇m is the side length L2 of the triangular membrane. (1) 𝜀0 is the vacuum permittivity, 8.854 pF/m. 37 558 559 Figure S1. Motivation of designing low-noise solid-state nanopores in sapphire. (a) A schematic 560 of typical DNA signals during the DNA translocating through a solid-state nanopore. ΔI is the 561 blockade current amplitude, Δt is the dwelling time, and the pink ripples are the current noise. (b) 562 The current noise contribution on the solid-state nanopores at different frequencies. One key noise 563 contributor at high-frequency detection is the total input capacitance. (c) The equivalent circuit of 564 a silicon-substrate solid-state nanopore, showing the parasitic capacitance (CSi-B1, CSi-B2 and CSi- 565 B3) 566 sapphire-substrate solid-state nanopore. No parasitic capacitance is observed due to the insulating 567 property of the sapphire substrate. Instead, as a dielectric material, the capacitance from the thick 568 sapphire itself (Csub and Cslope) are very small. due to the existence of free carriers in the silicon substrate. (d) The equivalent circuit of a 38 569 570 Figure S2. Process development to achieve crack-free SiO2 mask for reliable sapphire etching. (a) 571 An optical image of a sapphire wafer with PECVD SiO2 window patterned after 1-hour sapphire 572 etching @400°C hot-plate temperature. Severe undercut etching was observed. (b) An optical 573 image of the sapphire wafer with the same PECVD SiO2 window after 2-hour sapphire etching 574 @450°C hot-plate temperature, with added RCA2 cleaning and thermal annealing prior to etching. 575 No undercut etching was observed. 39 4° 6° 8° 10° 12° 14° 16° 18° 20° 22° 24° 26° 28° 30° 32° 34° 36° 38° 40° 42° 44° 46° 48° 50° 52° 54° 56° 58° (b) Membrane area / µm2 (a) 2° 104 103 102 α 0 10 20 30 40 50 60 Angle / ° 576 577 Figure S3. Experimental analysis of the dependence of membrane shape and size (side length L2) 578 control on the alignment angle between the triangular-shaped etching windows (side length L1) 579 and the A-plane sapphire flat. (a) Optical images of the membranes. The alignment angles (α, 580 indicated in figure b) between the etching window and the A-plane sapphire flat is indicated on 581 the images. (b) The plot of the membrane area versus the alignment angle α. Here the etching 582 window size length L2 was fixed as about 767 µm. the sapphire was etched about 232 µm. 40 583 584 Figure S4. Optical images of the membranes formed on sapphire by square-shaped etching 585 windows (L1) with different alignment angles. Here the window side length L2 was fixed as 800 586 µm. The numbers on each image indicate the alignment angles α. 41 128µm (b) 51µm 70µm 103µm 115µm 132µm 143µm 154µm 180µm SiO2 membrane L1 (c) SiO2 membrane L1 L2 SiO2 mask SiO2 mask (d) Membrane size L2 / µm (a) 5µm 123µm 200 160 θ=60° 55° 50° 120 80 40 0 500 587 600 700 800 900 Window size L1 / µm 588 Figure S5. Demonstration of tuning membrane dimension by engineering the etching mask 589 dimensions. (a) Optical images of the membranes (side length L1) with different etching window 590 sizes (side length L2). The numbers on the images indicate the value of L2. The magnification of 591 the objective lens is 100x for the 5 µm triangle and 10x for others. (b) Top view of a real sapphire 592 chip after the sapphire is etched through. There is an offset angle between L1 and L2. (c) The 593 membrane L2 is assumed to be paralleled to L1 to estimate the effective facet angle θ by applying 594 the equation 𝐿1 = 𝐿2 + 2√3ℎ/ 𝑡𝑎𝑛 𝜃. (d) Plot of L2–L1 relationship, fitted by a model assuming 595 the sapphire etching follows an effective facet angle θ, which is the angle marked in Figure 2a. 596 The fitting indicates the effective facet angle is around 50° while α=0°. 42 597 598 Figure S6. Facets of the sapphire in the cavity after sapphire etching. (a) The SEM image of the 599 top view of the sapphire cavity. (b) The three-fold symmetric n-r-n plane system, which caused 600 the three-fold symmetric etching facets of sapphire. (c) The SEM image of the cross section of 601 the sapphire cavity. 43 602 603 Figure S7. Comparison of thinning down the SiN membrane by reactive-ion etching (RIE) or 604 phosphoric acid wet etching. (a) Optical image of a SiN membrane after RIE dry etching (thickness 605 after etching: 136 nm). RIE recipe: PlasmaTherm 790 RIE Fluorine (tool), 30 W bias, 100 mTorr, 606 CF4 50 sccm, O2 2 sccm, etching rate: 18 nm/min (b) Optical image of a SiN membrane after hot 607 phosphoric wet etching (thickness after etching: 30 nm). (c) current-voltage (IV) characteristic of 608 the membrane in figure a in 1M KCl solution. (d) IV characteristic of the membrane in figure b in 609 1M KCl solution. 44 610 611 Figure S8. The thickness characterization of the membrane thickness using Filmetrics F40. (a) The 612 fitting curve (red) of the measured reflectance spectrum of the SiN membrane (blue). (b) The 613 uniformity characterization of the membrane thickness. The thickness variation of the left corner 614 may come from the bending of the membrane, since F40 measurement is based on the reflectance 615 of light. 45 616 617 Figure S9. The small-membrane Si nanopore chip for comparison. (a) The optical image of the 618 SiN membrane (4.2 µm by 4.7 µm). (b) The schematic of the structure of this nanopore chip. (c) 619 The nanopore drilled by TEM on the SiN membrane. (d) The IV curve tested by 100 mM KCl 620 solution, showing good linearity. 46 621 622 Figure S10. Representative 1kbp dsDNA translocation events for the sapphire nanopore and the Si 623 nanopore under 10kHz filter bandwidth. (a) The current trace of the DNA translocation events of 624 the Si nanopore under different voltages (black: 50 mV, red: 100 mV, blue: 150 mV). (b) Scatter 625 plot of the fractional blockade current IB (=ib/i0) versus the dwelling time ∆t of all the DNA events 626 from the Si nanopore under different voltages (black: 50 mV, red: 100 mV, blue: 150 mV). (c) The 627 current trace of the DNA translocation events of the sapphire nanopore under different voltages 628 (black: 50 mV, red: 100 mV, blue: 150 mV). (d) Scatter plot of the fractional blockade current IB 629 (=ib/i0) versus the dwelling time ∆t of all the DNA events from the sapphire nanopore under 630 different voltages (black: 50 mV, red: 100 mV, blue: 150 mV). 47 631 632 Figure S11. The histograms of IB from the analysis of Poly(A)40 single-stranded (ss) DNA by the 633 sapphire nanopore under 100 mV (a) and 150 mV (b). Two distinct peaks are observed and fitted 634 by Gaussian function, corresponding to the translocation events (green bars) and the collision 635 events (pink bars). 48 636 637 Figure S12. Optical graphs of: (a) A sapphire wafer with SiO2 mask patterned right before the 638 sapphire etching. (b) The glassware setup used for sapphire etching: The glass vessel and its lid 639 are clamped together by a stainless-steel clamp. On the top, a water condenser is used to condense 640 and recirculate the evaporated acid. The setup is put on a hot plate. 49 641 642 Figure S13. The experimental setup for the noise characterization and DNA sensing of the 643 nanopore chip. (a) A photo of the flow cell used for providing electrolyte ambient for the nanopore 644 chip. It is composed of two acrylic pieces drilled with fluidic channels. The two pieces are mounted 645 together by four screws. (b) A schematic of the flow cell showing the injection of the electrolyte 646 solution (blue path) and the mounted nanopore chip. (c) The Faraday cage used to contain the flow 647 cell to isolate the environment noise and the Axopatch 200B amplifier with the Digidata 1440A 648 digitizer. 50 649 Supplementary References 650 1. reduction in solid-state nanopores. Nanotechnology 2007, 18(30): 305505. 651 652 Tabard-Cossa V, Trivedi D, Wiggin M, Jetha NN, Marziali A. Noise analysis and 2. Dimitrov V, Mirsaidov U, Wang D, Sorsch T, Mansfield W, Miner J, et al. Nanopores in 653 solid-state membranes engineered for single molecule detection. Nanotechnology 2010, 654 21(6): 065502. 655 3. of solid-state nanopores at low frequencies. ACS sensors 2017, 2(2): 300-307. 656 657 4. 5. 6. Levis RA, Rae JL. The use of quartz patch pipettes for low noise single channel recording. Biophysical journal 1993, 65(4): 1666-1677. 662 663 Uram JD, Ke K, Mayer M. Noise and bandwidth of current recordings from submicrometer pores and nanopores. Acs Nano 2008, 2(5): 857-872. 660 661 Siwy Z, Fuliński A. Origin of 1/f α noise in membrane channel currents. Physical Review Letters 2002, 89(15): 158101. 658 659 Wen C, Zeng S, Arstila K, Sajavaara T, Zhu Y, Zhang Z, et al. Generalized noise study 7. Balan A, Machielse B, Niedzwiecki D, Lin J, Ong P, Engelke R, et al. Improving signal- 664 to-noise performance for DNA translocation in solid-state nanopores at MHz bandwidths. 665 Nano letters 2014, 14(12): 7215-7220. 666 8. Ferrari G, Gozzini F, Molari A, Sampietro M. Transimpedance amplifier for high 667 sensitivity current measurements on nanodevices. IEEE Journal of Solid-State Circuits 668 2009, 44(5): 1609-1616. 669 9. Rosenstein JK, Wanunu M, Merchant CA, Drndic M, Shepard KL. Integrated nanopore 670 sensing platform with sub-microsecond temporal resolution. Nature methods 2012, 9(5): 671 487. 51 672 10. Shekar S, Niedzwiecki DJ, Chien C-C, Ong P, Fleischer DA, Lin J, et al. Measurement of 673 DNA translocation dynamics in a solid-state nanopore at 100 ns temporal resolution. 674 Nano letters 2016, 16(7): 4483-4489. 52