Fundamentals of Computer Architecture and Design

5 Memory Circuits and Systems Basic serial and parallel bus structures and different forms of data transfer between a bus master and a slave were explained in Chapter 4. Regardless of the bus architecture, the bus master is defined as the logic block that initiates the data transfer, and the slave is defined as the device that exchanges data with the master on demand. Both devices, however, may include a buffer memory. The master may have an internal memory that stores user programs or data, and the slave may have a large capacity system memory or a small buffer memory. Depending on the read and write speed, capacity and permanence of data, system memories and peripheral buffers can be categorized into three different forms. If fast read and write times are desired, Static Random Access Memory (SRAM) is used despite its relatively large cell size compared to other types of memory. SRAM is commonly used to store small temporary data, and it is typically connected to a high speed parallel bus in a system. If large amounts of storage are required, but slow read and write speed can be tolerated, then Dynamic Random Access Memory (DRAM) should be the main memory type to be used. DRAMs are still connected to the high speed parallel bus, but typically operate with large bursts of data. A typical DRAM cell is much smaller than an SRAM cell with significantly lower power consumption. The main drawbacks of DRAM are high data read and write latencies, the complexity of memory control and management of data. The permanence of data yet calls for a third memory type whose cell type consists of a double-gated Metal-Oxide-Semiconductor (MOS) transistor. Data is permanently stored in the floating gate of the device until it is overwritten. Electrically-Erasable-ProgrammableRead-Only-Memory (E2PROM) or Flash memory fit into this type of device category. The advantage of this memory type is that it keeps the stored data even after the system power is turned off. However, this memory is the slowest compared to all other memory types, and it is subject to a limited number of read and write cycles. Its optimal usage is, therefore, to store permanent data for Built-In-Operating-Systems (BIOS), especially in hand-held devices where power consumption is critical. A typical computing system can contain one or all three types of memories depending on the usage and application software. © Springer International Publishing Switzerland 2017 A. Bindal, Fundamentals of Computer Architecture and Design, DOI 10.1007/978-3-319-25811-9_5 169 170 5 Memory Circuits and Systems The basic functionality of SDRAM, E2PROM and Flash memory blocks in this chapter is inspired from Toshiba memory datasheets [1–6]. The more recent serial Flash memory with SPI interface in this chapter is based on an Atmel Flash memory datasheet [7]. In each case, the functionality of the memory block has been substantially simplified (and modified) compared to the original datasheet in order to increase reader’s comprehension of the subject matter. The purpose here is to show how each memory type operates in a system, covering only the basic modes of operation to train the reader rather than going into the details of the actual datasheets. The address, data and control timing constraints for each memory have also been simplified compared to the datasheets. This allows us to design the bus interface for each memory type with ease. For the sake of simplicity, we avoided duplicating the port names, exact timing requirements and functionality details that can be found in the actual datasheets. After reading this chapter, interested readers are encouraged to study the referenced datasheets prior to carrying out their design tasks. 5.1 Static Random Access Memory Static Random Access Memory (SRAM) is one of the most fundamental memory blocks in digital design. Among all different types of memory, SRAM ranks the fastest; however, its large memory cell size limits its usage for a variety of applications. A typical SRAM architecture shown in Fig. 5.1 is composed of four different blocks: the SRAM core, the address decoder, the sense amplifier and the internal SRAM controller. The memory core retains all immediate data. The sense amplifier amplifies the cell voltage to full logic levels during read. The address decoder generates all 2N Word Lines (WL) from an N-bit wide address. Finally, the controller generates self-timed pulses required during a read or write cycle. Each SRAM cell is composed of two back-to-back inverters like the ones used in a latch, and two N-channel Metal Oxide Semiconductor (NMOS) pass-gate transistors to isolate the existing data in the cell or to allow new data into the cell as shown in Fig. 5.2. When data needs to be written to a cell, WL = 1 turns on both NMOS transistors, allowing the true and complementary bits of data to be simultaneously written from the Bit and Bitbar inputs. Suppose the node A is initially at logic 0, and the node B at logic 1 but WL = 0. The logic level at WL turns off both NMOS transistors, and the latch becomes completely isolated from its surroundings. As a result, logic 0 level is contained in the cell. But, if WL = 1, Bit = 1 and Bitbar = 0, this time the logic level at WL turn on both NMOS transistors, and the values at the Bit and the Bitbar nodes overwrite the existing logic levels at the nodes A and B, thereby changing the stored bit in the cell from logic 0 to logic 1. Similarly, if the data needs to be read from the cell, both NMOS transistors are turned on by WL = 1, and the small differential potential developed between the Bit and the Bitbar outputs are amplified by a sense amplifier to reach full logic levels at the SRAM output. 5.1 Static Random Access Memory 171 31 0 255 8 AddrIn[7:0] Address Decoder SRAM Core 256 WL [255:0] Precharge EnWL 32 WritePulse DIn[31:0] 0 32 EN WE Sense Amplifier Internal SRAM Controller ReadPulse DOut[31:0] Fig. 5.1 A typical SRAM architecture with eight-bit address and 32-bit data WL Bit A B Bitbar Fig. 5.2 SRAM memory cell The data write sequence starts with EN (Enable) = 1 and Write Enable (WE) = 1. This combination precharges the Bit and the Bitbar nodes in the SRAM core to a preset voltage and prepares the memory for a write. When the precharge cycle is complete, the controller enables the address decoder by EnWL = 1 as shown in Fig. 5.1. The decoder activates a single WL input out of 256 WLs according to the value provided at AddrIn[7:0]. Within the 172 5 Memory Circuits and Systems same time period, the controller also produces WritePulse = 1, which allows the valid data at DIn[31:0] to be written into the specified address. Reading data from the SRAM core is performed by EN = 1 and WE = 0. Similar to the write operation, the controller first precharges the SRAM core prior to reading data, and then turns on the address decoder. According to the address value at the AddrIn port, the WL input to a specific row is activated, and the data is read from each cell to the corresponding Bit and Bitbar nodes at this row. The sense amplifier amplifies the cell voltage to full logic levels and delivers the data to the DOut port. The SRAM I/O timing can be synchronized with clock as shown in Figs. 5.3 and 5.4. In Fig. 5.3, when EN and WE inputs are raised to logic 1, SRAM goes into the write mode, and the valid data is written to a specified address at the next positive clock edge. In Fig. 5.4, when EN = 1 and WE = 0, SRAM is enabled and operates in the read mode. The core delivers the valid data sometime after the next positive edge of the clock. clock WE EN Addr[7:0] DIn[31:0] Valid Address Valid Data Fig. 5.3 SRAM I/O timing for write clock WE EN Addr[7:0] DOut[31:0] Fig. 5.4 SRAM I/O timing for read Valid Address Valid Data 5.1 Static Random Access Memory 173 One of the important tasks to integrate an SRAM module to an existing system is to design its bus interface. Figure 5.5 shows the block diagram of such an implementation. The bus interface basically translates all bus control signals to SRAM control signals (and vice versa), but it seldom makes any modifications on address or data. In the unidirectional bus protocol described in Chapter 4, SRAM is considered to be a bus slave that exchanges data with the bus master on the basis of a Ready signal. As also mentioned in Chapter 4, a bus master has four control signals to indicate the data transfer. The Status signal indicates if the bus master is sending the first data packet (START) or is in the process of sending remaining data packets (CONT). The bus master may also send IDLE or BUSY signals to indicate if it has finished the current data transfer or busy with an internal task, respectively. The Write signal specifies if the bus master intends to write data to a slave or read from a slave. The WData[31:0] RData[31:0] 32 32 DOut[31:0] DIn[31:0] Ready Bus Interface WE SRAM Burst Status Write BIWEn EN BIREn AddrIn[7:0] 8 4 D Q W Addr[31:28] Addr[7:0] 8 32 Addr[31:0] Fig. 5.5 SRAM bus interface block diagram R clock 174 5 Memory Circuits and Systems Burst signal designates the number of data packets in the transaction, and the Size signal defines the width of the data. The timing diagram in Fig. 5.6 shows how to write four data packets, W1 to W4, to four consecutive SRAM addresses, A1 to A4, as an example to build the bus interface in Fig. 5.5. To initiate a write sequence, the bus master issues a valid address, Status = START and Write = 1 in the first clock cycle of this timing diagram, and enables the bus interface for a Idle Standby Write Write Write Last Write Idle clock Write Burst Status 4 START Addr[31:28] CONT CONT CONT IDLE A2 A3 A4 A4 W1 W2 W3 W4 SRAM Space BIWEn Addr[7:0] WData[31:0] A1 RData[31:0] EN WE BM writes BM writes BM writes BM writes AddrIn[7:0] A1 A2 A3 A4 DIn[31:0] W1 W2 W3 W4 DOut[31:0] Ready Fig. 5.6 SRAM bus interface timing diagram for write W4 5.1 Static Random Access Memory 175 write by producing an active-high Bus Interface Write Enable (BIWEn) signal. Upon receiving the BIWEn = 1, the bus interface produces Ready = 1 in the next cycle, and prompts the bus master to change the address and control signals in the third cycle. As the bus master changes its address from A1 to A2, it also sends its first data packet, W1, according to the unidirectional bus protocol explained in Chapter 4. However, in order to write data into an SRAM address, a valid data must be available within the same cycle as the valid address as shown in Fig. 5.3. Therefore, a set of eight flip-flops are added to the write path prior to the AddrIn port in Fig. 5.5 so that the address, A1, is delayed for one clock cycle, and aligned with the current data, W1. The bus interface also produces EN = WE = 1 in the third cycle so that W1 is written to A1 at the positive edge of the fourth clock cycle. The next write is accomplished in the same way: the SRAM address is delayed for one cycle in order to write W2 into A2 at the positive edge of the fifth cycle. In the sixth cycle, the bus interface keeps EN = WE = 1 to be able to write W3 to A3, but lowers the Ready signal to logic 0 so that the bus master stops incrementing the slave address and suspends the controls in the next cycle. In the seventh and final write cycle, the bus interface lowers both EN and WE to logic 0 but allows the last data, W4, to be written to A4 at the positive edge of the clock. The bus interface state diagram for write in Fig. 5.7 is developed as a result of the timing diagram in Fig. 5.6. The first state, Idle state, is the result of the bus interface waiting to receive BIWEn = 1 from the bus master, which corresponds to the first clock cycle of the timing diagram in Fig. 5.6. The next state that follows the Idle state is the Standby state where the bus interface generates Ready = 1. This state is one clock cycle long and represents the second clock cycle in the timing diagram. The Write state is the state during which the actual write sequence takes place: EN and WE are kept at logic 1 as long as the number of write addresses issued by the bus master is less than Burst length. This state corresponds to the third, fourth and fifth clock periods in the timing diagram. When the number of write addresses reaches the value of the Burst length, the bus interface goes to the Last Write stage and Ready signal becomes logic 0. The bus master writes the final data packet to the last SRAM address at the positive edge of the seventh clock cycle before it enters the Idle state. In order to initiate a read sequence, the bus master issues a valid SRAM address, Status = START and Write = 0 signals in the first clock cycle of Fig. 5.8. This combination produces an active-high Bus Interface Read Enable, BIREn = 1, which is interpreted as the bus master intending to read data from an SRAM address. Consequently, the bus interface generates EN = 1, WE = 0, Ready = 1 in the second cycle. This fetches the first data, R1, from the SRAM address, B1, in the third cycle. The read transactions in the fourth and fifth cycles are identical to the third, and the bus master reads R2 and R3 from the addresses, B2 and B3, respectively. In the sixth cycle, the bus interface retains Ready = 1 so that the bus master can still read the last data, R4, from the address, B4. 176 5 Memory Circuits and Systems BIWEn = 0 Ready = 0 EN = 0 WE = 0 Idle BIWEn = 1 Ready = 1 EN = 0 WE = 0 Standby Ready = 1 EN = 1 WE = 1 Write Write = 1 Status = CONT or BUSY Burst < Burst length Write = 1 Status = CONT Burst = Burst length Ready = 0 EN = 1 WE = 1 (BM dispatches the last data) Last Write Status = IDLE Status = BUSY Fig. 5.7 SRAM bus interface for write As in the write case, the read bus interface in Fig. 5.9 is also a direct consequence of the timing diagram in Fig. 5.8. The Idle state corresponds to the first clock cycle of the timing diagram in Fig. 5.8. As soon as BIREn = 1 is generated, the bus interface transitions to the Standby state where it produces EN = 1, WE = 0 and Ready = 1. The interface enters the Read state in the third cycle and produces the same outputs as before so that the bus master can read its first data, R1, and sends a new address in the next cycle. The interface stays in the Read state until the number of read addresses issued by the bus master is less than the Burst length. The Read state covers from the third to the fifth cycle in the timing diagram in Fig. 5.8. After the number of read addresses reaches the Burst length, the bus interface 5.1 Static Random Access Memory 177 Idle Standby Read Read Read Last Read Idle clock Write Burst 4 Status START Addr[31:28] CONT CONT CONT IDLE B2 B3 B4 B4 R1 R2 R3 R4 B2 B3 B4 R1 R2 R3 SRAM Space BIREn Addr[7:0] B1 WData[31:0] RData[31:0] EN WE AddrIn[7:0] B1 DIn[31:0] DOut[31:0] Ready BM reads BM reads BM reads R4 BM reads Fig. 5.8 SRAM bus interface timing diagram for read transitions to the Last Read state in cycle six where it continues to generate Ready = 1. This is done so that the bus master is able to read the last data as mentioned earlier. The interface unconditionally goes back to the Idle state in the following cycle. 178 5 Memory Circuits and Systems BIREn = 0 Ready = 0 EN = 0 WE = 0 Idle BIREn = 1 Ready = 1 EN = 1 WE = 0 Standby Ready = 1 EN = 1 WE = 0 Read Write = 0 Status = CONT or BUSY Burst < Burst length Write = 0 Status = CONT Burst = Burst length Ready = 1 EN = 0 WE = X Last Read Status = IDLE Status = BUSY Fig. 5.9 SRAM bus interface for read Increasing SRAM capacity necessitates employing extra address bits. In the example shown in Fig. 5.10, the SRAM capacity is increased from 32x16 bits to 32x64 bits by appending two extra address bits, Addr[5:4], which serves to access one of the four SRAM blocks. In this figure, even though Addr[3:0] points to the same address location for all four 32x16 SRAM blocks, Addr[5:4] in conjunction with EN enables only one of the four blocks. Furthermore, the data read from the selected block is routed through the 4-1 MUX using Addr[5:4] inputs. Addr[5:4] = 00 selects the contents of DOut0 port and routes the data through port 0 of the 4-1 MUX to Out[31:0]. Similarly, Addr[5:4] = 01, 10 and 11 select ports 1, 2 and 3 of the 4-1 MUX, and route data from DOut1, DOut2 and DOut3 ports to Out[31:0], respectively. 5.2 Synchronous Dynamic Random Access Memory 179 In[31:0] 32 Addr[3:0] 4 4 DIn2 BLOCK 3 DIn0 BLOCK 1 4 BLOCK 0 WE WE WE WE En3 En2 En1 En0 Addr[5] Addr[4] 3 2 1 EN Addr[4] Addr[5] Addr[5] DOut0 Addr[4] EN DOut1 Addr[4] EN EN DOut2 Addr[4] DOut3 Addr[5] 4 DIn1 BLOCK 2 Addr[5] DIn3 Addr[3:0] Addr[3:0] Addr[3:0] 0 32 Out[31:0] Fig. 5.10 Increasing SRAM address space 5.2 Synchronous Dynamic Random Access Memory Synchronous Dynamic Random Access Memory (SDRAM) is a variation of the older DRAM, and it constitutes the main memory of almost every computing system. Even though its capacity can be many orders of magnitude higher than SRAM, it lacks speed. Therefore, its usage is limited to storing large blocks of data when speed is not important. An SDRAM module is composed of four blocks. The memory core is where data is stored. The row and column decoders locate the data. The sense amplifier amplifies the cell voltage during read. The controller manages all the read and write sequences. The block diagram in Fig. 5.11 shows a typical 32-bit SDRAM architecture composed of four memory cores, called banks, accessible by a single bidirectional input/output port. Prior to operating the memory, the main internal functions, such as addressing mode, data latency and burst length, must be stored in the Address Mode Register. Once programmed, the active-low Row Address Strobe, RAS, Column Address Strobe, CAS, and Write Enable, WE, signals determine the functionality of the memory as shown in Table 5.1. The data from a selected bank can be masked by the Read/Write logic block at the DInOut port so that only part of the data can be fetched from the memory. This unit also serves blocking parts of the 32-bit data to be written to a bank. 180 5 CS CS BS[1:0] = 3 Column Address Stobe (CAS) R O W D E C O D E COLUMN DECODE 0 31 R O W BANK 3 0 R O W BANK 2 COLUMN DECODE RAS 10 RowAddr[9:0] BANK 0 D E C O D E SENSE AMP SENSE AMP WE RAS ColAddr[9:0] 0 31 R O W BANK 1 D E C O D E 10 COLUMN DECODE CAS 0 31 SENSE AMP WE BS[1:0] = 0 BS[1:0] = 1 CAS 31 D E C O D E SENSE AMP Row Address Stobe (RAS) COLUMN DECODE Chip Select (CS) CS BS[1:0] = 2 CAS Memory Circuits and Systems WE RAS Write Enable (WE) 32 READ/WRITE LOGIC Mask[3:0] 4 Address Mode Register 32 DInOut[31:0] Fig. 5.11 Typical SDRAM architecture Table 5.1 SDRAM modes of operation CS RAS CAS WE OPERATION 0 0 0 0 Program Addr. Mode Register 0 0 0 1 Self Refresh 0 0 1 0 Precharge a Bank with BS[1:0] 0 0 1 1 Activate a Bank with BS[1:0] 0 1 0 0 Write into a Bank with BS[1:0] 0 1 0 1 Read from a Bank with BS[1:0] 0 1 1 0 Burst Stop 0 1 1 1 Reserved 1 X X X SDRAM Deselect The SDRAM cell is a simple device composed of an NMOS transistor to control the data-flow in and out of the cell and a capacitor to store data as shown in Fig. 5.12. When new data needs to be written into the cell, the NMOS transistor is turned on by Control = 1, and the data at the DIn/Out terminal overwrites the old data at the Cell node. Reading data from the cell, on the other hand, requires amplification of the cell voltage, thus activation of the 5.2 Synchronous Dynamic Random Access Memory 181 sense amplifier when the NMOS transistor is turned on. When data needs to be preserved, the NMOS transistor is simply turned off by Control = 0. However, the charge on the cell capacitor slowly leaks through its insulator, resulting in a reduced cell voltage. Thus, an automatic or manual cell refresh cycle becomes mandatory during SDRAM operation to preserve the bit value in the cell. Control Cell DIn/Out C Fig. 5.12 SDRAM memory cell The first row of the truth table in Table 5.1 indicates how to program the internal Address Mode Register. At the positive edge of the clock, CS, RAS, CAS and WE signals are pulled low to logic 0 to program the Address Mode Register as shown in Fig. 5.13. In the program, the address bits, A[2:0], define the data burst length as shown in Table 5.2. Burst length can range from one word of data to a full page, which is equal to the contents of the entire bank. The address bit, A[3], defines how the SDRAM address is incremented for each data packet. In sequential addressing mode, the starting address is incremented by one while the carry bit is eliminated according to the size of the burst length. In linear addressing mode, the address is incremented without eliminating the carry bit. The address bits, A[5:4], determine the data latency when reading takes place from the memory. Latency can range from two to five clock cycles depending on the need. clock CS RAS CAS WE A[2:0] BURST LENGTH A[3] ADDRESS MODE A[5:4] LATENCY Fig. 5.13 Timing diagram for programming the address mode register 182 5 Memory Circuits and Systems Table 5.2 Truth tables for programming the address mode register A[2] A[1] A[0] Burst Length A[3] Addressing Mode 0 Sequential 1 Linear 0 0 0 1 Word 0 0 1 2 Words 0 1 0 4 Words 0 1 1 8 Words 1 0 0 16 Words 0 0 2 1 0 1 32 Words 0 1 3 1 1 0 64 Words 1 0 4 1 1 1 Full Page 1 1 5 A[5] A[4] Latency The example in Table 5.3 shows the elimination of the carry bit in sequential addressing mode for burst lengths of 2, 4 and 8. In this example, if the starting address is 13 and the burst length is two words, the carry bit from the column A[0] is eliminated, resulting the next address to be 12. In the same example, if the burst length is increased to four, this time the carry bit from the column A[1] is eliminated, and the address values following the starting address 13 become 14, 15 and 12. If the burst length becomes eight, the carry bit from the column A[2] is eliminated, and the address values of 14, 15, 8, 9, 10, 11 and 12 follow the initial address 13. Sequential addressing confines reading or writing of data within a predefined, circulatory memory space, convenient for specific software applications. The linear addressing mode is a simplified version of the interleave addressing in various SDRAMs, and increments the SDRAM address linearly without eliminating the carry bit as shown in Table 5.4. In this example, if the starting address is 13 and the burst length is two, the next address will be 14. If the burst length is increased to four, the next three addresses following 13 will be 14, 15 and 16. In contrast to the sequential addressing mode, the linear addressing increments SDRAM address one bit at a time, not confining the data in a circulatory address space. The second row of the operational truth table in Table 5.1 shows how to initiate a self refresh cycle as shown in Fig. 5.14. In self refresh, SDRAM automatically replenishes node voltage values at each cell because the charge across the cell capacitor leaks through its dielectric layer over time. The time duration between refresh cycles depends on the technology used, the quality of the oxide growth and the thickness of the dielectric used between capacitor plates. 5.2 Synchronous Dynamic Random Access Memory 183 Table 5.3 SDRAM sequential mode addressing for burst lengths of 2, 4 and 8 Starting Address = 13, Burst Length = 2, Mode = Sequential A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] 0 0 0 0 0 0 1 1 0 1 +1 = 13 0 0 0 0 0 0 1 1 0 0 = 12 delete the carry bit Starting Address = 13, Burst Length = 4, Mode = Sequential A[9] A[8] 0 0 A[7] A[6] 0 0 A[5] 0 A[4] A[3] 0 1 A[2] A[1] A[0] 1 0 1 = 13 +1 0 = 14 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 +1 = 15 0 0 0 0 0 0 1 1 0 0 = 12 +1 delete the carry bit Starting Address = 13, Burst Length = 8, Mode = Sequential A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] 0 0 0 0 0 0 1 1 0 1 = 13 +1 0 0 0 0 0 0 1 1 1 0 = 14 +1 0 0 0 0 0 0 1 1 1 1 = 15 +1 0 0 0 0 0 0 1 0 0 delete the carry bit 0 = 8 +1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 = 9 +1 0 = 10 +1 0 0 0 0 0 0 1 0 1 1 = 11 +1 0 0 0 0 0 0 1 1 0 0 = 12 184 5 Memory Circuits and Systems Table 5.4 SDRAM linear addressing mode for burst lengths of 2 and 4 Starting Address = 13, Burst Length = 2, Mode = Linear A[9] A[8] A[7] A[6] A[5] 0 0 0 0 0 0 0 0 0 0 A[4] A[3] A[2] A[1] A[0] 0 1 1 0 1 = 13 0 1 1 1 0 = 14 Starting Address = 13, Burst Length = 4, Mode = Linear A[9] A[8] A[7] A[6] A[5] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A[4] A[3] A[2] A[1] A[0] 0 1 1 0 1 = 13 0 0 1 1 1 0 = 14 0 0 0 1 1 1 1 = 15 0 0 1 0 0 0 0 = 16 clock CS RAS CAS WE BANK0 IDLE BANK1 IDLE BANK2 IDLE BANK3 IDLE Self Refresh Fig. 5.14 Timing diagram for self-refresh 5.2 Synchronous Dynamic Random Access Memory 185 Rows three to six in Table 5.1 define the read and write sequences in an SDRAM as shown in Fig. 5.15. In this figure, a read or a write sequence always starts with precharging all the rows and columns of the SDRAM core. This is followed by an activation cycle where the row address is generated. In the last cycle, the column address is generated, and the data is either written or read from the memory according to the control signals, CS, RAS, CAS and WE. PRECHARGE PRECHARGE WAIT WAIT ACTIVATE and supply Row Address WAIT WRITE and supply Column Address WAIT ACTIVATE and supply Row Address WAIT READ and supply Column Address WAIT Fig. 5.15 Write and read operation cycles Prior to a read or a write, all the rows and columns of a bank must be precharged to a certain voltage level for a period of one clock cycle as shown in Fig. 5.16. During precharge, CS, RAS and WE, must be lowered to logic 0, and CAS must be kept at logic 1 as shown in the third row of Table 5.1. The value of the precharge voltage can be anywhere between 0 V and the full supply voltage depending on the technology and the requirements of the circuit design. The activation cycle starts right after precharging a bank. The time interval between the precharge and activation cycles is called the precharge time period, tPRE, as shown in Fig. 5.16. The activation cycle is enabled by lowering CS and RAS to logic 0, but keeping CAS and WE at logic 1 as shown in the fourth row of Table 5.1. Following the activation cycle, the next precharge period must not start until after a certain time period has elapsed for the same bank. This time interval is called the RAS time period, tRAS, as shown in Fig. 5.16. 186 5 Memory Circuits and Systems clock CS RAS CAS WE BS[1] BS[0] tPRE Precharge BANK1 tRAS Activate BANK1 Precharge BANK1 Fig. 5.16 Bank precharge and activation cycles The fifth row of Table 5.1 shows how to write to a selected bank when CS = CAS = WE = 0 and RAS = 1. The actual write takes place in the last phase of the write sequence in Fig. 5.15 following the precharge and activation cycles. To illustrate the write sequence in detail, an example illustrating a single write burst is given in Fig. 5.17. In this figure, the write cycle starts with precharging Bank 1. After t = tPRE, the activation period starts and the row address is defined for the SDRAM. When the column address is generated after a time period of tCAS, four data packets, D(0) to D(3), are written to SDRAM core in four consecutive clock cycles. Note that in this figure if the same bank is used for another write, a new time period, tRAS, needs to be placed between the bank activation cycle and the next precharge period. 5.2 Synchronous Dynamic Random Access Memory 187 clock CS RAS CAS WE BS[1] BS[0] A[9:0] ROW COL DInOut D(0) tPRE tCAS D(1) D(2) tBURST D(3) tWAIT tRAS PRECHARGE BANK1 ROW ADDRESS COLUMN ADDRESS and and WRITE BANK1 ACTIVATE BANK1 PRECHARGE BANK1 Fig. 5.17 A single write cycle The example in Fig. 5.18 shows two separate write sequences into two different banks. When writing takes place more than a single bank, interleaving one bank’s precharge and activation time periods with respect to the other may result in a time-saving scenario where one write burst takes place immediately after the other, resulting in a shorter overall write period. In this figure, the interleaving technique results in writing four words to bank 1 immediately after writing four words to bank 0 without any cycle loss. Therefore, writing to two (or more) different banks as opposed to writing continuously to a single bank is a preferred scheme because this process eliminates all unnecessary waiting periods between precharge cycles. However, as the burst length involves a lot more than four words, the relative placement of the bank precharge cycle in the timing diagram becomes less important. 188 5 Memory Circuits and Systems clock CS RAS CAS WE BS[1] BS[0] A[9:0] ROW0 DInOut PRE BANK0 ACT BANK0 PRE BANK1 COL0 ROW1 D0(0) D0(1) WRITE BANK0 COL1 D0(2) D0(3) D1(0) D1(1) D1(2) D1(3) WRITE BANK1 ACT BANK1 Fig. 5.18 Multiple write cycles to different banks (tPRE = 1 cycle, tCAS = 2 cycles) The sixth row of Table 5.1 shows how to initiate a read cycle from a selected bank. Reading words from SDRAM involves a latency period, and it needs to be programmed in the Address Mode Register. The example in Fig. 5.19 shows the start of a read burst after a latency period of three clock cycles once the read command and the address are given. A latency of three clock cycles means that the data becomes available at the output of SDRAM in the third clock cycle after the address is issued. Read 8 WORDS from the Starting Address = 13 in Sequential Mode with Latency = 3 clock Address controls 13 Data LATENCY = 2 LATENCY = 1 D(13) D(14) D(15) LATENCY = 3 Mode Fig. 5.19 Definition of latency during a read cycle D(8) D(9) D(10) D(11) D(12) 5.2 Synchronous Dynamic Random Access Memory 189 The example in Fig. 5.20 shows a single read sequence from bank 1. Until the read command and the column address are issued, the read and write sequences follow identical paths. However, after this point the read burst starts following a latency period. Similar to the write process, a certain tRAS period must elapse between read bursts before additional streams of data become available from the same bank. In this figure, tWAIT corresponds to the waiting period between the last data packet read from the memory and the start of the next precharge period. clock CS RAS CAS WE BS[1] BS[0] A[9:0] ROW COL LATENCY = 3 DInOut D(0) tPRE PRECHARGE BANK1 tCAS tLAT ROW ADDRESS COLUMN ADDRESS and and READ BANK1 ACTIVATE BANK1 D(1) D(2) D(3) tBURST tRAS tWAIT LAST READ BANK1 PRECHARGE BANK1 Fig. 5.20 Single read cycle The example in Fig. 5.21 describes multiple reads from the same bank and assumes tWAIT is equal to zero. This scenario produces a read burst of four words, D(0) to D(3), from bank 1 and causes the same bank to be precharged during the last data delivery. The second read burst from bank 1 follows the same pattern as the first one and delivers D(4) to D(7) after a programmed latency of two clock periods. If tWAIT is different from zero, then the second precharge period should start right after the tWAIT period as described in Fig. 5.20. The interleaving technique used in reading data from two different banks in Fig. 5.22 is not any different from the one used when writing data to two different banks. As with the write case, the placement of the second precharge cycle in the timing diagram is important to achieve two consecutive read bursts, D0(0) to D0(3) from bank 0 and D1(0) to D1(3) from bank 1, without any cycle loss in between, accomplishing the shortest possible time to fetch data from SDRAM. 190 5 Memory Circuits and Systems clock CS RAS CAS WE BS[1] BS[0] A[9:0] COL ROW ROW COL LATENCY = 2 DInOut D(0) LATENCY = 2 D(1) D(2) D(3) D(4) D(5) D(6) D(7) tRAS PRECHARGE BANK1 ROW ADDRESS COLUMN ADDRESS and and ACTIVATE BANK1 READ BANK1 LAST READ and ROW ADDRESS COLUMN ADDRESS PRECHARGE and and BANK1 ACTIVATE BANK1 READ BANK1 Fig. 5.21 Multiple read cycles from the same bank (tPRE = 1 cycle, tCAS = 2 cycles, tWAIT = 0 cycle) clock CS RAS CAS WE BS[1] BS[0] A[9:0] ROW0 COL0 ROW1 DInOut COL1 D0(0) PRE BANK0 ACT BANK0 PRE COL ADDR ACT BANK1 and BANK1 READ BANK0 D0(1) D0(2) D0(3) D1(0) D1(1) D1(2) D1(3) COL ADDR and READ BANK1 Fig. 5.22 Multiple read cycles from different banks (tPRE = 1 cycle, tCAS = 2 cycles) The seventh row of Table 5.1 shows how to stop a read or a write burst. Figure 5.23 shows a single write sequence when the burst stop command is issued in the middle of a data 5.2 Synchronous Dynamic Random Access Memory 191 burst. Upon receiving this command, the selected bank goes into the standby mode and waits for the next precharge command. clock CS RAS CAS WE A[9:0] ROW COL DInOut PRECHARGE BANK0 ROW ADDRESS and ACT BANK0 COL ADDRESS and WRITE into BANK0 BURST STOP Fig. 5.23 Burst stop during write When the burst stop command is given in the middle of a read, the last data packet is still delivered at the clock edge following the burst stop command as shown in Fig. 5.24. clock CS RAS CAS WE A[9:0] ROW COL CAS LATENCY = 2 DInOut PRECHARGE BANK0 ROW ADDRESS COL ADDRESS and and READ from BANK0 ACT BANK0 Fig. 5.24 Burst stop during read BURST STOP 192 5 Memory Circuits and Systems The Input/Output data can be masked with the Read/Write Logic block in Fig. 5.11. The truth table in Table 5.5 lists all the possible cases of blocking and transmitting data to/from SDRAM core. When Mask[3:0] = 0000, for example, no mask is applied to the output data, and all 32 bits are allowed to be written to the selected bank or read from it. The case, Mask [3:0] = 1111, on the other hand, blocks all four bytes of data, and allows no byte to be written or read from the selected address. Table 5.5 Truth table for data output mask Mask [3] Mask [2] Mask [1] Mask [0] MASKED BITS 0 0 0 0 None 0 0 0 1 DInOut[7:0] 0 0 1 0 DInOut[15:8] 0 0 1 1 DInOut[15:0] 0 1 0 0 DInOut[23:16] 0 1 0 1 DInOut[23:16] and DInOut[7:0] 0 1 1 0 DInOut[23: 8] 0 1 1 1 DInOut[23:0] 1 0 0 0 DInOut[31:24] 1 0 0 1 DInOut[31:24] and DInOut[7:0] 1 0 1 0 DInOut[31:24] and DInOut[15:8] 1 0 1 1 DInOut[31:24] and DInOut[15:0] 1 1 0 0 DInOut[31:16] 1 1 0 1 DInOut[31:16] and DInOut[7:0] 1 1 1 0 DInOut[31:8] 1 1 1 1 DInOut[31:0] Figure 5.25 shows the data-path and the controller of the SDRAM bus interface. Prior to operating SDRAM, each ten-bit wide bus interface register containing the precharge (tPRE), CAS (tCAS), burst (tBURST), latency (tLAT), and wait (tWAIT) periods must be programmed through a 10-bit program bus. The precharge, CAS and wait registers contain the number of clock cycles to achieve the required waiting period. The burst register should store the number of data packets of the data transfer. Therefore, the value in this register must be identical to the value programmed in the Address Mode Register. The latency register specifies the number of clock cycles prior to reading the first data from an SDRAM address. The details of how the programming takes place prior to the normal SDRAM operation and the required hardware are omitted from Fig. 5.25 to avoid complexity. The Address Mode C 10 10 Program Data = { 0000, Addr[5:0] = Addr Mode Reg } P 10 Addr[19:10] = Row Addr StoreReg 5.2 Synchronous Dynamic Random Access Memory 10 Addr[9:0] = Column Addr R Addr[31:0] 2 Addr[21:20] Address Reg 4 Program Data Addr[31:28] 32 -1 A[9:0] tBURST tCAS tPRE BIWEn BIREn Status Write Burst Size SelRow SelCol tWAIT tLAT BS[1:0] 10 Bus Interface Control Unit Load tPRE P C B W Count Load tCAS clock D Q Load tBURST Load tWAIT SDRAM CS Load tPRE Load tCAS Load tBURST Load tWAIT RAS Addr Mode Reg CAS WE CountOut DIn/DOut[31:0] 32 Ready StoreReg EnWData EnRData 32 RData WData 193 Fig. 5.25 SDRAM bus interface block diagram 32 194 5 Memory Circuits and Systems Register (or a set of registers defining basic SDRAM functionality) exists in many older SDRAMs. However, recent SDRAM modules omit the mode register completely and rely on the bus interface unit to store such information. To manage the precharge, CAS, burst and wait periods the memory controller is continuously interact with a down-counter in Fig. 5.25 since these periods are often many clock cycles long. For normal SDRAM operation, the address bus, Addr[31:0], has been divided into several segments. In the example in Fig. 5.26, the four most significant bits of the SDRAM address, Addr[31:28], indicate the SDRAM chip identification, and it is used to activate the corresponding bus interface. Addr[21:20] is used to select the SDRAM bank, BS[1:0]. Addr[19:10] and Addr[9:0] specify the row and column addresses, respectively. Addr[31:0] = Addr[31:28] Addr[27:22] Addr[21:20] Addr[19:10] Addr[9:0] Activate SDRAM Bus Interface Reserved Bank select[1:0] = BS[1:0] Row Address[9:0] = A[9:0] Column Address[9:0] = A[9:0] Fig. 5.26 SDRAM bus interface address mapping Figure 5.27 shows a typical SDRAM write sequence. In this timing diagram, all five SDRAM interface registers must be programmed prior to the IDLE/PROG clock cycle as mentioned earlier. The SDRAM write sequence starts with the system bus sending Status = START, Write = 1 and the starting SDRAM address. These three signals cause the Bus Interface Write Enable signal, BIWEn, to transition to logic 1, which in turn, enables the bus interface for write in the first cycle of Fig. 5.27. Once enabled, the bus interface stores the starting SDRAM address in the Address Reg by StoreReg = 1 and issues the precharge command by CS = 0, RAS = 0, CAS = 1 and WE = 0 for the selected bank. Within the same cycle, the counter is loaded with the precharge wait period, tPRE, by LoadtPRE = 1 as shown in the timing diagram. The Precharge wait period is calculated by multiplying the number of clock cycles by the clock period. The counter in this design is a down-counter. When its output value, CountOut, becomes one, the controller initiates the activation cycle for the selected SDRAM bank and dispatches the row address. The activation period starts with loading the value of tCAS into the LOAD PRE tPRE tPRE tPRE LOAD CAS tCAS tCAS LOAD BURST START WRITE WRITE WRITE LOAD WAIT tWAIT tWAIT tWAIT clock Addr SDRAM Start Addr = A0 Status START Write WRITE A1 A2 A3 CONT CONT CONT Addr = B0 IDLE START WRITE BIWEn StoreReg SelRow SelCol CS RAS CAS WE BS[1:0] Bank 1 Bank 1 Bank 1 A[9:0] 5.2 Synchronous Dynamic Random Access Memory IDLE/ PROG ROW COL D0 WData D1 D2 D3 EnWData LoadtPRE Output of the down-counter 3 2 1 3 2 1 4 3 2 1 3 2 1 LoadtCAS LoadtBURST LoadtWAIT Ready PRE tPRE Row Addr + Act Bank1 tCAS tWAIT 195 Fig. 5.27 Write cycle with SDRAM bus interface BM sends WRITE data Col Addr + Write Bank1 tBURST 196 5 Memory Circuits and Systems down-counter by LoadtCAS = 1. Within the same clock cycle, the row address, Addr[19:10], is transferred from the Address Reg to the SDRAM through the R-port of the 3-1 MUX by SelRow = 1. When the activation wait period expires, the controller uses the LoadtBURST input to load the length of the write burst (the number of data packets) to the down-counter and subsequently initiates the write sequence in the next cycle. During the START WRITE period, the controller transfers the column address, Addr [9:0], from the Address Reg through the C-port of the 3-1 MUX to the A[9:0] port of the SDRAM by generating SelCol = 1. In the same cycle, the controller also generates CS = 0, RAS = 1, CAS = 0, WE = 0 and enables the tri-state buffer by EnWData = 1 in order to write the first data packet, D0, to the SDRAM. To be able to write the remaining data packets, the controller issues Ready = 1 from this point forward. When the sequence comes to the LOAD WAIT period (where the last write takes place), the controller lowers the Ready signal, but keeps the EnWData signal at logic 1 in order to write the last data packet, D3. This clock cycle also signifies the start of the wait period, tWAIT. The controller issues LoadtWAIT = 1 to load tWAIT into the down-counter if another write sequence needs to take place for the same bank. The remaining control signals, Burst and Size, are omitted from the timing diagram for simplicity. During the entire data transfer process, Burst is set to four and Size is set to 32 in Fig. 5.27. For byte and half-word transfers, Size needs to be defined with masking in place as described in Table 5.5. The state diagram of the controller for write is shown in Fig. 5.28. In this diagram, when the interface receives BIWEn = 1, the controller transitions from the IDLE/PROG state, which corresponds to the first cycle of the timing diagram in Fig. 5.27, to the LOAD PRE state, which corresponds to the second clock cycle in the same timing diagram. In the LOAD PRE state, the controller resets CS, RAS and WE, but sets CAS for the selected bank to start the precharge process. In this state, two additional signals are generated: StoreReg = 1 to store the bus address in the Address Reg, and LoadtPRE = 1 to start the precharge wait period. In the next cycle, the controller transitions to the precharge wait state, tPRE. The controller remains in this state until CountOut = 1. The controller then transitions to the LOAD CAS state where it activates the selected bank, issues SelRow = 1 to transfer the row address to the SDRAM, and produces LoadtCAS = 1 to initiate the activation wait period. The next state, tCAS, is another wait state where the controller waits until the activation period expires. Once this period is over, the controller first goes into the LOAD BURST state, and then to the START WRITE state to initiate writing data to the SDRAM. The latter corresponds to the state where the first data packet is written to the SDRAM core as mentioned earlier. The subsequent writes take place when the controller transitions to the WRITE state. The controller stays in this state until CountOut = 2, which signifies one more data packet to be written to the SDRAM. The last data packet is finally written when the controller moves to the LOAD WAIT state. Before attempting another write process, the controller waits in the tWAIT state until CountOut = 1. 5.2 Synchronous Dynamic Random Access Memory 197 Note that all the state names in Fig. 5.28 and the cycle names on top of Fig. 5.27 are kept the same to make one-to-one correspondence between the timing diagram and the state diagram. else IDLE/ PROG CS = 0 RAS = 0 CAS = 0 WE = 0 Ready = 0 Status = START Write = 1 Addr = SDRAM start addr LOAD PRE StoreReg = 1 CS = 0 RAS = 0 CAS = 1 WE = 0 Loadt PRE = 1 Ready = 0 Status = START Write = 1 Addr = SDRAM start addr else CountOut = 1 CountOut > 1 tPRE Ready=0 CountOut > 1 tWAIT Ready=0 CountOut = 1 LOAD CAS SelRow = 1 CS = 0 RAS = 0 CAS = 1 WE = 1 A [9:0] = Addr [19:10] = Row Address LoadtCAS = 1 Ready = 0 LOAD WAIT EnWData = 1 LoadtWAIT = 1 Ready = 0 CountOut = 2 CountOut > 2 tCAS Ready=0 CountOut > 2 WRITE EnWData = 1 Ready = 1 CountOut = 2 LOAD BURST Loadt BURST = 1 Ready = 1 START WRITE SelCol = 1 CS = 0 RAS = 1 CAS = 0 WE = 0 A [9:0] = Addr [9:0] = Col Address EnWData = 1 Ready = 1 Fig. 5.28 SDRAM bus interface for write The SDRAM read sequence also starts with the system bus sending Status = START, Write = 0 and an initial SDRAM address. This combination sets the Bus Interface Read Enable signal, BIREn = 1, to enable the bus interface to read data from the SDRAM core in the first cycle of the timing diagram in Fig. 5.29. The remainder of the read process is LOAD PRE tPRE tPRE tPRE LOAD CAS tCAS tCAS tCAS START READ LAT WAIT READ READ LOAD WAIT A1 A2 A3 CONT CONT D1 D2 READ tWAIT tWAIT tWAIT 198 IDLE/ PROG clock Addr SDRAM Start Addr = A0 Status START Write READ ST Addr CONT IDLE START BIREn StoreReg SelRow SelCol CS RAS CAS WE BS[1:0] Bank1 A[9:0] Bank1 Bank1 ROW COL D0 RData D3 Latency = 2 EnRData LoadtPRE Output of the down-counter 3 2 1 3 2 1 4 3 2 1 3 2 1 5 LoadtCAS LoadtWAIT Ready PRE tPRE Row Addr + Act Bank1 tCAS Col Addr + Read Bank1 tLAT Fig. 5.29 Read cycle with SDRAM bus interface BM reads SDRAM data tBURST tWAIT Memory Circuits and Systems LoadtBURST 5.2 Synchronous Dynamic Random Access Memory 199 identical to the write process until the controller issues the read command during the START READ cycle, and sends the column address of the selected SDRAM bank. Since SDRAM data becomes available after a latency period, the controller must replicate this exact delay prior to a read burst and produce the control signals during and after the burst. For example, a cycle before the latency period expires, the controller needs to generate LoadtBURST = 1 to load the burst duration to the down-counter to be able to detect the beginning and the end of burst data. As a result, the controller can determine when to generate EnRData = 1 for the tri-state buffer to read data packets, D0 to D3, from the SDRAM RData output. During the last data delivery, the controller issues LoadtWAIT = 1 to load the value of tWAIT to the down-counter in the event the same bank is selected for another read. The state diagram in Fig. 5.30 for the read sequence is a direct result of the timing diagram in Fig. 5.29. In this diagram, when the interface receives BIREn = 1, the controller transitions from the IDLE state which corresponds to the first cycle in Fig. 5.29, to the LOAD PRE state which corresponds to the second clock cycle in the same timing diagram. In the LOAD PRE state, the precharge process is initiated by CS = 0, RAS = 0, WE = 0 and CAS = 1 for the selected bank. In this state, the controller stores the valid bus address in the Address Reg by StoreReg = 1, and loads the precharge wait period into the down-counter by LoadtPRE = 1. Then the controller moves to the tPRE and stays in this state until the precharge value in the down-counter expires. Next, the controller transitions to the LOAD CAS state where it activates the selected bank by CS = 0, RAS = 0, CAS = 1 and WE = 1, issues SelRow = 1 to transfer the row address from the Address Reg to the SDRAM, and generates LoadtCAS = 1 to load the activation wait period to the down-counter. The CAS wait period corresponds to the tCAS state in Fig. 5.30. When this period is over at CountOut = 1, the controller transitions to the START READ state where it issues CS = 0, RAS = 1, CAS = 0 and WE = 1 to initiate the data read and produces SelCol = 1 to transfer the column address from Address Reg to the SDRAM address port. This state is followed by four individual latency states to select the programmed read latency period. Since the read latency in Fig. 5.29 is equal to two, the state machine traces through a single LAT WAIT state. In the LAT WAIT state, the controller issues LoadtBURST = 1 and loads the value of the data burst, tBURST, to the down-counter. Following the latency states, the state machine transitions to the READ state where it stays until CountOut = 2, signifying the end of the read burst. Here, it produces EnRData = 1 to enable the data output buffer and Ready = 1 to validate the read data. At the end of the burst period, the state machine moves to the LOAD WAIT state and issues LoadtWAIT = 1 to load the required wait period into the down-counter until the next precharge takes place. Subsequently, the state machine transitions to the tWAIT state and stays there until the wait period is over. 200 5 else Memory Circuits and Systems CS = 0 RAS = 0 CAS = 1 WE = 0 Ready = 0 Status = START Write = 0 Addr = SDRAM Start Addr IDLE/ PROG StoreReg = 1 CS = 0 RAS = 0 CAS = 1 WE = 0 Load t PRE = 1 Ready = 0 LOAD PRE else Status = START Write = 0 Addr = SDRAM Start Addr CountOut > 1 tPRE Ready=0 CountOut = 1 SelRow = 1 CS = 0 RAS = 0 CAS = 1 WE = 1 A [9:0] = Addr [19:10] = Row Address Load tCAS = 1 Ready = 0 LOAD CAS CountOut = 1 CountOut > 1 tWAIT Ready=0 CountOut > 1 tCAS LOAD WAIT Ready=0 LoadtWAIT = 1 EnRData = 1 Ready = 1 CountOut = 1 CountOut = 2 START READ SelCol = 1 CS = 0 RAS = 1 CAS = 0 WE = 1 A [9:0] = Addr [9:0] = Col Address Ready = 0 LATENCY = 2 CountOut > 2 READ LAT WAIT Load tBURST = 1 Ready = 0 LATENCY = 3 LAT WAIT Ready = 0 LATENCY = 4 LATENCY = 5 LAT WAIT Load tBURST = 1 Ready = 0 LAT WAIT LAT WAIT Ready = 0 Ready = 0 LAT WAIT LAT WAIT LAT WAIT Ready = 0 Ready = 0 Ready = 0 Fig. 5.30 SDRAM bus interface for read LAT WAIT Load tBURST = 1 Ready = 0 LAT WAIT Load tBURST = 1 Ready = 0 EnRData = 1 Ready = 1 5.3 Electrically-Erasable-Programmable-Read-Only-Memory 5.3 201 Electrically-Erasable-Programmable-Read-Only-Memory Electrically-Erasable-Programmable-Read-Only-Memory (E2PROM) is historically considered the predecessor of Flash memory and also the slowest memory in a computing system. Its greatest advantage over the other memories is its ability to retain data after the system power is turned off due to the floating-gate MOS transistor in its memory core. Its relatively small size compared to electromechanical hard disks makes this device an ideal candidate to store Built-In-Operating-Systems (BIOS) especially for hand-held computing platforms. A typical E2PROM memory is composed of multiple sectors, each of which contains multiple pages as shown in the example in Fig. 5.31. A single word in E2PROM can be located by specifying its sector address, page address and row address. The sector address indicates which sector a particular word resides. The page address locates the specific page inside a sector. Finally, the row address points to the location of the data byte inside a page. There are five control signals in E2PROM to perform read, write or erase operations. The active-low Enable signal, EN, places a particular page in standby mode and prepares it for an upcoming operation. The active-low Command Enable signal, CE, is issued with a command code, such as read, write (program) or erase. The active-low Address Enable signal, AE, is Page Addr[3:0] Sector Addr[3:0] 4 4 Sector 15 7 Sector 0 7 0 0 255 255 8 Row Addr[7:0] WE RE Page15 0 E2PROM Read/Write Interface 8 I/O Fig. 5.31 A typical E2PROM organization 0 Page0 Page1 AE Page15 Page1 CE Page0 EN 202 5 Memory Circuits and Systems issued when an address is provided. Finally, the active-low Write Enable signal, WE, and the Read Enable signal, RE, are issued for writing and reading data, respectively. Typical E2PROM architecture consists of a memory core, an address decoder, an output data buffer, status, address and command registers, and a control logic circuit as shown in Fig. 5.32. Prior to any operation, command and address registers are programmed. When the operation starts, the control logic enables the address decoder, the data buffer and the memory core using the active-high Enable Address (ENA), Enable Data Buffer (END), and Write Enable Core (WEC) or Read Enable Core (REC) signals depending on the operation. The address stored in the address register is decoded to point the location of data. If the read operation needs to be performed, the required data is retrieved from the E2PROM core and stored in the data buffer before it is delivered to the I/O bus. If the operation is a write (or program), the data is stored in the data buffer first before it is uploaded to the designated E2PROM address. In all cases, EN needs to be at logic 0 to place E2PROM into standby mode before starting an operation. The table in Fig. 5.33 describes all major operation modes. Hibernate mode disables the address decoder, memory core and data buffer to reduce power dissipation, and puts the device into sleep. WEC/REC EN ENA AE WE Address Decoder CE Control Logic RE To I/O[7:0] Status Register From I/O[7:0] Command Register From I/O[7:0] Address Register Fig. 5.32 A typical E2PROM architecture Row + Page + Sector Addr 16 Memory Core 8 Data Buffer END 8 I/O[7:0] 5.3 Electrically-Erasable-Programmable-Read-Only-Memory 203 EN WE RE 0 1 1 Standby 0 0 1 Write 0 1 0 Read 1 X X Hibernate Fig. 5.33 E2PROM major operation modes The E2PROM cell shown in Fig. 5.34 is basically an N-channel MOS transistor with an additional floating gate layer sandwiched between its control gate terminal (Wordline) and the channel where the electronic conduction takes place. This device has also drain (Bitline) and source (Sourceline) terminals for connecting the cell to the neighboring circuitry. To write logic 0 into the memory cell, a high voltage is applied between Wordline and Bitline terminals while the Sourceline node remains connected to ground. This configuration generates hot carriers in the transistor channel which tunnel through the gate oxide and reach the floating gate, raising the threshold voltage of the transistor. The raised threshold voltage prevents the programmed device to be turned on by the standard gate-source voltage used during normal circuit operations, and causes the value stored in the device to be interpreted as logic 0. An unprogrammed device with no charge on the floating gate, on the other hand, exhibits low threshold voltage characteristics and can be turned on by the standard gate-source voltage, producing a channel current. In this state, the value stored in the device is interpreted as logic 1. Wordline Sourceline Floating gate Bitline Channel Fig. 5.34 E2PROM cell Figure 5.35 shows a typical command input sequence. There are four basic commands for this E2PROM example: read, write (program), page-erase and status register read. The write and program commands will be used interchangeably here and when describing the Flash memory since they mean the same operation. The operation sequence always starts with the command input followed by the address and data entries. To issue a command input, EN is lowered to logic 0, AE is raised to logic 1 (because the entry is not an address), and CE is lowered to logic 0, indicating that the value on the I/O bus is a command input. Since the command input is written into the command register WE is also lowered to logic 0 some 204 5 Memory Circuits and Systems time after the negative edge of CE signal. This delay is called the setup time (tS) as shown in Fig. 5.35. The low phase of WE signal lasts for a period of tLO, and transitions back to logic 1 some time before the positive edge of CE. This time interval is called the hold time, tH. Prior to the positive edge of WE, a valid command input is issued, satisfying the data setup time, tDS, and the data hold time, tDH, as shown in Fig. 5.35. EN AE CE tS tLO tH WE tDS I/O[7:0] tDH Command Input Fig. 5.35 Command input timing diagram The address input timing shown in Fig. 5.36 has the same principle as the command input timing described above: EN needs to be at logic 0 to enable the device, AE must be at logic 0 for the address entry, and CE needs to be at logic 1 because this operation is not a command entry. During the low phase of EN signal, WE signal must be lowered to logic 0 twice to locate data in the E2PROM. The first time WE = 0, an eight-bit row address is entered at the first positive edge of WE. This is followed by the combination of four-bit page address and four-bit sector address at the next WE = 0. The WE signal must be lowered to logic 0 after a period of tS, following the negative edge of the EN signal, and then back to logic 1 for a period of tH before the positive edge of EN. The WE signal must also be at the low phase for a period of tLO and at the high phase for a period of tHI (or longer) during the address entry. Valid address values are issued at each positive edge of WE within the tDS and tDH setup and hold time periods. 5.3 Electrically-Erasable-Programmable-Read-Only-Memory 205 EN AE CE tS tLO tHI tH WE tDS I/O[7:0] tDH A[7:0] A[15:8] Row Address Page + Sector Address Fig. 5.36 Address input timing diagram Figure 5.37 describes data entry sequence where (M + 1) number of data packets are written to the E2PROM. During the entire write cycle AE signal must be at logic 1, indicating that the operation is a data entry but not an address. Data packets are written at each positive edge of WE signal. EN AE CE tS tLO tHI tH WE tDS I/O[7:0] tDH DIn0 DIn1 DInM Fig. 5.37 Data input (write or program) timing diagram During a read the active-low control signals, AE and CE, are kept at logic 1. The Read Enable signal, RE, enables the E2PROM to read data from the memory core at each negative edge as shown in Fig. 5.38. The time delay between the negative edge of RE and the actual 206 5 Memory Circuits and Systems availability of data from the memory is called the access time, tA, as shown in the same timing diagram. The RE signal must have the specified tS, tH, tLO and tHI time periods to be able to read data from the memory core. EN AE CE tS tLO tHI tH RE I/O[7:0] DOut0 DOut1 DOutM tA Fig. 5.38 Data output (read) timing diagram Reading data from the Status Register is a two-step process. The first step involves entering the command input, Status Register Read, at the positive edge of the WE signal. The contents of the register are subsequently read sometime (tA) after the negative edge of RE as shown in Fig. 5.39. Note that CE signal is initially kept at logic 0 when entering the command input, but raised to logic 1 when reading the contents of the Status Register. A full-page write data entry consists of the combination of four tasks as shown in Fig. 5.40. The first task is entering the Write to Data Buffer command at the positive edge of WE while keeping CE at logic 0. The second task is entering the page and sector addresses at the positive edge of WE while AE is at logic 0. The third task is entering the full-page of data from D(0) to D(255) into the data buffer at each positive edge of WE signal. Both AE and CE are kept at logic 1 during this phase. The last task is entering the Write to Core Memory command in order to transfer all 256 bytes of data from the data buffer to the memory core. The last cycle needs a relatively longer time period, tWRITE, to complete the full-page write. The read operation is composed of three individual tasks similar to the write operation as shown in Fig. 5.41. The first task is entering the Read from Memory command at the positive edge of WE while CE is at logic 0. The second step is entering the starting address by specifying the row, page and sector address values at each positive edge of WE while AE is at logic 0. The third task is to read data from the memory core at each negative edge of RE while CE and AE signals are at logic 1. 5.3 Electrically-Erasable-Programmable-Read-Only-Memory 207 EN AE CE tS tLO tH tS WE tLO tH RE tDS I/O[7:0] tA tDH Status Read SR contents SR Read Command Read SR Contents Fig. 5.39 Timing diagram for reading status register EN tS tH AE CE tS tH tH tS WE tS tH RE tWRITE I/O[7:0] WrtDB Program Command Register: Write to Data Buffer Command A15-8 Page + Sector Address DI(0) DI(1) DI(255) Full Page Fig. 5.40 Timing diagram for full-page write (program) WrtCM Program Command Register: Write to Core Memory Command 208 5 Memory Circuits and Systems EN AE tS tH CE tS tH WE tS tH RE I/O[7:0 ] Read A7-0 Row Address Program Command Register: Read from Memory Command A15-8 DO(N) Page + Sector Address DO(N+1) DO(N+255) From Starting Addr From Last Addr Fig. 5.41 Timing diagram for full-page read A typical full-page erase is described in Fig. 5.42. In this figure, the Erase Full Page command is entered first at the positive edge of WE while CE is at logic 0. The memory address, EN AE tS tH CE tS tH tH tS WE RE t ERASE I/O[7:0] FPEras Program Command Register: Erase Full Page Command A15-8 Page + Sector Address CMEras Program Command Register: Erase Core Memory Command Fig. 5.42 Timing diagram for full-page erase 5.3 Electrically-Erasable-Programmable-Read-Only-Memory 209 composed of page and sector addresses, is entered next while AE is at logic 0. The Erase Core Memory command is entered following the address while CE is at logic 0. Full-page erase time period, tERASE, must be employed to complete the operation. 5.4 Flash Memory Flash memory is the successor of the Electrically-Erasable-Programmable-Read-OnlyMemory (E2PROM), and as its predecessor it has the capability of retaining data after power is turned off. Therefore, it is ideal to use in hand-held computers, cell phones and other mobile platforms. A typical Flash memory is composed of multiple sectors and pages as shown in Fig. 5.43. An eight-bit word can be located in a Flash memory by specifying the sector, the page and the row addresses. To be compatible with the E2PROM architecture example given in the previous section, this particular Flash memory also contains 16 sectors and 16 pages. Each page contains 256 bytes. The sector address constitutes the most significant four bits of the 16-bit Flash address, namely Addr[15:12]. Each page in a sector is addressed by Addr[11:8], and each byte in a page is addressed by Addr[7:0]. There are five main control signals in Flash memory to perform basic read, write (program), erase, protect and reset operations. Write and program commands are equivalent to each other, and used interchangeably Addr[15:8] = Addr[15:12] = Sector[3:0] Addr[11:8] = Page[3:0] 8 Sector 15 7 Sector 0 7 0 0 255 255 8 WE Reset 0 Page 15 RE 0 Flash Read/Write Interface 8 I/O[7:0] Fig. 5.43 Flash memory organization Page 15 EN Page 1 Page 0 Page 1 Page 0 Addr[7:0] = Row[7:0] 210 5 Memory Circuits and Systems throughout the manuscript when describing Flash memory operations. Many Flash datasheets use the term, program, to define writing a byte or a block of data to Flash memory. The active-low Enable input, EN, activates a particular page in the Flash memory to prepare it for an upcoming operation. The active-low Read Enable input, RE, activates the Read/Write interface to read data from the memory. The active-low Write Enable input, WE, enables to write (program) data to the memory. The active-low Reset input, Reset, is used for resetting the hardware. After this command, Flash memory automatically goes into the read mode. Typical Flash memory architecture, much like the other memory structures we have examined earlier, consists of a memory core, address decoder, sense amplifier, data buffer and control logic as shown in Fig. 5.44. When a memory operation starts, the control logic enables the address decoder, the address register, and the appropriate data buffers in order to activate the read or the write data-path. The address in the address register is decoded to point the location of data in the memory core. If a read operation needs to be performed, the retrieved data is first stored in the data buffer, and then released to the bus. If the operation calls for a write, the data is stored in the data buffer first, and then directed to the designated address in the memory core. The standby mode neither writes to the memory nor reads from it. The hibernation mode disables the address decoder, memory core and data buffer to reduce power dissipation. The main Flash operation modes are tabulated in Fig. 5.45. I/O[7:0] Data Buffer EN RE Control Logic WE Reset Address Decoder Address[15:0] Address Register Sector 15 High voltage Fig. 5.44 Flash memory architecture Sector 14 Sector 0 5.4 Flash Memory 211 EN RE WE reset 0 0 1 1 Read 0 1 0 1 Write 0 1 1 1 Standby 1 X X 1 Hibernate X X X 0 Hardware reset MODE Fig. 5.45 Main modes of Flash memory The Flash memory cell shown in Fig. 5.34 is the basic storage element in the Flash memory core. It is an N-channel MOS transistor with a floating gate whose sole purpose is to store electronic charge. The device needs high voltages well above the power supply voltage to create and transfer electrons back and forth to the floating gate according to the need. If there is no secondary high voltage supply for this job, the control logic in Fig. 5.44 may contain a charge pump circuit composed of a constant current source and a capacitor in order to obtain a higher DC voltage from the primary power supply for a short duration. As the constant current charges the capacitor, the voltage across the capacitor rises linearly with time, ultimately reaching a high DC potential to create electron-hole pairs near the Bitline contact (drain) of the device, ultimately causing the electrons to tunnel to the floating gate. The mechanism of electron tunneling to the floating gate requires time. Therefore, a write or erase operation may take many consecutive clock cycles compared to simple control operations such as suspend or resume. Figure 5.46 shows the basic read operation provided that data has already been transferred from the memory core to the data buffer. Once a valid address is issued, data is produced at the I/O terminal some time after the falling edge of the Read Enable signal, RE. Data is held at the I/O port for a period of hold time, th, following the rising edge of RE as shown in the timing diagram below. The actual read operation takes about four clock cycles as the entire data retrieval process from the memory core takes time. This involves sensing the voltage level at the Flash cell, amplifying this value using the sense amplifier, and propagating the data from the sense amplifier to the data buffer. In contrast to read, the basic write operation follows the timing diagram of Fig. 5.47. In this figure, a valid address must be present at the address port when the Enable and the Write Enable signals, EN and WE, are both at logic 0. Valid data satisfying the setup and hold times, ts and th, is subsequently written to the data buffer. The actual write process can take up to four clock cycles due to the data propagation from the I/O port to the data buffer, and then from the data buffer to the Flash cell. 212 5 Memory Circuits and Systems tcommand Addr Address EN RE WE Reset th tacc I/O[7:0] Data Fig. 5.46 Basic read operation timing diagram tcommand Addr Address EN RE WE Reset ts I/O[7:0] th Data Fig. 5.47 Basic write (program) operation timing diagram Disabling the I/O port for read or write, and therefore putting the device in standby mode requires EN signal to be at logic 0 as shown in Fig. 5.48. The I/O port will float and show high impedance (Hi-Z). 5.4 Flash Memory 213 tcommand Addr Address EN RE WE Reset I/O[7:0] Hi-Z Fig. 5.48 Basic standby operation Hardware reset requires only lowering the Reset signal during the command cycle as shown in Fig. 5.49. The actual reset operation takes three bus cycles and resets the entire Flash memory. tcommand Addr Address EN X RE X WE X Reset I/O[7:0] Hi-Z Fig. 5.49 Basic hardware reset operation timing diagram Basic Flash memory operations are tabulated in Fig. 5.50. In actuality, there are a lot more commands in commercially available Flash memories than what is shown in this table. This section considers only essential byte-size operations in a Flash memory. Word-size 214 MAIN COMMANDS CYCLE 1 Addr Data CYCLE 2 Addr Data CYCLE 3 Addr Data Read 0x5555 0xAA 0xAAAA 0x55 0x5555 0x00 ID Read 0x5555 0x5555 0xAA 0xAA 0xAAAA 0xAAAA 0x55 0x55 0x5555 0x5555 0x10 0x20 Page Addr 0xAAAA 0xAAAA 0x55 0x55 0x5555 0x5555 Page Addr 0xA0 Write Write suspend Write resume Page Addr Page protect Page Addr 0xA0 Fast write set 0x5555 0xAA 0xAAAA 0x55 Fast write 0xXXXX 0xC0 Write Addr Write Data Fast write reset 0xXXXX 0xD0 0xXXXX 0xE0 Reset 0x5555 0xAA 0xAAAA 0x55 Page erase Page Addr 0x5555 0x5555 CYCLE 6 Read Data Manuf. Addr Manuf. Data Device Addr Device Data Write Addr Write Data 0x50 0x50 0x5555 0x5555 0xAA 0xAA Page Addr 0xA0 Page Addr Verif. Code 0x5555 0xB0 0x5555 0xF0 0xAAAA 0xAAAA 0x55 0x55 0x5555 Page Addr 0x60 0x70 Fig. 5.50 Flash memory commands with required clock cycles Memory Circuits and Systems Page Addr Chip erase Read Addr CYCLE 5 5 Page erase suspend Page erase resume 0x30 0x40 0xAA 0xAA 0x80 0x90 CYCLE 4 Addr Data 5.4 Flash Memory 215 operations, very specific Flash command sequences, such as hidden ROM programs, query and verification commands and boot protection processes are avoided in order to emphasize the core Flash memory operations for the reader. Address and data entries for each specific command in Fig. 5.50 are also modified compared to the actual datasheets to simplify the read, write (program) and erase sequences. The number of clock cycles, the address and data preamble values in each cycle, and the operational codes to perform read, write, page erase, chip erase, page protect, fast write and other modes of operation may be different from the actual datasheets. The first task in Fig. 5.50 is the Flash memory read sequence which takes four clock cycles. The first three clock cycles of this sequence represents the waiting period to prepare the read path from the memory core. During this period, address and data values in the form of alternating combinations of 1s and 0s, such as 0x5555/0xAA and then 0xAAAA/0x55, are introduced at the address and data ports of the Flash memory as shown in Fig. 5.51. Once the read command, 0x00, is issued in the third clock cycle, a byte of data becomes available shortly after the negative edge of the RE signal in the fourth and final clock cycle. Cycle 1 Addr 0x5555 Cycle 2 0xAAAA Cycle 3 0x5555 Cycle 4 Addr EN WE RE I/O[7:0] 0xAA 0x55 Read command Fig. 5.51 Timing diagram for read operation 0x00 Data Read data 216 5 Memory Circuits and Systems Figure 5.52 shows an example of the read operation which extracts the manufacturer’s ID and device ID from the Flash memory. The first three clock cycles of this sequence are the same as the normal read operation, but with the exception of the ID read code, 0x10. The next two cycles deliver the manufacturer’s ID and the device ID following the negative edge of the RE signal. Cycle 1 Addr 0x5555 Cycle 2 0xAAAA Cycle 3 0x5555 Cycle 4 Man Addr Cycle 5 Dev Addr EN WE RE I/O[7:0] 0xAA 0x55 ID read command 0x10 Man Data Manufacturer ID read Dev Data Device ID read Fig. 5.52 Timing diagram for ID read operation There are basically two types of write (program) operations for the Flash memory: auto write (program) and fast write (program). Figure 5.53 explains the auto write sequence where the first three cycles are the same as the read sequence with the exception of the auto write command code, 0x20, in the third clock cycle. In the fourth cycle, a valid address and a data are entered to the device when EN and WE are both lowered to logic 0. The valid data is subsequently written to the specified address at the positive edge of WE. The data written to the Flash memory can be retrieved in the following cycle without going through a separate read sequence. This is called the auto write verification step, and the most recent written data becomes available at the I/O port as soon as RE is lowered to logic 0. 5.4 Flash Memory 217 Cycle 1 Addr 0x5555 Cycle 2 Cycle 3 0xAAAA Cycle 4 0x5555 Write Addr Write Addr EN WE RE I/O[7:0] 0xAA 0x55 0x20 Write Data Write command Write Data Write Data Verification Fig. 5.53 Timing diagram for write (program) operation The write sequence can be suspended or resumed depending on the need. Both operations take only one clock cycle with the appropriate suspend and resume codes as shown in Figs. 5.54 and 5.55, respectively. The write suspend and resume codes can be read in the second cycle as a verification step. Cycle 1 Addr Page Addr Page Addr EN WE RE I/O[7:0] 0x30 Write suspend command Suspend comm. Verification Fig. 5.54 Timing diagram for write (program) suspend operation 218 5 Memory Circuits and Systems Cycle 1 Addr Page Addr Page Addr EN WE RE I/O[7:0] 0x40 Write resume command Resume comm. Verification Fig. 5.55 Timing diagram for write (program) resume operation The erase operation can be applied either to the entire chip or to a particular page. Both sequences take six clock cycles because of the lengthy nature of erase process. In the auto chip erase operation, the first three and the last three cycles are almost identical except the two new codes, 0x50 and 0x60, are introduced in the third and in the sixth cycles as shown in Fig. 5.56. Cycle 1 Addr 0x5555 Cycle 2 0xAAAA Cycle 3 0x5555 Cycle 4 0x5555 Cycle 5 0xAAAA Cycle 6 0x5555 EN WE RE I/O[7:0] 0xAA 0x55 0x50 0xAA Chip erase command Fig. 5.56 Timing diagram for chip erase operation 0x55 0x60 5.4 Flash Memory 219 The first five clock cycles of the page erase operation are identical to the chip erase as shown in Fig. 5.57. The page address to be erased is supplied with the page erase command, 0x70, in the sixth cycle. Cycle 1 Addr Cycle 2 0x5555 Cycle 3 0xAAAA Cycle 4 0x5555 0x5555 Cycle 5 Cycle 6 0xAAAA Page Addr EN WE RE I/O[7:0] 0xAA 0x55 0x50 0xAA 0x55 Page erase command 0x70 Page Addr input Fig. 5.57 Timing diagram for page erase operation A certain Flash memory page can be protected from being overwritten or erased by issuing a page protect operation. This is a three-cycle operation as shown in Fig. 5.58. In all three cycles, the page address and the page protect code, 0x0A, have to be specified. Cycle 1 Addr Page Addr Cycle 2 Page Addr Cycle 3 Page Addr Page Addr EN WE RE I/O[7:0] 0xA0 0xA0 0xA0 Page protect command Fig. 5.58 Timing diagram for page protect operation Protect com Verification 220 5 Memory Circuits and Systems If faster writing speed is required from the Flash memory, the fast write (program) sequence can be used. This sequence is composed of three parts: fast write set, fast write and fast write reset. The fast write set and reset codes are entered at the beginning and at the end of a write sequence. Figure 5.59 shows the timing diagram for the fast write set sequence where the set code, 0xB0, is entered in the third clock cycle. Cycle 1 Addr Cycle 2 0x5555 Cycle 3 0xAAAA 0x5555 EN WE RE I/O[7:0] 0xAA 0x55 0xB0 Fast write set command Fig. 5.59 Timing diagram for fast write (program) set operation The timing diagram for the fast write is a two-cycle sequence as shown in Fig. 5.60. In the first cycle, the fast write code, 0xC0, is entered. In the second cycle, a valid address/data pair is entered at the positive edge of WE. Cycle 1 Addr 0xXXXX Cycle 2 Write Addr EN WE RE I/O[7:0] 0xC0 Write Data Fast write command Fig. 5.60 Timing diagram for fast write (program) operation 5.4 Flash Memory 221 The fast write reset sequence shown in Fig. 5.61 is also a two-cycle process with two fast write termination codes, 0xD0 and 0xE0, entered in two consecutive clock cycles. Cycle 1 Addr Cycle 2 0xXXXX 0xXXXX EN WE RE I/O[7:0] 0xD0 0xE0 Fast write reset command Fig. 5.61 Timing diagram for fast write (program) reset operation Device reset can be initiated either by Reset input in Fig. 5.48 or by entering the reset code, 0xF0, in the third clock cycle of Fig. 5.62. Cycle 1 Addr 0x5555 Cycle 2 0xAAAA Cycle 3 0x5555 EN WE RE I/O[7:0] 0xAA 0x55 Reset command Fig. 5.62 Timing diagram for Reset operation 0xF0 222 5 Memory Circuits and Systems Both reading and writing (programming) data are cyclic processes. This means that a loop has to be established in the user program to generate a series of memory addresses to read or write data. Figure 5.63 shows the auto write (program) flow chart where a loop is created to generate the next write address. Each box in the flow chart corresponds to a clock cycle. The first three boxes of the flow chart prepare the memory core for a write operation. The preparation period terminates with the auto write code, 0x20, as mentioned earlier in Fig. 5.53. After entering the first write address and data, the memory address is incremented in the fourth cycle. The same process repeats itself prior to issuing the next address and data. When the final address is reached, the write process simply terminates. Start 0x5555/0xAA 0xAAAA/0x55 Write sequence 0x5555/0x20 Write Addr/ Write Data Addr = Addr + 1 NO Last Addr YES Complete Fig. 5.63 Flow chart for write (program) 5.4 Flash Memory 223 The sequence of events is a little different for the fast write (program) in Fig. 5.64. The fast write phase starts with the three-cycle long fast write set sequence followed by the two cycle long fast write sequence. The memory address keeps incrementing until the last data byte is written to the core. The fast write process ends with the two-cycle long fast write reset sequence. Auto write and fast write processes can be interrupted or resumed by issuing one-cycle long suspend and resume commands anytime during the write process. Start 0x5555/0xAA 0xAAAA/0x55 Fast write set sequence 0x5555/0xB0 0xXXXX/0xC0 Fast write sequence Write Addr/ Write Data Addr = Addr + 1 NO Last Addr YES 0xXXXX/0xD0 Fast write reset sequence 0xXXXX/0xE0 Complete Fig. 5.64 Flow chart for fast write (program) 224 5 Memory Circuits and Systems In the following sections, we will demonstrate how to design three individual I2C bus interfaces with Flash memory to perform read, write and erase operations. In each design, we will assume only one mode of operation to simplify the design process. After studying each design example, the reader is encouraged to design a single interface that integrates all three operations. Design Example 1: I2C Fast Write (Program) Interface for Flash Memory The following design example constructs only the I2C fast write (program) interface for a Flash memory that has parallel address and data ports as shown in Fig. 5.44 using a modified seven-bit address mode. No read, auto write, erase, page protect, reset or other modes are included in this design for the sake of simplicity. Before dealing with the design details and methodology, it may be prudent to review the timing diagram of I2C write sequence using the seven-bit addressing mode. Although Fig. 5.65 includes only one byte of data, it describes the entire write protocol for the seven-bit address mode in Fig. 4.22. This diagram also includes the start and the stop conditions in Fig. 4.23, and when data (or address) is allowed to change in Fig. 4.24. After generating the start condition, the bus master delivers a seven-bit slave address, starting from the most significant bit, A6. The address sequence is followed by the write bit at logic 0. Once the slave receives the seven-bit address and the write command, it produces an acknowledgment, ACK, by lowering the SDA bus to logic 0. The master detects the ACK signal, and sends out an eight-bit data starting from the most significant bit, D7. Once the entire byte is received, the slave responds with another ACK. More data packets follow the same routine until the master generates the stop condition. A6 A5 A0 W ACK D7 D6 D0 ACK SCL Master Master sends sends Master Master I2C sends sends ACK SDA START A6 A5 A0 W=0 I2C reads I2C reads I2C reads I2C reads Master Master sends sends ACK D7 Master I2C reads reads D6 I2C reads Master sends I2C ACK D0 I2C reads ACK Master reads STOP Fig. 5.65 A simple timing diagram for I2C write (program) using seven-bit address mode In Fig. 5.65, the names that appear on top of each SCL cycle describe a distinct state. If a state machine needs to be constructed from this timing diagram, we simply assign an independent state that corresponds to each name in Fig. 5.65 and produce a state diagram in Fig. 5.66. In this diagram, the start condition activates the state machine, which goes through the address and the command sequences before the data. As long as the state machine does 5.4 Flash Memory 225 not detect any stop condition, it constantly traces the data states D7 to D0. However, when there is a stop condition, the state machine goes to the IDLE state and waits for another start condition to emerge. START = 0 IDLE START = 1 A6 A0 W ACK D7 D0 ACK STOP = 0 STOP = 1 Fig. 5.66 The state diagram for the simple I2C write (program) in Fig. 5.65 Even though this example only shows the fast write interface, it sets up a solid foundation of how to design any typical I2C interface between a bus master and a Flash memory. The first step of the design process is to create a rough interface block diagram showing all the major I/O ports between the Flash memory and the I2C bus as shown in Fig. 5.67. For the fast write sequence, the address and data packets are serially transferred to the interface through the SDA port. However, the Flash memory needs the address and data fields all at once. Therefore, the write operation requires the interface to perform serial-to-parallel conversion of incoming data. The interface also needs to produce two control signals, EN and WE, for the fast write sequence, and the control signal, EnDataOut, for writing an eight-bit data to a designated Flash memory address. 226 5 16 SDA Memory Circuits and Systems Addr [15:0] Flash Fast Write I/F EnDataOut DataI/O [7:0] SCL EN 8 I/O [7:0] WE Fig. 5.67 Simplified page diagram of the I2C fast write (program) interface Figure 5.68 shows the architectural block diagram of the Flash memory interface for the fast write operation. As mentioned earlier when designing SRAM and SDRAM memory interfaces, creating a complete data-path for an interface is not a single-step process. The design methodology requires building a simple data-path with all of its functional units and a corresponding timing diagram showing the flow of data in each clock cycle, the start and stop conditions, address and data formations. However, as more detail is added to the architecture, the initial timing diagram also becomes more complex to match the architecture. Figures 5.69, 5.70 and 5.71 show a set of timing diagrams related to the architecture in Fig. 5.68. These diagrams describe the start and stop conditions, preamble sequence, address and data formations, repacking and delivery of serial address and data in a systematic manner. Once the cycle-by-cycle nature of address and data entries are accurately described in the timing diagram, the control signals responsible for routing the address and data can be added to the diagram. The final step of the design process is to assign distinct states to each clock cycle in the timing diagram that contains different sets of control signals in order to generate a Moore-type state machine. To start, we need to include four functional units in Fig. 5.68 to be able to handle a simple fast write operation. The first functional unit is an eight-bit shift register whose sole purpose is to convert the incoming serial data from the SDA port into a parallel form. If the fast-write process requires an authentication step prior to data exchange, the first eight-bit packet coming to this interface must be delivered to the device ID register, which is considered the second functional unit. The second and the third eight-bit data packets arriving at the interface belong to the most and the least significant bytes of the 16-bit starting Flash memory address, respectively, and they are stored in the address counter. The address counter, which constitutes the third functional unit, uses this initial address to generate subsequent addresses for programming the Flash memory. All eight-bit data that follows the address entry is routed directly to the data port of the Flash memory. There are also several fixed-value registers connected to the inputs of the address and data MUXes in Fig. 5.68. These registers contain 5.4 Flash Memory 227 the preamble data for setting and resetting the fast write modes for the Flash memory prior to address and data sequences. The write controller, which is considered to be the fourth functional unit, generates all the control signals necessary for storing data, incrementing the address, and routing the address and data to the output ports of the interface. The host processor delivers all address, control and data signals to the interface at the negative edge of the SCL, which requires all the registers to operate at the positive edge of SCL in Fig. 5.68. shift 7 0 Shift Reg 8 MSB SCL SDA Detector SDA START STOP EnSDAOut SCL 15 0 shiftRegOut LoadAddrLSB Address Counter LoadAddrMSB IncrAddr SCL AddrRegOut 0 Device ID + W 15 0 SCL 16 0x5555 1 LoadDevID 15 0 16 selAAAA sel5555 selAddr 0 8 0xAA 7 0 7 2 0 8 0xB0 7 0 0 8 0 selAux EnDataOut 8 5 8 6 SCL Fig. 5.68 I2C fast write (program) interface data-path selAA selData 1 sel55 SCLAux selB0 SCL selC0 0 selE0 SCLMaster 8 I/O[7:0] DataI/O [7:0] 4 0xD0 7 3 8 0xC0 7 1 8 0x55 0xE0 EN WE 2 0 7 Data MUX shift LoadDevID LoadAddrLSB LoadAddrMSB IncrAddr sel5555 selAAAA selAddr selAA sel55 selB0 selC0 selD0 selE0 selData EnDataOut EnSDAOut selD0 SCL Write Controller Addr[15:0] SCL STOP W START 0xAAAA Address MUX 16 0 7 228 5 Memory Circuits and Systems The START condition in Fig. 5.69 is produced by the bus master in cycle 1 by lowering the SDA signal to logic 0 while keeping the SCL signal at logic 1. Once the START condition is detected, the serial data on the SDA port is transferred to an eight-bit shift register which converts this data into a parallel form before sending it to different registers in Fig. 5.68. In clock cycles 2 to 8, the seven-bit Flash memory ID is loaded to the shift register starting from the most significant bit if device authentication is required prior to data transmission. In cycle 9, the bus master sends the write bit, W, stored in the shift register. In cycle 10, a number of events take place simultaneously. First, the write bit at the least significant bit position of the shift register activates the write controller. Second, the device ID and the write bit are transferred from the shift register to a special device ID register. Third, the Flash memory interface produces the first acknowledge signal, ACK, by EnSDAOut = 1, thus lowering the SDA bus to logic 0. Finally, the interface sends the first preamble which consists of the address, 0x5555, and the data, 0xAA, to the Flash memory and lowers EN and WE to logic 0 as the first step of the fast write set. In cycle 11, the most significant bit of the 16-bit initial Flash memory address, Add15, is received from the SDA bus and stored in the shift register. This cycle is also considered a hold period for the EN and WE signals. In cycle 12, the second most significant address bit, Add14, is stored in the shift register. In this cycle, the second preamble that contains the address, 0xAAAA, and the data, 0x55, are sent to the Flash memory as the second step of the fast write set. In cycle 14, the third address and command preamble, 0x5555 and 0xB0, are sent to the Flash memory, completing the fast write set sequence. The fast write sequence starts at cycle 16 where the fast write command, 0xC0, is sent to the Flash memory. In cycle 19, the most significant byte of the 16-bit starting Flash memory address, StAddMSB, is transferred from the shift register to the address register which resides inside the address counter. In this cycle, the interface also generates the second ACK signal by EnSDAOut = 1. From cycles 20 to 27 in Fig. 5.70, the least significant byte of the starting Flash address, StAddLSB, is received by the shift register. In cycle 28, this byte is transferred to the least significant byte of the address register in order to form the 16-bit starting Flash address. In this cycle, the interface generates the third ACK signal. From cycles 29 to 36, the first set of data bits starting from the most significant bit, DF7, to the least significant bit, DF0, are received by the shift register. In cycle 37, the first eight-bit data packet, Data0, is transferred to the Flash memory through its bidirectional I/O port. The tri-state buffers in Fig. 5.68 need to be enabled by the control signal, EnDataOut, to be able write this data packet to the Flash memory. Cycles 38 to 45 in Fig. 5.71 are used to store the second eight-bit data packet in the shift register. Cycle 46 transfers this data packet, Data1, to the I/O port and generates an ACK signal for receiving the second data byte from the bus master. If the STOP condition is detected during the next clock cycle, the fast write process halts. The write controller goes into the fast write reset mode and asynchronously produces selAux = 1 to engage the auxiliary clock, SCLAux, instead of using the main SCL clock, SCLMaster, generated by the bus SDA shiftRegOut Addr 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Add9 Add8 19 START DAdd6 DAdd5 DAdd4 DAdd3 DAdd2 DAdd1 DAdd0 W ACK Add15 DevID+W Add14 Add13 Add12 Add11 Add10 0x5555 0xAAAA HOLD 0x5555 HOLD 0xXXXX DevID HOLD ACK StAddMSB 5.4 Flash Memory 1 SCL EN WE I/O[7:0] 0xAA 0x55 0xB0 0xC0 shift EnSDAOut LoadDevID LoadAddMSB LoadAddLSB IncrAddr sel5555 selAAAA selAddr selB0 selC0 selD0 selE0 sel55 selAA selData EnDataOut selAux 229 Fig. 5.69 I2C fast write (program) set sequence with device ID and memory address 230 20 21 Add7 Add6 22 23 24 25 26 27 Add1 Add0 28 29 30 31 32 33 34 35 36 37 ACK DF7 DF6 DF5 DF4 DF3 DF2 DF1 DF0 ACK 38 SCL SDA D7 StAddLSB shiftRegOut Data0 Addr StAdd EN WE I/O[7:0] Data0 shift EnSDAOut LoadDevID LoadAddMSB LoadAddLSB IncrAddr sel5555 selAAAA selAddr selB0 selC0 sel55 selAA selData EnDataOut selAux Fig. 5.70 I2C fast write (program) sequence Memory Circuits and Systems selE0 5 selD0 40 41 42 43 44 45 46 47 48 49 50 STOP SDA shiftRegOut Addr D6 D5 D4 D3 D2 D1 ACK D0 Data1 StAdd+1 HOLD 0xXXXX HOLD 51 52 53 54 55 56 57 5.4 Flash Memory 39 SCL 0xXXXX EN WE I/O[7:0] Data1 0xD0 0xE0 shift EnSDAOut LoadDevID LoadAddMSB LoadAddLSB IncrAddr sel5555 selAAAA selAddr selB0 selC0 selD0 selE0 sel55 selAA selData EnDataOut selAux 231 Fig. 5.71 I2C fast write (program) reset sequence 232 5 Memory Circuits and Systems master. This is because the Flash memory needs two more preambles that contain 0xD0 and 0xE0 commands to complete the fast write reset sequence. Therefore, starting from cycle 48, SCL resumes with three more cycles. In cycle 48, the first preamble that contains 0xD0, and in cycle 50 the second preamble that contains 0xE0 are sent to the Flash memory by setting selD0 and then selE0 to logic 1, respectively. In the next cycle, selAux becomes logic 0, and SCL switches back to the SCLMaster input which permanently stays at logic 0. The Moore machine in Fig. 5.72 implements the write controller in Fig. 5.68. At the onset of the START condition, the controller wakes up and goes into the device ID retrieval mode. From cycles 2 to 8 in Fig. 5.69, the serial device ID is received by the shift register on the SDA bus. These cycles correspond to the states DAdd6 to DAdd0 in Fig. 5.72 where the shift signal is constantly kept at logic 1, and writing data to the Flash memory is disabled. In cycle 9, the write bit is also stored in the shift register. This corresponds to the W state in the state machine. In cycle 10, numerous events take place simultaneously. First, shifting serial data into the shift register stops by shift = 0. Second, the seven-bit device ID and the write bit are delivered to the device ID register by LoadDevID = 1. Third, the first address and data preamble, 0x5555 and 0xAA, is delivered to the Flash memory through port 1 of the address MUX by sel5555 = 1 and port 1 of the data MUX by selAA = 1. Fourth, the control signals, EN and WE, are lowered to logic 0 in order to write the address and data preamble to the Flash memory. Finally, an ACK signal is generated by EnSDAOut = 1. This cycle corresponds to the DevID ACK state of the write controller. In cycle 11, shifting data resumes, and the shift register receives the most significant bit of the initial Flash address, Add15, while in the Add15 state. In cycle 12, which corresponds to the Add14 state, the second most significant address bit, Add14, is latched in the shift register by shift = 1. In the same cycle, the second address and data preamble, 0xAAAA and 0x55, is delivered to the Flash memory through port 2 of the address MUX by selAAAA = 1 and port 2 of the data MUX by sel55 = 1. The control signals, EN and WE, are also lowered to logic 0 in order to write this preamble to the Flash memory. In cycle 13, Add13 is stored in the shift register. This cycle corresponds to the Add13 state. In cycle 14, the third address and data preamble, 0x5555 and 0xB0, is written to the Flash memory through port 1 of the address MUX by sel5555 = 1 and port 3 of the data MUX by selB0 = 1. In this cycle, the control signals, EN and WE, are lowered to logic 0 in order to write the last address and data preambles. This cycle corresponds to the Add12 state. Cycle 15 designates the end of the fast write set cycle, and corresponds to the Add11 state when the address bit, Add11, is loaded to the shift register. 5.4 Flash Memory 233 START = 1 shift = 1 EN = 1 WE = 1 shift = 1 EN = 1 WE = 1 shift = 0 EnSDAOut = 1 EnDataOut = 1 LoadDevID = 1 sel5555 = 1 selAA = 1 EN = 0 WE = 0 shift = 1 EN = 1 WE = 1 shift = 1 EnDataOut = 1 sel55 = 1 selAAAA = 1 EN = 0 WE = 0 shift = 1 EN = 1 WE = 1 shift = 1 EnDataOut = 1 selB0 = 1 sel5555 = 1 EN = 0 WE = 0 shift = 1 EN = 1 WE = 1 shift = 1 EnDataOut = 1 selC0 = 1 EN = 0 WE = 0 Add7 shift = 1 EN = 1 WE = 1 Add0 shift = 1 EN = 1 WE = 1 DAdd6 shift = 0 EnSDAOut = 1 LoadAddLSB = 1 EN = 1 WE = 1 DAdd0 AddLSB ACK W DF7 shift = 1 EN = 1 WE = 1 DF0 shift = 1 EN = 1 WE = 1 DevID ACK Add15 Add14 STOP = 0 Add13 Add12 Add11 shift = 0 EnSDAOut = 1 selAddr = 1 selData = 1 EnDataOut = 1 EN = 0 WE = 0 0xD0 HOLD Add9 shift = 1 EN = 1 WE = 1 Add8 D7 shift = 1 EN = 1 WE = 1 D0 shift = 1 IncrAddr = 1 EN = 1 WE = 1 Data ACK Add10 shift = 1 EN = 1 WE = 1 shift = 0 EnSDAOut = 1 LoadAddMSB = 1 EN = 1 WE = 1 START = 0 STOP = 1 shift = 1 EN = 1 WE = 1 IDLE 0xE0 AddMSB ACK Fig. 5.72 I2C fast write (program) interface controller shift = 0 EnDataOut = 1 selD0 = 1 selAux = 1 EN = 0 WE = 0 shift = 0 selAux = 1 EN = 1 WE = 1 shift = 0 EnDataOut = 1 selE0 = 1 selAux = 1 EN = 0 WE = 0 234 5 Memory Circuits and Systems Cycle 16 enters the fast write command mode and writes the address and data preambles, 0xXXXX and 0xC0, through port 4 of the data MUX by selC0 = 1. In this cycle, EN and WE signals are lowered to logic 0 to accommodate the write operation, and Add10 is latched in the shift register. This clock cycle corresponds to the Add10 state. Storing the higher byte of the initial Flash address becomes complete by the end of cycle 18. In cycle 19, the higher byte of the initial address is transferred to the address register by LoadAddMSB = 1, and an acknowledge signal is generated by EnSDAOut = 1. This cycle corresponds to the AddMSB ACK state in the state diagram. Similar events take place when storing the least significant byte of the starting address in the shift register. These states are marked as Add7 to Add0 in the state diagram, and correspond to the cycles 20 though 27, respectively. The cycle 28, which corresponds to the AddLSB ACK state, generates the third acknowledge for the bus master by EnSDAOut = 1, and transfers the least significant byte of the starting Flash memory address to the address register by LoadAddLSB = 1. From cycles 29 to 36, the first set of data bits are delivered to the shift register starting from the most significant data bit, DF7. This sequence is shown as the states DF7 to DF0 in the state diagram. In cycle 37, an acknowledgement is sent to the bus master by EnSDAOut = 1 shown as the Data ACK state. During this period, the initial 16-bit address and eight-bit data are delivered to the Flash memory through port 0 of the address MUX by selAddr = 1 and port 0 of the data MUX by selData = 1. Tri-state buffer at the I/O port is also enabled by EnDataOut = 1. The second data byte is received during cycles 38 to 45, which correspond to the states D7 to D0, respectively. Cycle 45 is also the cycle to increment the Flash memory address by issuing IncrAddr = 1. In Cycle 46, the write controller goes into the Data ACK state once again and issues an acknowledgement for receiving the second data packet by EnSDAOut = 1. In this cycle, the second data packet is delivered to the incremented Flash memory address, StAdd + 1, by selAddr = 1, selData = 1 and EnDataOut = 1. As long as the STOP condition is not detected, data packets are delivered to the Flash memory at each incremented address. However, if the bus master issues a STOP condition, the auxiliary SCL generator, SCLAux, is asynchronously enabled within the same cycle by selAux = 1. The write controller goes into the fast write reset mode in the next clock cycle and keeps the auxiliary SCL generator enabled by selAux = 1. For the next three clock cycles, the 0xD0 and 0xE0 command codes, corresponding to the 0xD0 and 0xE0 states in the state diagram, are delivered to the Flash memory through port 5 of the data MUX by selD0 = 1 and port 6 of the data MUX by selE0 = 1. 5.4 Flash Memory 235 Design Example 2: I2C Read Interface for Flash Memory The following design example constructs only the I2C read interface for a Flash memory that has parallel address and data ports shown in Fig. 5.44 using a modified seven-bit address mode. No other modes are included in this design except the read. The timing diagram for I2C read sequence is given in Fig. 5.73 where each eight-bit data packet is serially read from a slave after issuing an initial seven-bit address. The address sent by the bus master requires an acknowledgment (ACK) from the slave. In contrast, data packets sent by the slave require the master’s acknowledgment. If the bus master chooses not to acknowledge the receipt of data (NACK), the data transfer stops in the next cycle. Figure 5.74 shows the sequence of events taking place in Fig. 5.73 in the form of a state diagram where the logic level in Master ACK/NACK state determines the continuation or the end of the data transfer. A6 A5 A0 R ACK D7 D6 D0 NACK SCL Master Master sends sends SDA A6 START I2C reads A5 I2C reads Master Master I2C sends sends ACK A0 I2C reads R=1 Master Master sends sends ACK D7 I2C Master I2C reads reads reads D6 I 2C reads Master Master sends sends D0 I2C reads Master NACK I2C reads STOP Fig. 5.73 A simple timing diagram for the I2C read operation using seven-bit address mode The Flash memory read sequence described in Fig. 5.75 is a four-cycle process as mentioned earlier in Fig. 5.50. The bus master sends the address and data preambles, 0x5555/0xAA and 0xAAAA/0x55, in the first two cycles. This is followed by the 0x5555/0x00 preamble containing the read command code in the third cycle. All three cycles can be considered a preparation period for a read operation which takes place in the fourth cycle. Following the read operation, the address is incremented either by one or a predefined value according to the Flash memory address generation protocol before the next data read sequence takes place. To read data from the Flash memory, the address and command entries are serially sent by the host processor to the I2C interface through the SDA port. The Flash memory requires a 236 5 START = 0 Memory Circuits and Systems IDLE START = 1 A6 A0 R Slave ACK D7 D0 SDA = 0 Master ACK/NACK SDA = 1 Fig. 5.74 The state diagram for the simple I2C read operation in Fig. 5.73 16-bit address all at once in order to read an eight-bit data, and this necessitates an interface to perform both serial-to-parallel and parallel-to serial conversions. The interface has to produce three active-low control signals, EN, WE and RE, to be able to read data from the Flash memory. It also needs to produce the control signals, EnDataIn and EnDataOut, to route the incoming and outgoing data. 5.4 Flash Memory 237 Start 0x5555/0xAA 0xAAAA/0x55 Read preamble 0x5555/0x00 Read Addr/ Read Data Addr = Addr + 1 NO Last Addr YES Complete Fig. 5.75 Flow chart for the read sequence Figure 5.76 shows the architectural diagram of the Flash memory read interface. Figures 5.77, 5.78 and 5.79 show the timing diagrams related to this architecture. These waveforms describe a complete picture of the preamble formation, device ID creation, address generation and serializing the read data from the Flash memory. The architecture in Fig. 5.76 still contains four functional units as in the fast write (program) data-path. The first functional unit is an eight-bit shift register which identifies the serial address, command and data boundaries, and converts the serial data on the SDA bus into a parallel form and the parallel data from the Flash memory into a serial form. The second functional unit stores the device ID if the Flash memory requires an identification process prior to data exchange, and the command bit. The third unit stores the initial 16-bit Flash memory address and generates the subsequent memory addresses using an up-counter. The fourth unit is the read controller, which is responsible for storing the device ID, the command bit, forming and incrementing the initial address, and handling the proper data-flow that complies with the timing diagrams in Figs. 5.77, 5.78 and 5.79. There are also several fixed-value registers, each of which contains the address and data preambles for retrieval of data from the Flash memory. The host processor dispatches all address and 238 5 Memory Circuits and Systems SDAIn LoadShift ShiftOut ShiftIn control signals at the negative edge of the SCL clock in order to read data packets from the Flash memory, and therefore it requires all the registers in Fig. 5.76 to operate at the positive edge of the SCL clock. 7 0 SDAOut Shift Reg 8 8 SCL ShiftRegOut SDA ShiftRegIn SDA 7 EnSDAOut MasterAck (external from the Master) 0 LoadDevID Device ID + R 8 SCL SCL START Detector SDA STOP 0 7 LoadAddrMSB Addr MSB 8 +1 8 SCL 8 0 1 Addr Reg MUX IncrAddr selStartAddr 2 initAddr Addr Reg 0 SCL 16 0 AddrCountOut selStartAddr 15 0 0x5555 15 0 0xAAAA 16 16 1 2 0 7 0x55 0 0 0xAA RE selAAAA sel5555 selAddr SCL 7 EN WE 1 0 1 0 7 Data MUX SCL Read Controller ShiftIn ShiftOut LoadShift LoadDevID LoadAddrLSB IncrAddr selStartAddr selAddr sel5555 selAAAA sel55 selAA sel00 EnDataIn EnDataOut SDAIn SDAOut EnSDAOut 16 15 Address MUX STOP R START 16 I/O[7:0] 2 0x00 EnDataIn sel00 selAA sel55 SCL Fig. 5.76 I2C read interface data-path EnDataOut Addr[15:0] 2 3 4 5 6 7 8 START DAdd6 SDA DAdd5 DAdd4 DAdd3 DAdd2 DAdd1 DAdd0 R 9 Slave ACK 10 Add15 11 Add14 12 Add13 13 Add12 14 Add11 15 Add10 16 17 18 Add9 Add8 Slave ACK DevID+R ShiftRegOut AddMSB Start Read Preamble ShiftRegIn Addr 0x5555 HOLD 0xAAAA HOLD 5.4 Flash Memory 1 SCL 0x5555 AddrCountOut 0xAA I/O[7:0] 0x55 0x00 EN WE HIGH RE ShiftIn ShiftOut LoadShift LoadDevID LoadAddMSB IncrAddr selStartAddr selAddr sel5555 selAAAA sel55 selAA sel00 EnDataOut EnDataIn SDAIn SDAOut Fig. 5.77 I2C read sequence with device ID and the LSB of starting memory address 239 EnSDAOut 20 21 22 Add7 Add6 Add5 Add4 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Add3 Add2 Add1 Add0 Slave ACK D7 D6 D5 D4 D3 D2 D1 D0 Master ACK 37 SDA ShiftRegOut ShiftRegIn Addr D7 AddLSB Data0 Data1 0x5555 StartAdd AddrCountOut I/O[7:0] 240 19 SCL HOLD 0xAAAA HOLD 0x5555 StartAdd Data0 HOLD StAdd+1 StAdd+1 0xAA 0x55 0x00 Data1 EN WE RE ShiftIn ShiftOut LoadShift LoadDevID LoadAddMSB IncrAddr selStartAddr selAddr sel5555 selAA sel00 EnDataOut EnDataIn SDAIn SDAOut EnSDAOut Fig. 5.78 I2C read sequence with the MSB of starting memory address and data formation Memory Circuits and Systems sel55 5 selAAAA 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Master ACK D7 D6 D5 D4 D3 D2 D1 D0 Master NACK 0x5555 HOLD 0xAAAA HOLD 0x5555 HOLD StAdd+3 55 SDA D6 D5 D4 D3 D2 D1 D0 STOP ShiftRegOut ShiftRegIn Addr Data2 0x5555 HOLD 0xAAAA HOLD 0x5555 StAdd+2 StAdd+3 StAdd+2 AddrCountOut I/O[7:0] HOLD 0xAA 0x55 0x00 Data2 5.4 Flash Memory 38 SCL 0xAA 0x55 0x00 EN WE RE ShiftIn ShiftOut LoadShift LoadDevID LoadAddMSB IncrAddr selStartAddr selAddr sel5555 selAAAA sel55 selAA sel00 EnDataOut EnDataIn SDAIn SDAOut Fig. 5.79 I2C read sequence emphasizing the end of read cycle 241 EnSDAOut 242 5 Memory Circuits and Systems Figures 5.77, 5.78 and 5.79 describe the complete picture of reading data from the Flash memory. Figure 5.77 shows the device ID and the command bit formations followed by the generation of the most significant byte of the initial Flash memory address. Figure 5.78 describes the formation of the least significant byte of the initial Flash memory address and the first data byte read from the memory. Figure 5.79 includes two additional bytes of data sent to the bus master and the termination of data transfer. The bus master initiates the data transfer by issuing the START condition in Fig. 5.77. Between cycles 1 and 8, the bus master sends the device ID followed by the read command on the SDA bus, both of which are serially loaded to an eight-bit shift register by ShiftIn = 1. These cycles are represented by the states DAdd6 to DAdd0 followed by the R state, which corresponds to the read command, in the state diagram in Fig. 5.80. In cycle 9, the Flash memory interface responds to the bus master with an acknowledgement by issuing EnSDAOut = 1, but pauses shifting data by ShiftIn = 0. In the same cycle, the interface also transfers data from the shift register to the device ID register by LoadDevID = 1. This cycle corresponds to the first slave-acknowledgement state, DevID SACK, in Fig. 5.80. In cycle 10, the interface starts sending the preamble to the Flash memory for a read operation. In this cycle, the first address and data preamble, 0x5555/0xAA, is fetched from the fixed-data registers, 0x5555 and 0xAA in Fig. 5.76. This preamble is subsequently sent to the address port of the device through port 1 of the address MUX by sel5555 = 1, and to the data port of the device through port 1 of the data MUX by selAA = 1. In this cycle, the bus master also sends the most significant bit of the 16-bit Flash memory address, Add15, on the SDA bus. In cycle 12, the interface sends the second address and data preamble, 0xAAAA/0x55, through port 2 of the address MUX by selAAAA = 1 and port 0 of the data MUX by sel55 = 1. In cycle 14, the last address and data preamble, 0x5555/0x00, containing the read command, is sent to the Flash memory address and data ports. The cycles 10 to 17 correspond to storing the most significant byte of the starting Flash memory address, Add15 to Add8, in the shift register by ShiftIn = 1. In cycle 18, the interface sends an acknowledgement to the bus master by EnSDAOut = 1 to indicate that it has received the higher byte of the starting Flash memory address. Within the same cycle, this higher byte is stored in the 16-bit address register that resides in the address counter by LoadAddMSB = 1. This cycle represents the second slave-acknowledgement state, AddLSB SACK, in Fig. 5.80. In cycles 19 to 26, the bus master sends the least significant byte of the starting Flash memory address by ShiftIn = 1. These cycles correspond to the states Add7 to Add0 in Fig. 5.80, respectively. Cycle 27 constitutes the third slave-acknowledgement state, AddLSB SACK, in Fig. 5.80. There are numerous events that take place during this clock cycle, and they are all inter-related. The first event concatenates the least significant byte of the starting Flash memory address in the shift register with the most significant byte in the Addr MSB register to form the complete 16-bit starting Flash memory address. This address is subsequently sent to the Addr[15:0] terminal of the Flash memory through port 1 of the address register MUX by selStartAddr = 1 and port 0 of the address MUX by selAddr = 1. 5.4 Flash Memory 243 START = 1 ShiftIn = 1 SDAIn = 1 EN = 1 WE = 1 RE = 1 IDLE ShiftIn = 1 SDAIn = 1 EN = 1 WE = 1 RE = 1 Add7 START = 0 DAdd6 ShiftIn = 1 SDAIn = 1 EN = 1 WE = 1 RE = 1 Add0 ShiftIn = 1 SDAIn = 1 EN = 1 WE = 1 RE = 1 ShiftIn = 1 SDAIn = 1 EN = 1 WE = 1 RE = 1 R EnSDAOut = 1 LoadDevID = 1 EN = 1 ShiftIn = 1 WE = 1 sel5555 = 1 RE = 1 selAA = 1 EnDataOut = 1 SDAIn = 1 EN = 0 WE = 0 ShiftIn = 1 RE = 1 SDAIn = 1 ShiftIn = 1 selAAAA = 1 sel55 = 1 EnDataOut = 1 SDAIn = 1 EN = 0 WE = 0 RE = 1 ShiftIn = 1 sel5555 = 1 sel00 = 1 EnDataOut = 1 SDAIn = 1 EN = 0 WE = 0 RE = 1 ShiftIn = 1 SDAIn = 1 EN = 1 WE = 1 RE = 1 LoadAddMSB = 1 EnSDAOut = 1 EN = 1 WE = 1 RE = 1 AddLSB SACK DAdd0 EN = 1 WE = 1 RE = 1 ShiftIn = 1 SDAIn = 1 EN = 1 WE = 1 RE = 1 ShiftIn = 1 SDAIn = 1 EN = 1 WE = 1 RE = 1 D7 DevID SACK D6 Add15 D5 Add14 D4 Add13 D2 Add12 D2 Add11 D1 Add10 MACK Add8 AddMSB SACK Fig. 5.80 I2C read interface controller 1 LoadShift = 1 selAddr = 1 EnDataIn = 1 If SDA = 1 EN = 0 WE = 1 RE = 0 ShiftOut = 1 SDAOut = 1 EN = 1 WE = 1 RE = 1 ShiftOut = 1 sel5555 = 1 selAA = 1 EnDataOut = 1 SDAOut = 1 ShiftOut = 1 EN = 0 SDAOut = 1 WE = 0 EN = 1 RE = 1 WE = 1 ShiftOut = 1 RE = 1 selAAAA = 1 sel55 = 1 EnDataOut = 1 SDAOut = 1 EN = 0 ShiftOut = 1 WE = 0 SDAOut = 1 RE = 1 EN = 1 WE = 1 ShiftOut = 1 RE = 1 sel5555 = 1 sel00 = 1 EnDataOut = 1 SDAOut = 1 EN = 0 IncrAddr = 1 WE = 0 SDAOut = 1 RE = 1 EN = 1 D0 = ck rA ste a M Add9 ShiftIn = 1 SDAIn = 1 EN = 1 WE = 1 RE = 1 ShiftOut = 1 SDAOut = 1 EN = 1 WE = 1 RE = 1 LoadShift = 1 selStartAddr = 1 selAddr = 1 EnDataIn = 1 EnSDAOut = 1 EN = 0 WE = 1 RE = 0 WE = 1 RE = 1 Ma ste rA ck =0 MNACK LoadShift = 0 selAddr = 0 EnDataIn = 0 If SDA = 1 EN = 1 WE = 1 RE = 1 244 5 Memory Circuits and Systems The second event lowers EN and RE control signals to logic 0 and produces EnDataIn = 1 in order to fetch the first data byte from the Flash memory, Data0, since the read preamble has already been sent between cycles 10 and 14. The third event stores Data0 in the shift register through its ShiftRegIn port by LoadShift = 1. Finally, the last event sends an acknowledgement signal to the bus master by EnSDAOut = 1, signifying the least significant byte of the starting address has been received so that the bus master can start receiving serial data on the SDA bus in the next cycle. In cycle 28, the starting address, which could not be registered due to time limitations in the earlier cycle, is now registered in the address register, and the address counter output, AddrCountOut, becomes equal to the starting address, StartAdd. In the same cycle, the most significant bit of Data0, D7, becomes available on the SDA bus by SDAOut = 1. Starting from cycle 30, the read preamble associated with the second data is sent to the Flash memory. The read preamble could have been issued as early as cycle 28 or 29 since the address counter still held StartAdd at the AddrCountOut node during these periods. In cycle 35, the interface increments the starting address by IncrAddr = 1 and uses port 2 of the address register MUX to feed through the result. Until the beginning of cycle 36, all eight bits of Data0, D7 to D0, are serially sent to the bus master by SDAOut = 1. Therefore, cycles 28 to 35 correspond to the states D7 to D0 in Fig. 5.80, respectively. In cycle 36, while the bus master acknowledges the reception of Data0 by MasterAck = 1, and thereby lowering the SDA bus to logic 0, the interface sends the incremented Flash memory address, StAdd + 1, to the Addr[15:0] terminal through port 0 of the address counter MUX by selAddr = 1. In the same cycle, the interface lowers EN and RE signals to logic 0, fetches Data1 from the I/O port of the Flash memory by EnDataIn = 1, and stores this value in the shift register by LoadShift = 1. This particular cycle corresponds to the master-acknowledge state, MACK, in Fig. 5.80, where the state machine continues fetching data from the Flash memory. Cycles 37 to 44 and cycles 46 to 53 contain identical events to the ones between cycles 28 and 35. They both correspond to the states D7 to D0 in Fig. 5.80. In cycle 54, the SDA bus transitions to logic 1 because the bus master decides not to issue any more acknowledgements by MasterAck = 0. Even though the current address increments at this point, the interface neither lowers the EN nor lowers the RE signal to logic 0 as shown by the master-no-acknowledge state, MNACK. Therefore, no data reading takes place from the Flash memory. In the next cycle, the bus master terminates the SCL activity and issues the STOP condition, signifying the end of data transfer. 5.4 Flash Memory 245 Design Example 3: I2C Page Erase Interface for Flash Memory The following design example constructs only the I2C page erase interface for a Flash memory that has parallel address and data ports as shown in Fig. 5.44. Using a modified seven-bit address mode. No other Flash memory mode is implemented in this design except the erase. The Flash memory page erase is a six-cycle sequence as described earlier in Fig. 5.50. The flow chart for this process is shown in Fig. 5.81. In the first five cycles, the bus master sends fixed address/data combinations to the Flash memory as a preamble to prepare the memory to erase a block of data at a specified memory location. The page erase command is the 0x50 entry in the third cycle followed by the page address and the second erase command, 0x70, in the sixth cycle to initiate the process. Start 0x5555/0xAA 0xAAAA/0x55 0x5555/0x50 0x5555/0xAA 0xAAAA/0x55 Page Addr/ 0x70 Complete Fig. 5.81 Flow chart for page erase Page Erase preamble 246 5 Memory Circuits and Systems Figure 5.82 shows the data-path for the I2C page erase interface. The shift register acquires the device ID (if the Flash memory requires any type of device authentication prior to page erase) and the page address from the SDA bus, and transfers them to the device ID register and the page address register, respectively. There are also address and data registers that store only the fixed values, and they are routed to the address and data ports of the Flash memory in order to produce the correct preamble and page erase commands in Fig. 5.81. shift 7 0 Shift Reg 8 LoadDevID SCL SDA START Detector SDA STOP EnSDAOut SCL 0 7 0 7 15 0 Page Address Reg CommandOut Command Reg 0 15 SCL 16 0 0x5555 15 0 0xAAAA 16 1 16 Address MUX LoadCom shiftRegOut SCL LoadBlkLSB LoadBlkMSB Device ID + W Addr[15:0] 2 Encoder 0 0x55 0 0x50 7 0 Fig. 5.82 I2C page erase interface data-path 8 2 0x70 WE 1 8 EnDataOut 8 8 I/O[7:0] DataI/O [7:0] 3 SCL selAA 7 8 Data MUX 0 sel55 SCL 7 8 sel70 shift LoadDevID LoadBlkLSB LoadBlkMSB LoadCom sel5555 selAAAA selBlkAddr selAA sel55 sel50 sel70 EnDataOut EnSDAOut 0 0xAA sel50 7 Block Erase Controller EN selAAAA sel5555 selBlkAddr STOP EraseCom START SCL 5.4 Flash Memory 247 The page erase process is described in the timing diagrams of Figs. 5.83, 5.84 and 5.85. The process starts with the bus master generating the START condition in Fig. 5.83. In cycles 2 to 9, the bus master sends the seven-bit device ID and the write bit, starting with the most significant device ID bit, DAdd6. Even though the write bit is considered a command bit, it does not have any significance in the page erase preamble. The bus master sends this bit only to comply with the I2C protocol. All these bits are temporarily stored in the shift register and correspond to the states DAdd6 to W in the state diagram in Fig. 5.86. In cycle 10, the interface generates an acknowledgement, ACK, to signify that it has received the first eight bits from the bus master by EnSDAOut = 1, and transfers the device ID stored in the shift register to the device ID register by LoadDevID = 1. This cycle corresponds to the DevID ACK state in Fig. 5.86. From cycles 11 to 18, which correspond to the states Add15 to Add8 in the state diagram, the bus master sends the most significant byte of the Flash memory page address to the interface. These bits are received by the shift register and immediately transferred to the page address register in cycle 19 by LoadBlkMSB = 1. In this cycle, the interface also sends a second acknowledgment to the bus master by EnSDAOut = 1, which is represented by the AddMSB ACK state in the state diagram. From cycles 20 to 27, the interface receives the least significant byte of the page address. It stores this byte in cycle 28 by LoadBlkLSB = 1, and sends a third acknowledgement to the bus master by EnSDAOut = 1. These events are shown by the states Add7 to Add0 and the state AddLSB ACK in the state diagram, respectively. Starting in cycle 29, the complete page address becomes available at the Addr[15:0] terminal in Fig. 5.82 even though the page erase process has not been initiated. This cycle is also the starting point for the bus master to send the erase command, 0x50, to the Flash memory interface. Without this step, the interface will not be able to recognize if the ongoing process is actually about erasing a block of data. From cycle 29 to 36 that correspond to the states 0x50-0 to 0x50-7, the interface receives all eight bits of the command code, 0x50, in the shift register. Then in cycle 37, it generates the fourth acknowledgment by EnSDAOut = 1, and transfers the contents of the shift register, 0x50, to the command register by LoadCom = 1. Later on, the interface uses this value to be able to generate the correct preamble for the page erase operation. Cycle 37 corresponds to the 0x50 ACK state in the state diagram. While the bus master sends the second command code, 0x70, from cycles 38 to 45 to initiate the page erase, the interface, now aware of the page erase operation, sends the first address and data preamble, 0x5555/0xAA, to the Flash memory in cycle 39. In this cycle, the fixed register value, 0x5555, is routed through port 1 of the address MUX by sel5555 = 1. The fixed register data, 0xAA, is also sent to the I/O[7:0] port through port 0 of the data MUX by selAA = 1 and EnDataOut = 1. In cycle 41, the second address and data preamble, 0xAAAA/0x55, is sent. This is followed by sending the third preamble (including the first page erase command), 0x5555/0x50, in cycle 43, and then the fourth preamble, 0x5555/0xAA, in cycle 45. The interface pauses for one cycle after dispatching each address and data combination to comply with the Flash memory protocol of writing data. 248 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Add9 Add8 19 SCL START SDA DAdd6 DAdd5 DAdd4 DAdd0 W ACK Add15 Add14 DevID+W Add13 Add12 Add11 Add10 ACK PageMSB shiftRegOut CommandOut Addr HIGH EN HIGH WE I/O[7:0] shift EnSDAOut LoadDevID LoadBlkMSB LoadBlkLSB LoadCom sel5555 selAA sel55 sel50 sel70 EnDataOut Fig. 5.83 I2C page erase sequence with device ID and the LSB of page address Memory Circuits and Systems selBlkAddr 5 selAAAA 21 22 Add7 Add6 Add5 23 24 25 26 27 Add1 Add0 28 29 30 31 32 33 34 35 36 0 1 0 1 0 0 0 0 37 SDA ACK ACK PageLSB shiftRegOut 0x50 5.4 Flash Memory 20 SCL CommandOut Addr Page Address HIGH EN HIGH WE I/O[7:0] shift EnSDAOut LoadDevID LoadBlkMSB LoadBlkLSB LoadCom sel5555 selAAAA selBlkAddr selAA sel55 sel50 sel70 EnDataOut 249 Fig. 5.84 I2C page erase sequence with the MSB of page address and the erase command 39 40 41 42 43 44 45 0 0 46 47 48 49 X X X 50 250 38 SCL STOP 0 SDA 1 1 1 0 0 shiftRegOut 0X70 CommandOut Addr ACK 0X50 Page Address Start Page Erase Preamble 0x5555 hold 0xAAAA hold 0x5555 hold 0x5555 hold 0xAAAA hold Page Address Controller releases 0x70 as opposed to 0x60 (Chip Erase) EN WE I/O[7:0] 0xAA 0x55 0x50 0xAA 0x55 0x70 shift EnSDAOut LoadDevID LoadBlkMSB LoadBlkLSB LoadCom sel5555 selAA sel55 sel50 sel70 EnDataOut Fig. 5.85 I2C page erase preamble and the page erase command Memory Circuits and Systems selBlkAddr 5 selAAAA 5.4 Flash Memory 251 START = 0 START = 1 shift = 1 EN = 1 WE = 1 shift = 1 EN = 1 WE = 1 shift = 1 EN = 1 WE = 1 EnSDAOut = 1 LoadDevID = 1 EN = 1 WE = 1 shift = 1 EN = 1 WE = 1 DAdd6 DAdd0 W IDLE 0x50 0 0x50 7 0x50 ACK DevID ACK 0x70 0 Add15 0x70 1 0x70 2 shift = 1 EN = 1 WE = 1 EnSDAOut = 1 LoadBlkMSB = 1 EN = 1 WE = 1 shift = 1 EN = 1 WE = 1 Add8 0x70 3 AddMSB ACK 0x70 4 Add7 EnSDAOut = 1 LoadBlkLSB = 1 EN = 1 WE = 1 shift = 1 selBlkAddr = 1 EN = 1 WE = 1 Add0 0x70 7 AddLSB ACK 0x70 ACK DontCare 0 selAAAA = 1 sel55 = 1 EnDataOut = 1 EN = 0 WE = 0 shift = 1 selBlkAddr = 1 EN = 1 WE = 1 shift = 1 sel5555 = 1 sel50 = 1 EnDataOut = 1 EN = 0 WE = 0 shift = 1 selBlkAddr = 1 EN = 1 WE = 1 shift = 1 sel5555 = 1 selAA = 1 EnDataOut = 1 EN = 0 WE = 0 EnSDAOut = 1 selBlkAddr = 1 EN = 1 WE = 1 Fig. 5.86 I2C page erase interface controller selAAAA = 1 sel55 = 1 EnDataOut = 1 EN = 0 WE = 0 DontCare 1 selBlkAddr = 1 EN = 1 WE = 1 DontCare 2 selBlkAddr = 1 sel70 = 1 EnDataOut = 1 EN = 0 WE = 0 EnSDAOut = 1 LoadCom = 1 selBlkAddr = 1 EN = 1 SDA = 1 WE = 1 shift = 1 selBlkAddr = 1 EN = 1 WE = 1 shift = 1 sel5555 = 1 selAA = 1 EnDataOut = 1 EN = 0 shift = 1 WE = 0 selBlkAddr = 1 EN = 1 WE = 1 shift = 1 0x70 5 0x70 6 shift = 1 EN = 1 WE = 1 shift = 1 selBlkAddr = 1 EN = 1 WE = 1 SDA = 0 252 5 Memory Circuits and Systems Cycles 38 to 45 are represented by the states 0x70-0 to 0x70-7 in the state diagram, respectively. The interface sends the fifth acknowledgment to the bus master in cycle 46 by EnSDAOut = 1 while in the 0x70 ACK state. In cycle 47, the interface sends the fifth address and data preamble, 0xAAAA/0x55, and finally in cycle 49, it sends the page address with the second page erase command, 0x70, to erase the entire block of data. Cycles 47 to 49 are represented by the DontCare-0, DontCare-1 and DontCare-2 states in Fig. 5.86, respectively. An architecture combining the read and the fast write interfaces can be implemented by a data-path shown in Fig. 5.87. A shift register can be used to receive the incoming device address and command bit from the SDA bus, which is subsequently is stored in an auxiliary register as shown in this figure. The seven-bit device ID field can be used to activate one of the maximum 128 Flash memory chips. The command bit, R or W, is used to enable either the read interface or the fast write interface depending on its value. The Flash memory address residing in the shift register is then forwarded to the eight-bit shift register in either the read or the fast write interface to prepare the Flash memory for a data transfer. 7 0 SDA Shift Reg Shift Reg 1 8 7 R/W SCL SCL 0 6 Read I/F DeviceID EnFlash127 7 Decoder SCL EnReadIF EnFlash0 Shift Reg SCL Fast Write I/F EnWriteIF Fig. 5.87 I2C read and fast write (program) interface topologies The reader should be quite familiar with all three I2C interface designs shown above to be able to integrate them in one interface to achieve a complete design. 5.5 Serial Flash Memory 5.5 253 Serial Flash Memory Recent Flash memory chips already include I2C or SPI interfaces to interact with a host processor or another bus master. The user does not have to deal with preambles, waiting periods or other complexities of the memory, but simply write an I2C or SPI-compliant embedded program to initiate a read, write or erase operation with the Flash memory. This section examines the operation of a typical Flash memory with an SPI interface. Figure 5.88 shows the basic internal architecture of the Flash memory where an external active-low Slave Select control signal, SS, is applied to enable the memory. The clock is supplied through the SCK port. The serial data comes into the memory through the Serial-Data-In (SDI) port and departs from the Serial-Data-Out (SDO) port. Once a serial address is retrieved from the SPI bus, it is stored in the address register. The address decoder uses the contents of the address register to access the Flash memory core and read the data to an internal data buffer. The serial data is subsequently delivered to the bus master through the SDO port. If the operation is a write, the bus master sends serial data to the SDI port, which is then transferred to an internal data buffer, and subsequently to the memory core. Address Reg SS Address Decoder Flash Memory Core SPI Bus Interface Control Unit Data Buffer SCK SDI SDO Fig. 5.88 Serial Flash memory architecture with SPI interface Figure 5.89 describes a typical partitioning scheme of a 1 MB memory core that requires a 20-bit address for each byte of data. To be consistent with the E2PROM and Flash memory organizations discussed in previous sections, the entire memory block in this example is divided into sixteen 64 KB sectors. Each sector is subdivided into sixteen 4 KB blocks, and each block is further subdivided into 16 pages. Each page contains 256 bytes, any of which is accessible through the SPI bus. Figure 5.90 shows the detailed address mapping of Block 0 in Sector 0 to further illustrate the internal memory organization. 254 5 Block 0 –4KB Memory Circuits and Systems Block 0 –4KB Block 14 –4KB Block 0 –4KB Block 14 –4KB Block 14 –4KB Block 15 –4KB Block 15 –4KB Block 15 –4KB Sector 15 –64KB Sector 14 –64KB Sector 0 –64KB Fig. 5.89 A serial Flash core memory organization: 16 sectors and 16 blocks in each sector 7 7 0 Page 0 (256B) 0x000FF 0 7 0 0x00F00 0x00100 0x00000 Page 1 (256B) 0x001FF Page 15 (256B) 0x00FFF Address mapping of Block 0 of Sector 0 Fig. 5.90 Memory organization of block 0 of sector 0: 16 pages, 256 bytes per page Figure 5.91 shows nine basic modes of operation for this Flash memory. Some of the modes in this table are further divided into sub-modes according to the complexity of the main mode. For example, in the write (program) mode, the opcode 0x20 assumes to write between 1 and 255 bytes into the memory core while the opcode 0x23 writes 64 KB of data into a sector. Similarly, the erase mode can be configured to erase a page, a block or the entire chip. The protect operation prevents overwriting to a sector or the chip. The write enable feature is a security measure for the serial Flash memory, and it is used prior to an actual write or an erase operation. Once the write enable command is issued, any kind of data alteration in the memory core becomes possible. Both the write enable and protect features are registered 5.5 Serial Flash Memory 255 in the status register and can be read on demand. The status register also indicates whether the device is busy, such as in the middle of a write or read operation, write enable is engaged or not, or which sector is protected. The Flash memory can be placed into a long term hibernation mode to save power. The modes in Fig. 5.91 are at minimum compared to a typical serial Flash memory to emphasize only the primary modes of operation. The opcode value for each mode is also randomly selected. Actual serial Flash memory datasheets contain many more operational modes with different opcode values assigned to each mode. FLASH MEMORY COMMANDS Read OPCODES 0x10 Write Byte (1-255) 0x20 Write Page 0x21 Write Block 0x22 Write Sector 0x23 Erase Page 0x30 Erase Block 0x31 Erase Chip 0x32 Protect Sector 0x40 Unprotect Sector 0x41 Protect Chip 0x42 Unprotect Chip 0x43 Write Erase Protect/Unprotect Write Enable 0x55 Write Disable 0x66 Read Status Register 0x77 Hibernate 0x88 Wake up 0x99 Fig. 5.91 Main serial Flash memory commands 256 5 Memory Circuits and Systems This particular Flash memory operates in both mode 0 (SCK is initially at logic 0) and mode 3 (SCK is initially at logic 1) of the SPI protocol. However, most of the timing diagrams in this section will refer to mode 0 when explaining different commands in Fig. 5.91. Figures 5.92 and 5.93 explain the basic write protocols in mode 0 and mode 3, respectively. Once SS signal is lowered to logic 0, data bits at SDI port can be written into the Flash memory’s data buffer at the positive edge of SCK. The data transaction stops when SS is raised to logic 1. The entire data buffer is subsequently transferred to the memory core within the write period, tWRITE. Mode 0 - Write Protocol SS SCK SDI MSB LSB Fig. 5.92 Serial Flash memory mode 0 SPI write (program) protocol Mode 3 - Write Protocol SS SCK SDI MSB LSB Fig. 5.93 Serial Flash memory mode 3 SPI write (program) protocol Similarly, Figs. 5.94 and 5.95 explain the basic read protocols in mode 0 and mode 3, respectively. When the SS signal is lowered to logic 0, data is delivered from the memory core to the data buffer, and then from the data buffer to the SDO terminal at the negative edge of each SCK cycle. The memory access is equal to tREAD with respect to the negative edge of SCK. When the SS signal is raised to logic 1, SCK is no longer allowed to change, and the read process terminates. In both write and read operations, the most significant data bit is delivered first, and the least significant data bit is delivered last. 5.5 Serial Flash Memory 257 Mode 0 - Read Protocol SS SCK SDO MSB LSB Fig. 5.94 Serial Flash memory mode 0 SPI read protocol Mode 3 - Read Protocol SS SCK SDO MSB LSB Fig. 5.95 Serial Flash memory mode 3 SPI read protocol A typical Flash memory byte read is shown in Fig. 5.96. The process starts with sending the opcode, 0x10, corresponding to a read operation according to the table in Fig. 5.91. A 20-bit address follows the opcode with the most significant address bit, A19, first, and the least significant address bit, A0, last. The first data bit, D7 (also the most significant bit of data), is delivered to the SDO terminal at the negative edge of SCK according to Fig. 5.96. The remaining seven bits of data are sequentially delivered at each negative edge of SCK until the SCK signal stabilizes at logic 0, and the SS signal transitions to logic 1. SS SCK SDI 0 0 0 1 OPCODE = 0x10 = READ 0 A19 MSB A18 A0 LSB ADDRESS [19:0] SDO D7 MSB D6 D0 LSB BYTE Fig. 5.96 Serial Flash memory byte read in mode 0 258 5 Memory Circuits and Systems Once a starting 20-bit address is issued, a number of bytes, ranging from one byte to the contents of the entire memory, can be read from the SDO port as long as the SS signal is kept at logic 0, and the SCK activity is present. Terminating SCK and raising SS to logic 1 ceases the read process as shown in Fig. 5.97. SS SCK SDI 0 0 0 1 0 A19 MSB OPCODE = 0x10 = READ A18 A0 LSB ADDRESS [19:0] SDO D7 MSB D0 LSB BYTE 0 D7 MSB D0 LSB BYTE N (MAX = 1,048,575) Fig. 5.97 Serial Flash memory read burst in mode 0 The Flash memory write (program) mode has four sub modes. In the byte write mode, bytes ranging between 1 and 255 can be written to a page following the opcode, 0x20, and a 20-bit memory address as shown in Fig. 5.98. After data is written to the last address of the page, subsequent bytes at SDI terminal are considered invalid and will be ignored even though there may still be SCK activity and/or SS may still be at logic 0. In some serial Flash memory chips, excess data is not ignored but written to the memory core starting from the first address of the page (address looping). SS SCK SDI 0 0 1 0 OPCODE = 0x20 = WRITE BYTE 0 A19 MSB A18 A0 LSB D7 MSB ADDRESS [19:0] Fig. 5.98 Serial Flash memory write burst (1 to 255 bytes) in mode 0 D6 BYTE (1-255) D0 LSB 5.5 Serial Flash Memory 259 Figure 5.99 describes the page write mode. After issuing the write page opcode, 0x21, and a 20-bit page address, 256 bytes of data are sequentially written into the memory core starting from the top of the page. Any data beyond 256 bytes will be ignored by the device. It is vital that the 20-bit starting address aligns with the first address of the page. For example, if page 0 of block 0 in sector 0 needs to be accessed to write data, the starting address has to be 0x00000 according to Fig. 5.90. Similarly, the starting address has to be 0x00100 for page 1 or 0x00F00 for page 15 if the contents of either page need to be written. Writing to a block or a sector is not any different from writing to a page. In both instances, the starting 20-bit address needs to align with the topmost address of the block or the sector. For example, writing a 4 KB of data to block 0 of sector 0 requires the starting address to be 0x00000. Similarly, the starting address of block 1 of sector 0 has to be 0x01000 if 4 KB data needs to be written to this block. SS SCK SDI 0 0 1 0 OPCODE = 0x21 = WRITE PAGE 1 A19 MSB A18 A0 LSB ADDRESS [19:0] D7 MSB D0 LSB D7 MSB BYTE 0 D0 LSB BYTE 255 PAGE Fig. 5.99 Serial Flash memory page write in mode 0 Erase can be performed on a page, a block or the entire chip according to the table in Fig. 5.91. The page erase requires the opcode, 0x30, followed by the topmost address of the page as shown in Fig. 5.100. Erasing the entire chip only requires the opcode, 0x32, as shown in Fig. 5.101. 260 5 Memory Circuits and Systems SS SCK SDI 0 0 1 1 0 A19 MSB OPCODE = 0x30 = PAGE ERASE A18 A0 LSB PAGE ADDRESS [19:0] Fig. 5.100 Serial Flash memory page erase in mode 0 SS SCK SDI 0 0 1 1 0 0 1 0 OPCODE = 0x32 = CHIP ERASE Fig. 5.101 Serial Flash memory chip erase in mode 0 Accidentally altering the contents of the Flash memory is a non-reversible process. Therefore, many manufacturers formulate a security measure, such as a write enable command, prior to a write or an erase operation. The write enable command requires issuing an opcode, 0x55, according to Fig. 5.91, and it is implemented in Fig. 5.102. This code changes the write enable bit in the status register which then enables the Flash memory for write or erase. For example, in Fig. 5.103 the write enable opcode, 0x55, is issued prior to the write byte opcode, 0x20, to allow any number of bytes to be written to a page. If the write enable opcode is omitted prior to a byte, a page, a block or a sector write, the data delivered to the memory core becomes invalid and is ignored. 5.5 Serial Flash Memory 261 SS SCK SDI 0 1 0 1 0 1 0 1 OPCODE = 0x55 = WRITE ENABLE Fig. 5.102 Serial Flash memory write enable operation in mode 0 SS SCK SDI 0 1 0 1 1 OPCODE = 0x55 = WRITE ENABLE 0 0 1 0 OPCODE = 0x20 = WRITE BYTE 0 A19 MSB A18 A0 LSB ADDRESS [19:0] D7 MSB D6 D0 LSB BYTE (1-255) Fig. 5.103 Serial Flash memory write (program) burst (1 to 255 bytes) followed by write enable Protecting a sector or the entire chip is also a vital security measure for the Flash memory. For example, if a Flash memory contains BIOS data in specific sectors, accidentally accessing these sectors for write or erase becomes fatal. Therefore, such accesses need to be prevented at all costs. The opcode, 0x40, is issued with a specific sector address to protect the data in this sector as shown in Fig. 5.104. However, as with the write and erase modes, the write enable opcode, 0x55, must accompany the sector protect opcode, 0x40, to make the sector protect a valid entry as shown in the timing diagram in Fig. 5.105. 262 5 Memory Circuits and Systems SS SCK SDI 0 1 0 0 0 0 0 0 A19 MSB OPCODE = 0x40 = PROTECT SECTOR A18 A0 LSB SECTOR ADDRESS [19:0] Fig. 5.104 Serial Flash memory protect sector operation in mode 0 SS SCK SDI 0 1 0 1 1 OPCODE = 0x55 = WRITE ENABLE 0 1 0 0 0 OPCODE = 0x40 = PROTECT SECTOR A19 MSB A18 A0 LSB SECTOR ADDRESS [19:0] Fig. 5.105 Serial Flash memory write enable operation followed by protect sector in mode 0 The user may reverse the write enable status of the device by issuing a write disable command, 0x66, as shown in the timing diagram in Fig. 5.106. Status register constitutes an important part of the Flash memory programming. For this particular Flash memory, there are four entries in the status register that contain vital operational information as shown in Fig. 5.107. The SP0, SP1 and SP2 bits identify which 5.5 Serial Flash Memory 263 SS SCK SDI 0 1 1 0 0 1 1 0 OPCODE = 0x66 = WRITE DISABLE Fig. 5.106 Serial Flash memory write disable operation in mode 0 7 6 5 Reserved 4 3 2 1 0 SP2 SP1 SP0 WEL WIP WIP = Write In Progress = 1 Device is busy with write 0 Device is not busy with write WEL = Write Enable Status = 1 Write Enable is active 0 Write Enable is inactive SP2 SP1 SP0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 No sector is protected Address 0x00000 to 0x0FFFF is protected Address 0x00000 to 0x1FFFF is protected Address 0x00000 to 0x3FFFF is protected Address 0x00000 to 0x7FFFF is protected Address 0x00000 to 0xFFFFF is protected Address 0x00000 to 0xFFFFF is protected Address 0x00000 to 0xFFFFF is protected Fig. 5.107 Serial Flash memory status register sectors are protected. The Write Enable Latch bit, WEL, signifies if the device has already been write-enabled or not. The Write-In-Progress, WIP, bit defines if the device is busy with a write process. The user can access the contents of the status register at any time by issuing the read status register command, 0x77, as shown in Fig. 5.108. After executing this command, the contents of the status register become available at the SDO port. The user can also place the Flash memory into the sleep mode to conserve power by issuing hibernate opcode, 0x88, as shown in Fig. 5.109. The hibernation mode can be reversed by issuing the wake-up opcode, 0x99, as shown in Fig. 5.91. 264 5 Memory Circuits and Systems SS SCK SDI 0 1 1 1 1 OPCODE = 0x77 = READ STATUS REGISTER SDO Res MSB Res Res SP2 SP1 SP0 WEL STATUS REGISTER CONTENTS Fig. 5.108 Serial Flash memory status register read operation in mode 0 SS SCK SDI 1 0 0 0 1 0 0 0 OPCODE = 0x88 = CHIP HIBERNATE Fig. 5.109 Serial Flash memory chip hibernate operation in mode 0 WIP LSB 5.5 Serial Flash Memory 265 Review Questions 1. An SDRAM is composed of two16-bit wide banks, bank 0 and bank 1, as shown below. SDRAM Bank0 SDRAM Bank1 15 15 0 0 0xAB00 0000 0xCD00 AA00 0xAB01 0xAB02 1111 2222 0xCD01 0xCD02 BB11 CC22 0xAB03 0xAB04 3333 4444 0xCD03 0xCD04 DD33 EE44 0xAB05 0xAB06 5555 6666 0xCD05 0xCD06 FF55 AA11 0xAB07 0xAB08 7777 8888 0xCD07 0xCD08 BB22 CC33 0xAB09 0xAB0A 9999 AAAA 0xCD09 0xCD0A DD44 EE55 The truth table below defines the precharge, activate and read cycles. Operation CS RAS CAS WE Precharge 0 0 1 0 Activate 0 0 1 1 Read 0 1 0 1 Each 16-bit SDRAM address is composed of two parts: the most significant byte corresponds to the row address, and the least significant byte corresponds to the column address as shown below. Address = {Row Address, Column Address} The precharge wait period is two clock cycles between the positive edge of the precharge cycle and the positive edge of the activate cycle. Similarly, the CAS wait period is two cycles between the positive edge of the activate cycle and the positive edge of the read command. The read burst from the specified address starts after a latency of two cycles. The waiting period between the last data packet and the precharge cycle is also two cycles if the read repeats from the same bank. 266 5 Memory Circuits and Systems (a) Show the two read sequences in sequential addressing mode from Bank 0. Each burst contains four data packets: the first burst is from the address, 0xAB03, and the next from the address, 0xAB07. (b) Show the two read sequences in sequential addressing mode from different banks with no delay in between. Each burst contains four data packets: the first burst is from the Bank 0 with the starting address, 0xAB03, and the next from Bank 1 with the address, 0xCD06. 2. A Flash memory is composed of two byte-addressable sectors. It has an eight-bit bidirectional I/O port for reading and writing data, and a 16-bit unidirectional address port. The upper eight bits of the address field are allocated for the sector address and the lower eight bits for the program address. The three active-low inputs, EN, RE and WE, control the Flash memory according to the following chart: Operations EN RE WE Read Write 0 0 0 1 1 0 Standby 0 1 1 Off 1 x x The initial data contents in this memory are shown below: Sector 0 Sector 1 15 0 15 0 0xEE 0xCC 0xFF 0xDD 0x00 0x02 0x34 0x78 0x12 0x56 0x00 0x02 0xAA 0x88 0xBB 0x99 0x04 0x06 0xBC 0xF0 0x9A 0xDE 0x04 0x06 The Flash command chart is as follows: Cycle 1 Sector protect Fast write Read Cycle 2 Cycle 3 Addr Data Addr Data Addr Data word word 0x5555 0x5555 0xAA 0xAAAA 0xAAAA 0x55 Sector Addr 0x01 Write Addr Write Data byte word 0xAAAA 0x5555 Write Addr Write Data Read Addr Read Data byte 0xAAAA Read Addr Read Data 0xAA 0xAA 0x5555 0xAAAA 0x5555 0x02 0x03 5.5 Serial Flash Memory 267 In this diagram, the sector protect is a three-cycle sequence where the sector protect code, 0x01, is provided in the third cycle along with the sector address. Both the fast write and the read processes are initially three cycles. However, once the process starts, additional reads or writes are reduced to two-cycle operations as shown in the flow chart below. According to this chart, for each additional data to be read or written, the command code must be employed in the second cycle, and the address/data combination in the third cycle. The flow chart for the fast write and read is as follows: Start First cycle Second cycle Addr/ Data Last Addr no Incr. Addr yes Finish (a) Perform protect sector 1. Show the timing diagram with control inputs, address and data. (b) Perform fast write to sector 0 with four bytes of data, 0x11, 0x22, 0x33, 0x44. Start from the address, 0x04, and increment the address to write each byte. (c) Read four bytes from sector 0 at the addresses, 0x00, 0x02, 0x04 and 0x06. Show the timing diagram with control inputs, address and data. 268 5 Memory Circuits and Systems 3. Two reads need to be accomplished from a 16-bit wide SDRAM organized in four banks with the data shown below. 15 AA00 AA01 AA02 AA03 AA04 AA05 AA06 AA07 0 1111 2222 3333 4444 5555 6666 7777 8888 15 BB00 BB01 BB02 BB03 BB04 BB05 BB06 0 AAAA BBBB CCCC CC00 CC01 CC02 DDDD EEEE FFFF CC03 CC04 0000 1111 CC06 BB07 Bank0 15 CC05 CC07 Bank1 0 15 DD00 FFFF EEEE DDDD CCCC BBBB AAAA DD01 DD02 DD03 DD04 DD05 1111 0000 DD06 DD07 Bank2 0 8888 7777 6666 5555 4444 3333 2222 1111 Bank3 Each SDRAM address is composed of an eight-bit wide row address, RA[7:0], and an eight-bit wide column address, CA[7:0], as in the following format: SDRAM Address = {RA[7:0], CA[7:0]} where the row address occupies higher bits. To control SDRAM, the following controls are supplied: Operation CS RAS CAS WE Precharge 0 0 1 0 Activate 0 0 1 1 Read 0 1 0 1 The wait period between the precharge and the activate cycles is one clock cycle. Similarly, the wait period between the activate and the read cycles is one clock cycle. The precharge cycle for the next read operation takes place after the last data is read out from SDRAM. BS[1:0] = 0 selects Bank0, BS[1:0] = 1 selects Bank1, BS[1:0] = 2 selects Bank2, and BS[1:0] = 3 selects Bank3 in the timing diagrams. (a) Assuming that the mode register is pre-programmed in sequential mode addressing with a burst length of four and a CAS latency of two, construct a timing diagram to show the two reads from the SDRAM addresses, 0xAA00 and 0xAA04. Start from the precharge cycle to accomplish each read. (b) With the same mode register contents in part (a), construct a timing diagram such that the two reads from the SDRAM addresses, 0xAA00 and 0xBB02, take place in the shortest possible time. Again start from the precharge cycle to accomplish each read. 5.5 Serial Flash Memory 269 (c) With the same mode register contents in part (a), accomplish one read from the SDRAM address, 0xCC00, with a burst length of two, and one read from the SDRAM address, 0xDD02, with a burst length of eight. Start from the precharge cycle to accomplish each read. 4. Subsequent write and read operations are performed on an SDRAM that consists of two banks. Both banks have eight-bit wide I/O data ports. The first SDRAM operation is a write operation that writes 0x11 to the starting address of 0xAB in bank 0. This is followed by writing the data values, 0xEE, 0x00 and 0xFF, to bank 0 in sequential mode. The read operation takes place from bank 1 without any interruption. This means that the first read-data is delivered to the data bus immediately after the last data, 0xFF, has been written. The first read-address is defined as 0x12. Four data packets are read from this starting address in sequential mode with a latency of two cycles. Both write and read operations require tPRE = tCAS = 1 cycle. Construct a timing diagram with control, address and data values to achieve these two consecutive operations. Assume all initial data values in Bank 0 are 0x00. Make sure to mark each precharge, activate, write and read cycle on the timing diagram. Indicate where latency happens. 7 7 0 BANK 0 0 Addr[0xA0] 0x88 Addr[0x10] Addr[0xA1] 0x99 Addr[0x11] Addr[0xA2] 0xAA Addr[0x12] Addr[0xA3] 0xBB Addr[0x13] Addr[0xA4] 0xCC Addr[0x14] Addr[0xA5] 0xDD Addr[0x15] Addr[0xA6] 0xEE Addr[0x16] Addr[0xA7] 0xFF Addr[0x17] Addr[0xA8] 0x00 Addr[0x18] Addr[0xA9] 0x11 Addr[0x19] Addr[0xAA] 0x22 Addr[0x1A] Addr[0xAB] 0x33 Addr[0x1B] Addr[0xAC] 0x44 Addr[0x1C] Addr[0xAD] 0x55 Addr[0x1D] Addr[0xAE] 0x66 Addr[0x1E] Addr[0xAF] 0x77 Addr[0x1F] BANK 1 270 5 Memory Circuits and Systems 5. An E2PROM memory is organized in four sectors. There are eight rows in each sector but no pages. The existing data in this memory is shown below. 3 0 3 7 0x7 7 6 5 0x6 6 5 3 0 0 3 0xF 7 0x0 7 0xE 6 5 0x1 6 5 0 0x8 0x9 4 0x5 0x4 4 0xD 0xC 4 0x2 0x3 4 0xA 0xB 3 0x3 3 0xB 3 0x4 3 0xC 2 1 0x2 2 1 0xA 2 1 0x5 2 1 0xD 0 0x1 0x0 Sector 0 0 0x9 0x8 Sector 1 0x6 0x7 0 Sector 2 0 0xE 0xF Sector 3 The command truth table is given below. Function SR Read Command code Read 0x0 0x1 Write buffer Write core 0x2 0x3 The memory has five control pins: EN is an active-low signal that activates the sector AE is an active-high signal that accepts address CE is an active-high signal that enables command function WE is an active-low signal that enables write RE is an active-low signal that enables read Writing to the memory takes place at the rising edge of WE. At the falling edge of RE, reads take place from the memory. The write sequence starts with the command function followed by the address and then the data. The read sequence follows a similar fashion: it starts with the read command, then the address and then the data. Assume all AE, WE and RE set-up times are 0 s. The setup and hold times for command, address and data are all different from 0 s. It takes tWRITE amount of time to transfer data from the buffer to the memory core. (a) Draw a timing diagram to read data from the row address = 0 and the sector address = 3. (b) Draw a timing diagram to write 0xA, 0xB, 0xC, 0xD, 0xE, 0xF, 0x7, 0x6 starting from the row address = 2 and the sector address = 2 in the following manner: the first data, 0xA, to the row address 2; the second data, 0xB, to the row address 0x3 and so forth. Draw the contents of the memory after the write sequence is complete. 5.5 Serial Flash Memory 271 6. A Flash memory block has an eight-bit address, and executes all reads and writes on an eight-bit bidirectional data bus. The Flash memory write sequence contains a preamble, a write command, and an address/data combination as shown in the flow chart below. Once the write command is issued, the address/data combination is generated continuously until the last write takes place. The sequence ends with the same preamble that starts the write. START Preamble Write com Addr/Data Next Addr no Last Addr yes Preamble DONE In the read sequence, the bus master starts fetching data once the preamble and the read command are issued. The sequence has the same exit preamble as shown below. START Preamble Read com Addr/Data Next Addr no Last Addr yes Preamble DONE 272 5 Memory Circuits and Systems START and DONE do not have any significance in timing diagrams other than that they indicate the start and the end of the sequence, respectively. The preamble, write and read commands are issued with the hexadecimal values shown in the truth table below. COMMANDS Address Data Preamble FF 00 Write com AA FF Read com BB FF The state of the Flash memory before any read or write operation is shown below. The leftmost column in this figure shows the Flash memory address in hexadecimal. 7 F8 F9 FA FB FC FD FE FF 0 FF EE DD CC BB AA 99 88 The bus master produces three data transmissions for the Flash memory. In the first transmission, four data packets are written to the Flash memory as shown below. Packet no Address Data 1 F8 00 2 F9 11 3 FA 22 4 FB 33 5.5 Serial Flash Memory 273 In the second transmission, the bus master reads two data packets from the following addresses below. Packet no Address 1 FA 2 FB Data In the third transmission, the bus master reads two more data packets from the following addresses. Packet no Address 1 FE 2 FF Data Construct a timing diagram, including the address, the active-low WE and RE signals, and the data. Note that the Flash memory requires a hold period which coincides with the high phase of EN signal. However, in the low phase, when the Flash memory is active, the device either writes or reads depending on the value of the WE and RE signals, respectively. 7. A serial on-chip SPI bus described in Chapter 4 is used to program an SDRAM register file that consists of five registers (see the SDRAM bus interface architecture). Assume that each register in the register file has an eight-bit long address. Data in each register is also assumed to be eight bits long. The Wait register receives the number of clock periods which is equivalent to tWAIT, the Latency register to tLAT, the Burst register to tBURST, the CAS register to tCAS, and the Precharge register to tPRE. The SDI port of the SDRAM programming interface receives an eight-bit address (starting with the most significant bit) followed by an eight-bit data (again starting with the most significant bit) at the positive edge of SCK until all five registers are programmed while SS = 0. Once the programming is finished, the SS node pulls back to logic 1. Design the interface between the SPI bus and the register file. Make sure to show each SPI-compliant I/O port (such as SCK, SDI, SS etc.), the internal address, data and control signals of the interface on the timing diagram. The functionality of the interface must be the same in both the timing diagram and the data-path. Start building the timing diagram that includes only the address and the data. Then form the corresponding data-path that matches the timing diagram. Increase the complexity of the design by including the control signals in the timing diagram, guiding the data flow. Lastly, draw the state diagram of the Moore type controller for the interface. 274 5 Memory Circuits and Systems Projects 1. Implement and verify the SRAM bus interface unit described in Fig. 5.5 with the unidirectional bus designed in Chapter 4. Use Verilog as the hardware design language for the module implementation and functional verification. Make sure the interface complies with the timing diagrams shown in Figs. 5.6 and 5.8 and includes a controller unit as shown in Figs. 5.7 and 5.9. 2. Implement and verify the SDRAM bus interface unit described in Fig. 5.25 with the unidirectional bus designed in Chapter 4. Use Verilog as the hardware design language for the module implementation and functional verification. Make sure the interface complies with the timing diagrams shown in Figs. 5.27 and 5.29 and includes a controller unit as shown in Figs. 5.28 and 5.30. Produce the hardware to program the SDRAM register file. Assume a serial bus such as SPI or I2C to distribute the program data to the registers. 3. Implement and verify the I2C fast write interface in the first design example of Chapter 5 using Verilog. Make sure your design is consistent with the state machine shown in Fig. 5.72. 4. Implement and verify the I2C read interface in the second design example using Verilog. Make sure to be consistent with the state machine shown in Fig. 5.80. 5. Combine the read and the fast write interfaces into a single unit. Design and verify the complete interface using Verilog. Note that for projects 3 through 5, write a behavioral Verilog code that mimics the bus master in order to send data on the I2C bus. References 1. 2. 3. 4. 5. 6. 7. Toshiba datasheet TC59S6416/08/04BFT/BFTL-80, -10 Synchronous Dynamic RAM Toshiba datasheet TC58DVM72A1FT00/TC58DVM72F1FT00 128Mbit E2PROM Toshiba datasheet TC58256AFT 256Mbit E2PROM Toshiba datasheet TC58FVT004/B004FT-85, -10, -12 4MBit CMOS Flash memory Toshiba datasheet TC58FVT400/B400F/FT-85, -10, -12 4MBit CMOS Flash memory Toshiba datasheet TC58FVT641/B641FT/XB-70, -10 64MBit CMOS Flash memory Atmel datasheet AT26DF161 16Mbit serial data Flash memory