2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2016
A simulation study exploring the possibility of performance improvements related with the applica... more A simulation study exploring the possibility of performance improvements related with the application of stress to nanowire TFETs is carried out. It is demonstrated that appropriate strain conditions, i.e., biaxial tensile strain, induce a remarkable enhancement of the on-state current thanks to bandgap reduction. However, a careful optimization of the device cross-section and strain level must be carried out in order to preserve the device subthreshold swing.
2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2016
The impact of strain and semiconductor/oxide interface traps (ITs) on the turn-on characteristics... more The impact of strain and semiconductor/oxide interface traps (ITs) on the turn-on characteristics of a 10×10 nm2 nanowire (NW) Al0.05Ga0.95Sb/InAs heterojunction n-type tunnel field-effect transistor (TFETs) is carefully investigated using a full-quantum simulator. In order to capture the effect of traps on the device electrostatics in a way consistent with the ballistic approach, the SRH theory has been properly generalized. Our results indicate that the presence of a relatively high IT density can cause a huge current reduction that cannot be recovered exploiting strain. In fact, biaxial tensile strain induces a remarkable current enhancement due to bandgap reduction and tunnel energy alignment at the heterojunction; however, a huge degradation of the ambipolar behavior is also observed.
2014 44th European Solid State Device Research Conference (ESSDERC), 2014
Different AC pulsed stress signals have been applied to an n-type LDMOS with shallow-trench isola... more Different AC pulsed stress signals have been applied to an n-type LDMOS with shallow-trench isolation (STI). The HCS degradation curves have been measured on wafer by varying frequency and duty-cycle under a high-VDS stress for both low and high Vgs biases. The linear drain current drifts have been also investigated through TCAD predictions under AC stress conditions for the first time. A quantitative explanation of the dependence on frequency and duty cycle has been obtained using the new approach based on physical models. An extended analysis of the HCS degradation in a real switching application through a resistive load has been reported to gain an insight on the role played by the peak-HCS rates during the rising/falling edges.
This paper investigates the digital circuit-level performance of an inverter realised with n-and ... more This paper investigates the digital circuit-level performance of an inverter realised with n-and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/Al 0.05 Ga 0.95 Sb technology platform in the presence of interface traps and localized strain. The TFET-based inverter is simulated for two different I OFF values, namely 100 nA/µm and 10 pA/µm to target both highperformance and low-power applications. Based on 3D full-quantum simulations, interface traps induce a significant degradation of the voltage gain, noise margin and transient performance despite the better subthreshold slope. The effect of localized strain at the source/channel heterojunction caused by lattice mismatch, while being beneficial in terms of on-current, is unable to recover the circuit-level performance of the ideal case. The device with traps and localized strain is able to outperform the ideal one only in terms of switching transients for I OFF = 10 pA/µm.
The most relevant transport features of doped diamond-like carbon (DLC) films have been implement... more The most relevant transport features of doped diamond-like carbon (DLC) films have been implemented in a TCAD setup to provide a theoretical tool to assess the reliability expectations for high-voltage device passivation. Starting from the band structure and boundary conditions of a metal-insulator-semiconductor (MIS) device, trap states in the bandgap have been used to determine the characteristics of differently doped DLC layers against experiments. The role of the DLC as a passivation layer on top of the bevel termination of a high-voltage diode has been studied and compared with experiments. The breakdown voltage is significantly influenced by the properties of the DLC as clearly explained by the TCAD simulation results.
Journal of Computational and Theoretical Nanoscience, 2008
In this work we investigate the performance of silicon nanowire and carbon-nanotube FETs at their... more In this work we investigate the performance of silicon nanowire and carbon-nanotube FETs at their extreme miniaturization limits. The model self-consistently solves the Schroedinger and Poisson equations using the Quantum Transmitting Boundary Method (QTBM) formalism. We compare the subthreshold slope, the drain-induced barrier lowering and the Ion/Ioff ratio versus diameter and gate length. The performance comparison demonstrates that the nanowire FET provides a better scaling trend at very low size despite its weaker gate control on the device electrostatics
A theoretical and experimental investigation on the electron impact ionization in silicon has bee... more A theoretical and experimental investigation on the electron impact ionization in silicon has been carried out in a temperature range up to about 1000 K. The proposed impact-ionization model amply extends the range of simulation tools up to temperatures which are important to predict the failure threshold of ESD-protection and power devices. Different protection diodes are investigated with electro-thermal simulation
The linear drain current degradation due to hot-carrier stress (HCS) of an n-type LDMOS with shal... more The linear drain current degradation due to hot-carrier stress (HCS) of an n-type LDMOS with shallow-trench isolation (STI) has been investigated through experiments and TCAD predictions under AC pulsed stress conditions. The systematic increase of degradation with frequency and the dependence on rise/fall times and duty cycle has been explained by using a new TCAD approach based on physical models. The degradation increase can be correlated to the peak of the HCS reaction rate at the rising edge. The analysis carried out on two different devices confirms the TCAD predictions.
2006 European Solid-State Device Research Conference, 2006
ABSTRACT In this work, the authors investigate the accuracy of the parabolic-band model for the s... more ABSTRACT In this work, the authors investigate the accuracy of the parabolic-band model for the simulation of cylindrical nanowire (CNW) FETs scaled down to a 1-nm diameter. Doing so, rely on a recently-published results based on a tight-binding computation of the band structure in square-and circular-section nanowires. The above results indicate that the FET characteristics are affected in two ways by the parabolic-band approximation: first, the conduction-band edge is shifted upwards in both nanowire types, leading to an overestimation of the FET threshold voltage at small wire areas; next, the transport effective masses are increased by the structural confinement of the electron charge, which is neglected in the parabolic-band model. Fitting functions of the tight-binding conduction-band edge and transport effective masses are worked out, thus providing the appropriate parameters for transport simulations. The output characteristics of the CNW-FET are then computed using the quantum-transmitting boundary method (QTBM) with and without the corrected conduction-band edge and transport effective masses, and the influence of the above corrections on threshold voltage and on-current is finally assessed
ABSTRACT In this work we investigate the performance of double-gate and cylindrical nanowire FETs... more ABSTRACT In this work we investigate the performance of double-gate and cylindrical nanowire FETs with high-kappa gate dielectrics at their extreme miniaturization limits. The model fully accounts for quantum electrostatics; current transport is simulated by an improved quantum drift-diffusion approach supported by a new thickness-dependent mobility model which nicely fits the available measurements for both SiO2 and HfO2 gate dielectrics. The on-current is simulated using both the quantum drift-diffusion model and a full-quantum transport approach based on the quantum transmitting boundary method, which assumes a purely ballistic transport. The performance comparison between SiO2 and HfO2 insulated-gate FETs with the same electrical oxide thickness demonstrates that the latter provides a slight degradation of the short-channel effect compared with the former but, at the same time, gives an improved on-current due to lateral capacitive-coupling effects, despite the inherent degradation of the low-field mobility
Ab initio calculations of the full-band structure of SiO 2 are worked out. Both the conduction an... more Ab initio calculations of the full-band structure of SiO 2 are worked out. Both the conduction and valence bands are investigated by means of two different techniques: Hartree-Fock (HF) and density-functional theory (DFT). A number of energy-level diagrams are calculated in order to compare the corresponding density of states in a range of about 10 eV. Different crystal structures of SiO 2 are studied, that are known to be built-up by the same fundamental unit, namely, the SiO 4 tetrahedron. All the analyzed systems are polymorphs of silica; specifically, the-and-quartz, the-and-cristobalite, and the-tridymite.
A number of experiments have recently appeared in the literature that extensively investigate the... more A number of experiments have recently appeared in the literature that extensively investigate the silicon-thickness dependence of the low-field carrier mobility in ultrathin-body silicon-on-insulator (SOI) MOSFETs. The aim of this paper is to develop a compact model, suited for implementation in devicesimulation tools, which accurately predicts the low-field mobility in SOI single-and double-gate MOSFETs with Si thicknesses down to 2.48 nm. Such a model is still missing in the literature, despite its importance to predict the performance of present and future devices based on ultrathin silicon layers.
A scalable Dual n/p-LDMOS device with interesting R SP versus V BD performance for voltage applic... more A scalable Dual n/p-LDMOS device with interesting R SP versus V BD performance for voltage applications in the range of 20-120 V is identified through proper optimization. Three designs have been proposed, based on different process implementations. The physical behavior of the device is reviewed and analyzed. The current expansion induced by the bipolar conductance in the drift region at high gate and drain biases is fully explained. The thermal behavior in a worst case condition is investigated, and the reduction in performance in terms of current and safe-operating area are reported. The switching performance is addressed, showing very good transient times in any analyzed load condition.
In this paper, an experimental investigation on high-temperature electron impact-ionization in si... more In this paper, an experimental investigation on high-temperature electron impact-ionization in silicon is carried out with the aim of improving the qualitative and quantitative understanding of carrier transport under electrostatic discharge (ESD) conditions. Special test devices were designed and manufactured using Infineon's SPT5 technology, namely: a bipolar junction transistor (BJT), a static-induction transistor (SIT) and a vertical DMOS transistor (VDMOS), all of them with a cylindrical geometry. The measurements were carried out using a customized measurement setup that allows very high operating temperatures to be reached. A novel extraction methodology allowing for the determination of the impact-ionization coefficient against electric field and lattice temperature has been used. The experiments, carried out up to 773 K, confirm a previous theoretical investigation on impact-ionization, and widely extend the validity range of the compact model here proposed for implementation in device simulation tools. This is especially useful to predict the failure threshold of ESD-protection and power devices. Index Terms-Electrostatic discharge (ESD) events, hightemperature device characterization, impact-ionization, nonequilibrium Auger effect, predictive TCAD tools. I. INTRODUCTION E NSURING electrostatic discharge (ESD) protection of microcircuits is one of the major issues in IC design. The ESD effect generates high-current pulses in semiconductors, with possible thermal instabilities which may be responsible for thermal overstress and, ultimately, circuit failure. Therefore, a clear understanding of the device physical behavior up to very high local temperatures is a necessary precondition to address the above reliability problem. The development of appropriate solutions requires an efficient design methodology, which can be worked out from the availability of predictive simulation
Physically based models of hot-carrier stress and dielectric-field-enhanced thermal damage have b... more Physically based models of hot-carrier stress and dielectric-field-enhanced thermal damage have been incorporated into a TCAD tool with the aim of investigating the electrical degradation in integrated power devices over an extended range of stress biases and ambient temperatures. An analytical formulation of the distribution function accounting for the effects of the full band structure has been employed for hot-carrier modeling purposes. A quantitative understanding of the kinetics and local distribution of degradation is achieved, and the drift of the most relevant parameters is nicely predicted on an extended range of stress times and biases.
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017
A simulation study on the impact of interface traps (ITs) and strain on the I/V characteristics o... more A simulation study on the impact of interface traps (ITs) and strain on the I/V characteristics of co-optimized n- and p-type tunnel field-effect transistors (TFETs) realized on the same InAs/Al0.05Ga0.95Sb technology platform is carried out using a full-quantum simulator. In order to capture the effect of interface/border traps on the device electrostatics in a way consistent with the ballistic approach, the classical Shockley-Read-Hall theory has been properly generalized. Traps induce a significant reduction on the ON-current; however, the inclusion of a uniform strain induces a remarkable current enhancement able to completely recover the current degradation.
This article illustrates the basic concepts underlying the operation of non-volatile memories (NV... more This article illustrates the basic concepts underlying the operation of non-volatile memories (NVM). After a classification of NVMs based on their functional properties with respect to the programming and erasing operations, the treatment addresses the structure, operation principles, circuit organization and reliability issues of read-only memories (ROM), electrically programmable read-only memories (EPROM), electrically programmable and erasable read-only memories (EEPROM) and flash memories, including both the NOR and NAND organizations. A final section is devoted to non-conventional memories, including magnetic, ferroelectric and phase-change memories, which are still in an early development stage
This article illustrates the operation principles, circuit organization, performance and reliabil... more This article illustrates the operation principles, circuit organization, performance and reliability issues of volatile memories, including the 6- and 4-transistors static RAM (SRAM), the 3- and 1-transistor dynamic RAM (DRAM), and the 10-transistor content addressable memory (CAM). First, the SRAM general features are discussed, including access time, packing density, and reliability issues. Also, a description of the basic cell topologies, cell array organization, and sense amplifier operation is provided. The treatment of DRAMs addresses the structural and functional properties of the one-transistor memory cell, the organization of the cell array, the structure and operation of the sense amplifier and the memory architecture. Finally, a short description of the structure and operation of associative memories is provided, as well as their basic application as a tag memory of set-associative caches
Aim of this work is to present a novel simulation tool based on the deterministic solution of the... more Aim of this work is to present a novel simulation tool based on the deterministic solution of the Boltzmann transport equation for electrons in the whole semiconductor-insulator structure. Full-band density of states and group velocity for SiO 2 have been incorporated, allowing for an accurate description of the distribution function on an extended range of energies.
2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2016
A simulation study exploring the possibility of performance improvements related with the applica... more A simulation study exploring the possibility of performance improvements related with the application of stress to nanowire TFETs is carried out. It is demonstrated that appropriate strain conditions, i.e., biaxial tensile strain, induce a remarkable enhancement of the on-state current thanks to bandgap reduction. However, a careful optimization of the device cross-section and strain level must be carried out in order to preserve the device subthreshold swing.
2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2016
The impact of strain and semiconductor/oxide interface traps (ITs) on the turn-on characteristics... more The impact of strain and semiconductor/oxide interface traps (ITs) on the turn-on characteristics of a 10×10 nm2 nanowire (NW) Al0.05Ga0.95Sb/InAs heterojunction n-type tunnel field-effect transistor (TFETs) is carefully investigated using a full-quantum simulator. In order to capture the effect of traps on the device electrostatics in a way consistent with the ballistic approach, the SRH theory has been properly generalized. Our results indicate that the presence of a relatively high IT density can cause a huge current reduction that cannot be recovered exploiting strain. In fact, biaxial tensile strain induces a remarkable current enhancement due to bandgap reduction and tunnel energy alignment at the heterojunction; however, a huge degradation of the ambipolar behavior is also observed.
2014 44th European Solid State Device Research Conference (ESSDERC), 2014
Different AC pulsed stress signals have been applied to an n-type LDMOS with shallow-trench isola... more Different AC pulsed stress signals have been applied to an n-type LDMOS with shallow-trench isolation (STI). The HCS degradation curves have been measured on wafer by varying frequency and duty-cycle under a high-VDS stress for both low and high Vgs biases. The linear drain current drifts have been also investigated through TCAD predictions under AC stress conditions for the first time. A quantitative explanation of the dependence on frequency and duty cycle has been obtained using the new approach based on physical models. An extended analysis of the HCS degradation in a real switching application through a resistive load has been reported to gain an insight on the role played by the peak-HCS rates during the rising/falling edges.
This paper investigates the digital circuit-level performance of an inverter realised with n-and ... more This paper investigates the digital circuit-level performance of an inverter realised with n-and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/Al 0.05 Ga 0.95 Sb technology platform in the presence of interface traps and localized strain. The TFET-based inverter is simulated for two different I OFF values, namely 100 nA/µm and 10 pA/µm to target both highperformance and low-power applications. Based on 3D full-quantum simulations, interface traps induce a significant degradation of the voltage gain, noise margin and transient performance despite the better subthreshold slope. The effect of localized strain at the source/channel heterojunction caused by lattice mismatch, while being beneficial in terms of on-current, is unable to recover the circuit-level performance of the ideal case. The device with traps and localized strain is able to outperform the ideal one only in terms of switching transients for I OFF = 10 pA/µm.
The most relevant transport features of doped diamond-like carbon (DLC) films have been implement... more The most relevant transport features of doped diamond-like carbon (DLC) films have been implemented in a TCAD setup to provide a theoretical tool to assess the reliability expectations for high-voltage device passivation. Starting from the band structure and boundary conditions of a metal-insulator-semiconductor (MIS) device, trap states in the bandgap have been used to determine the characteristics of differently doped DLC layers against experiments. The role of the DLC as a passivation layer on top of the bevel termination of a high-voltage diode has been studied and compared with experiments. The breakdown voltage is significantly influenced by the properties of the DLC as clearly explained by the TCAD simulation results.
Journal of Computational and Theoretical Nanoscience, 2008
In this work we investigate the performance of silicon nanowire and carbon-nanotube FETs at their... more In this work we investigate the performance of silicon nanowire and carbon-nanotube FETs at their extreme miniaturization limits. The model self-consistently solves the Schroedinger and Poisson equations using the Quantum Transmitting Boundary Method (QTBM) formalism. We compare the subthreshold slope, the drain-induced barrier lowering and the Ion/Ioff ratio versus diameter and gate length. The performance comparison demonstrates that the nanowire FET provides a better scaling trend at very low size despite its weaker gate control on the device electrostatics
A theoretical and experimental investigation on the electron impact ionization in silicon has bee... more A theoretical and experimental investigation on the electron impact ionization in silicon has been carried out in a temperature range up to about 1000 K. The proposed impact-ionization model amply extends the range of simulation tools up to temperatures which are important to predict the failure threshold of ESD-protection and power devices. Different protection diodes are investigated with electro-thermal simulation
The linear drain current degradation due to hot-carrier stress (HCS) of an n-type LDMOS with shal... more The linear drain current degradation due to hot-carrier stress (HCS) of an n-type LDMOS with shallow-trench isolation (STI) has been investigated through experiments and TCAD predictions under AC pulsed stress conditions. The systematic increase of degradation with frequency and the dependence on rise/fall times and duty cycle has been explained by using a new TCAD approach based on physical models. The degradation increase can be correlated to the peak of the HCS reaction rate at the rising edge. The analysis carried out on two different devices confirms the TCAD predictions.
2006 European Solid-State Device Research Conference, 2006
ABSTRACT In this work, the authors investigate the accuracy of the parabolic-band model for the s... more ABSTRACT In this work, the authors investigate the accuracy of the parabolic-band model for the simulation of cylindrical nanowire (CNW) FETs scaled down to a 1-nm diameter. Doing so, rely on a recently-published results based on a tight-binding computation of the band structure in square-and circular-section nanowires. The above results indicate that the FET characteristics are affected in two ways by the parabolic-band approximation: first, the conduction-band edge is shifted upwards in both nanowire types, leading to an overestimation of the FET threshold voltage at small wire areas; next, the transport effective masses are increased by the structural confinement of the electron charge, which is neglected in the parabolic-band model. Fitting functions of the tight-binding conduction-band edge and transport effective masses are worked out, thus providing the appropriate parameters for transport simulations. The output characteristics of the CNW-FET are then computed using the quantum-transmitting boundary method (QTBM) with and without the corrected conduction-band edge and transport effective masses, and the influence of the above corrections on threshold voltage and on-current is finally assessed
ABSTRACT In this work we investigate the performance of double-gate and cylindrical nanowire FETs... more ABSTRACT In this work we investigate the performance of double-gate and cylindrical nanowire FETs with high-kappa gate dielectrics at their extreme miniaturization limits. The model fully accounts for quantum electrostatics; current transport is simulated by an improved quantum drift-diffusion approach supported by a new thickness-dependent mobility model which nicely fits the available measurements for both SiO2 and HfO2 gate dielectrics. The on-current is simulated using both the quantum drift-diffusion model and a full-quantum transport approach based on the quantum transmitting boundary method, which assumes a purely ballistic transport. The performance comparison between SiO2 and HfO2 insulated-gate FETs with the same electrical oxide thickness demonstrates that the latter provides a slight degradation of the short-channel effect compared with the former but, at the same time, gives an improved on-current due to lateral capacitive-coupling effects, despite the inherent degradation of the low-field mobility
Ab initio calculations of the full-band structure of SiO 2 are worked out. Both the conduction an... more Ab initio calculations of the full-band structure of SiO 2 are worked out. Both the conduction and valence bands are investigated by means of two different techniques: Hartree-Fock (HF) and density-functional theory (DFT). A number of energy-level diagrams are calculated in order to compare the corresponding density of states in a range of about 10 eV. Different crystal structures of SiO 2 are studied, that are known to be built-up by the same fundamental unit, namely, the SiO 4 tetrahedron. All the analyzed systems are polymorphs of silica; specifically, the-and-quartz, the-and-cristobalite, and the-tridymite.
A number of experiments have recently appeared in the literature that extensively investigate the... more A number of experiments have recently appeared in the literature that extensively investigate the silicon-thickness dependence of the low-field carrier mobility in ultrathin-body silicon-on-insulator (SOI) MOSFETs. The aim of this paper is to develop a compact model, suited for implementation in devicesimulation tools, which accurately predicts the low-field mobility in SOI single-and double-gate MOSFETs with Si thicknesses down to 2.48 nm. Such a model is still missing in the literature, despite its importance to predict the performance of present and future devices based on ultrathin silicon layers.
A scalable Dual n/p-LDMOS device with interesting R SP versus V BD performance for voltage applic... more A scalable Dual n/p-LDMOS device with interesting R SP versus V BD performance for voltage applications in the range of 20-120 V is identified through proper optimization. Three designs have been proposed, based on different process implementations. The physical behavior of the device is reviewed and analyzed. The current expansion induced by the bipolar conductance in the drift region at high gate and drain biases is fully explained. The thermal behavior in a worst case condition is investigated, and the reduction in performance in terms of current and safe-operating area are reported. The switching performance is addressed, showing very good transient times in any analyzed load condition.
In this paper, an experimental investigation on high-temperature electron impact-ionization in si... more In this paper, an experimental investigation on high-temperature electron impact-ionization in silicon is carried out with the aim of improving the qualitative and quantitative understanding of carrier transport under electrostatic discharge (ESD) conditions. Special test devices were designed and manufactured using Infineon's SPT5 technology, namely: a bipolar junction transistor (BJT), a static-induction transistor (SIT) and a vertical DMOS transistor (VDMOS), all of them with a cylindrical geometry. The measurements were carried out using a customized measurement setup that allows very high operating temperatures to be reached. A novel extraction methodology allowing for the determination of the impact-ionization coefficient against electric field and lattice temperature has been used. The experiments, carried out up to 773 K, confirm a previous theoretical investigation on impact-ionization, and widely extend the validity range of the compact model here proposed for implementation in device simulation tools. This is especially useful to predict the failure threshold of ESD-protection and power devices. Index Terms-Electrostatic discharge (ESD) events, hightemperature device characterization, impact-ionization, nonequilibrium Auger effect, predictive TCAD tools. I. INTRODUCTION E NSURING electrostatic discharge (ESD) protection of microcircuits is one of the major issues in IC design. The ESD effect generates high-current pulses in semiconductors, with possible thermal instabilities which may be responsible for thermal overstress and, ultimately, circuit failure. Therefore, a clear understanding of the device physical behavior up to very high local temperatures is a necessary precondition to address the above reliability problem. The development of appropriate solutions requires an efficient design methodology, which can be worked out from the availability of predictive simulation
Physically based models of hot-carrier stress and dielectric-field-enhanced thermal damage have b... more Physically based models of hot-carrier stress and dielectric-field-enhanced thermal damage have been incorporated into a TCAD tool with the aim of investigating the electrical degradation in integrated power devices over an extended range of stress biases and ambient temperatures. An analytical formulation of the distribution function accounting for the effects of the full band structure has been employed for hot-carrier modeling purposes. A quantitative understanding of the kinetics and local distribution of degradation is achieved, and the drift of the most relevant parameters is nicely predicted on an extended range of stress times and biases.
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017
A simulation study on the impact of interface traps (ITs) and strain on the I/V characteristics o... more A simulation study on the impact of interface traps (ITs) and strain on the I/V characteristics of co-optimized n- and p-type tunnel field-effect transistors (TFETs) realized on the same InAs/Al0.05Ga0.95Sb technology platform is carried out using a full-quantum simulator. In order to capture the effect of interface/border traps on the device electrostatics in a way consistent with the ballistic approach, the classical Shockley-Read-Hall theory has been properly generalized. Traps induce a significant reduction on the ON-current; however, the inclusion of a uniform strain induces a remarkable current enhancement able to completely recover the current degradation.
This article illustrates the basic concepts underlying the operation of non-volatile memories (NV... more This article illustrates the basic concepts underlying the operation of non-volatile memories (NVM). After a classification of NVMs based on their functional properties with respect to the programming and erasing operations, the treatment addresses the structure, operation principles, circuit organization and reliability issues of read-only memories (ROM), electrically programmable read-only memories (EPROM), electrically programmable and erasable read-only memories (EEPROM) and flash memories, including both the NOR and NAND organizations. A final section is devoted to non-conventional memories, including magnetic, ferroelectric and phase-change memories, which are still in an early development stage
This article illustrates the operation principles, circuit organization, performance and reliabil... more This article illustrates the operation principles, circuit organization, performance and reliability issues of volatile memories, including the 6- and 4-transistors static RAM (SRAM), the 3- and 1-transistor dynamic RAM (DRAM), and the 10-transistor content addressable memory (CAM). First, the SRAM general features are discussed, including access time, packing density, and reliability issues. Also, a description of the basic cell topologies, cell array organization, and sense amplifier operation is provided. The treatment of DRAMs addresses the structural and functional properties of the one-transistor memory cell, the organization of the cell array, the structure and operation of the sense amplifier and the memory architecture. Finally, a short description of the structure and operation of associative memories is provided, as well as their basic application as a tag memory of set-associative caches
Aim of this work is to present a novel simulation tool based on the deterministic solution of the... more Aim of this work is to present a novel simulation tool based on the deterministic solution of the Boltzmann transport equation for electrons in the whole semiconductor-insulator structure. Full-band density of states and group velocity for SiO 2 have been incorporated, allowing for an accurate description of the distribution function on an extended range of energies.
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Papers by E. Gnani