Introduction to Logic gates

Introduction to Logic gates Theory Logic gates are circuits used to implement a Boolean function. It is a digital circuit which may have been more than one input but only one output. It has a set of two elements 0 and 1, with operations are applicable to gate type circuits. These logic gates which form the fundamental parts of logic circuits are constructed from diodes, resistors and transistors in such a way that the circuit output is a result of basic logic operations performed on the inputs. Experimentally the logic operations can be tested by verifying its truth table. A truth table is a tabular representation of operation performed by the logic gates. 1. OR – Gate (IC – 7432): The logic symbol along with pin configuration of a dual input OR gate is shown in fig 1.1 In an OR gate, the output is high when either of the input or all inputs are high and output is low when all inputs are low. It is represented by. A B A+B 0 0 0 1 1 1 1 0 1 1 1 1 Figure 1.1 2. AND – Gate(IC – 7408): The logic symbol along with pin diagram of a dual input AND gate is shown in fig 1.2. In an AND gate, the output is high only when all inputs are high and is low when either of the inputs are low. It is represented by. A B 0 0 0 0 1 0 1 0 0 1 1 1 Figure 1.2 3. NOT – Gate(IC – 7404): The circuit has only one input one output. The output is always the complement of input. i.e. if input is low output will be high and if input is high the output will be low. Logic symbol along with pin configuration is shown in fig 1.3. Symbol is A 0 1 1 0 Figure 1.3 4. NAND – Gate(IC – 7400): The logic symbol and pin configuration is shown in fig 1.4. The NAND gate is complemented AND gate. It is represented as. A B 0 0 1 0 1 1 1 0 1 1 1 0 Figure 1.4 5. NOR – Gate (IC – 7402): The logic symbol and pin configuration of a dual input NOR gate is shown in fig 1.5. NOR gate is a complemented OR gate. It is represented by the symbol. A B 0 0 1 0 1 0 1 0 0 1 1 0 Figure1.5 6. EX-OR – Gate(IC – 7486): The logic symbol and pin diagram are shown in fig 1.6. The output of an EX-OR gate is high only when either of the inputs are high and the output is low when all the inputs are high or low. The notation used to represent is. A B 0 0 0 0 1 1 1 0 1 1 1 0 Figure1.6 NAND Gate as Universal Block Input Output 0 1 1 0 1) NOT Gate 2) AND Gate Input Output A B 0 0 0 0 1 0 1 0 0 1 1 1 3) OR Gate Input Output A B 0 0 0 0 1 1 1 0 1 1 1 1 4) EX-OR Gate Input Output A B 0 0 0 0 1 1 1 0 1 1 1 0 5) EX-NOR Gate Input Output A B 0 0 1 0 1 0 1 0 0 1 1 1 NOR Gate as Universal Gate Input Output 0 1 1 0 1) NOT Gate Input Output A B 0 0 0 0 1 1 1 0 1 1 1 1 2) OR Gate 3) AND Gate Input Output A B 0 0 0 0 1 0 1 0 0 1 1 1 4) EX-OR Gate Input Output A B 0 0 0 0 1 1 1 0 1 1 1 0 Input Output A B 0 0 1 0 1 0 1 0 0 1 1 1 5) EX-NOR Gate Exp No: 1 DESIGN AND TESTING OF RECTIFIER CIRCUITS Aim: To determine the ripple factor, efficiency and regulation of the full wave and bridge rectifier circuits with and without capacitor. Components: Name Description Quantity Diode BY 127 4 Resistors 1KΩ 1 Capacitors 100μF 1 Function Generator 3MHz 1 DC Voltage source - 1 CRO 20MHz 1 Full Wave Rectifier (Center Tapped) without filter: Vm = VNOLOAD = Full Wave Rectifier (Center Tapped) with filter Bridge Rectifier without filter Bridge Rectifier with filter Procedure: Without Capacitor Filter Rig up the circuit as shown in the circuit diagram. To test the transformer, give 230V, 50Hz supply to the primary coil of the transformer and observe the AC waveform of rated value at the secondary of the transformer on a CRO. Connect CRO across the load resistance R. Observe the waveform keeping the CRO in DC mode. Note down its amplitude, Vm and frequency. Switch the CRO to AC mode and observe the waveform. Note down its amplitude Vm, frequency. Use relevant formula to find Vdc and Vrms for half wave, full wave & bridge rectifiers & draw the waveforms. Calculate the Ripple factor, Regulation and Efficiency by using the formula& compare it with respective theoretical values. With Capacitor Filter Connect the capacitor across the load resistance (with polarity of the capacitor as shown in circuit diagram). Switch the CRO in DC mode. Measure the peak amplitude with respect to ground reference. The peak to peak voltage of the ripple is measured from the CRO. Calculate the Ripple factor and compare it with theoretical value. Result: Parameters Full Wave Bridge Ripple factor without filter Theoretical Practical Ripple factor with filter Theoretical Practical Percentage Efficiency Theoretical Practical Percentage Regulation Practical Conclusion: VIVA QUESTIONS: What is filter? What is the efficiency of bridge rectifier? What is the value of PIV of a center tapped FWR? In filters capacitor is always connected in parallel, why? What is the purpose of Center Tapped transformer? What is Regulation? What is the location of poles of filter in S-plane? What is the output of FWR with filter? Is it unidirectional? What are the advantages and disadvantages of center tapped full-wave rectifiers compared with Bridge rectifiers? List the Merits and Demerits of Full-wave Rectifier Over Half-Wave Rectifier Date of completion Signature of Staff Remarks Rough Work: Exp No: 2 TESTING OF DIODE CLIPPING & CLAMPING CIRCUITS CLIPPING CIRCUITS: Aim: Design and test diode clipping circuits for a given reference voltage. Components: Name Description Quantity Diode 1N4007 2 Resistors 100 KΩ 1 Function Generator 3MHz 1 DC Voltage source (Dual) - 1 CRO 20MHz 1 Series Clippers: Positive clipping with given positive reference level Positive clipping with given negative reference level Negative clipping with given positive reference level Negative clipping with given Negative reference level Parallel Clippers: Positive clipping with given positive reference level Positive clipping with given negative reference level Negative clipping with given negative reference level Negative clipping with given positive reference level Double clipper, with given reference level Voltage VIN=5V, VR1=2V, VR2=3V Procedure: Connect the circuit as shown in circuit diagram. Set AFO to sinusoidal output and adjust the voltage to VIN (p-p) and voltage VR. Observe the output waveform along with input waveform using CRO. Draw necessary waveforms on graph sheet. Repeat the procedure for different clipper circuits. Result: Conclusion: CLAMPING CIRCUITS: Aim: Design a positive/negative clamping circuits for a given reference voltage. Components: Name Description Quantity Diode 1N4007 1 Resistors 100 KΩ 1 Capacitors 0.1 µF 1 Function Generator 3MHz 1 DC Voltage source (Dual) - 1 CRO 20MHz 1 Design: Let the input voltage be 10V (p-p) sine wave at 1 KHz For Clamping RC>>τ Let C=0.1μF So R>100KΩ Let R=100KΩ Positive Clamping Clamps the negative peak of the input voltage Circuit Diagram: Expected Waveforms: Clamper Output with VR=0 Clamper Output with VR>0 (+ve Voltage) Clamper Output with VR<0 (-ve Voltage) Negative Clamping Circuit Diagram: Expected Waveforms: (a)Clamper Output with VR=0 (b)Clamper Output with VR>0 (+ve Voltage) (c)Clamper Output with VR<0 (-ve Voltage) Procedure: 1. Connect the circuit as shown in circuit diagram. 2. Set AFO to sinusoidal output and adjust the voltage to VIN=10V(p-p) Set the RPS to voltage approximately to 2V Observe the output waveform along with input waveform using CRO. Draw necessary waveforms on graph sheet. Repeat the procedure for negative and positive clamper circuits. Result: Conclusion: VIVA QUESTIONS: What are clipping circuits? Mention the applications of clipping circuits? What are clamping circuits? What is the other name of clamping circuits? Mention the applications of clamping circuits? Date of completion Signature of Staff Remarks Rough Work: Exp No.3 RC-COUPLED AMPLIFIER Aim: Wiring of a RC coupled single stage BJT amplifier and determination of the gain frequency response, input and output impedances. Components: Name Description Quantity Transistor BC 107 1 Resistors 470 2.2k 10k 47k 820 1 1 1 1 1 Capacitors 15F 10F 1 2 Circuit diagram: Design: Let VCE 2=5V, IC 2=2mA ,VCC =10V. Av=-50, fL = 100Hz. We have VCC VE VCC. 1. To find the value of RE:- Let VE=VCC=10V=1V. RE= ==500 Use RE = 470 2. To find the value of RC:- VCE =VCC-ICRC-IERE RC = = = 2 k. Use RC = 2.2 k 3. Use BC107 transistor, Since its minimum guaranteed hFE(=100) is more than the required gain(=50) of the amplifier. IB(dc) =IC or IB (hFE) =IC ie IB= = = 20A. 4. Calculations of resistor values R1 and R2 :- We have IR2 ≥ 10IB Let IR2 = 10IB IR2 = 10(20*10) = 200 A. Also VB = VE+VBE = 1 V+0.7V =1.7V R2= VB/IR2 = 1.7V/200A = 8.5 k Use R2 = 10 k R1 = (VCC-VB)/IR2 = (10-1.7)/ 200A = 41.5 k Use R1= 47 k 5. Calculation of load resistance RL: AV= - (rc/re) =- = Substitute for RC, IE and AV RL =850 Use RL =820 6.Selection of capacitors, C1, C2, and CE Selection of C1: XC1 ≤ Zi/10, Where Zi = R1|| R2|| hie =R1|| R2|| hFEre =R1|| R2|| re R1=41.5 k , R2=8.5 k , hFE =100 re = 26mV/IE 26mV/IC = (26 mV/2mA) = 12.5 Substituting these, we have Zi=1.1 k XC1 ≤ XC1= ≤0.11 k or C1 ≥ 14µF Select C1 =15µF Selection of C2: XC2 ≤ where ZO =RC =2.2 k XC2 =≤= C2 ≥7.2µF Select C2 =10µF Selection of CE: XCE ≤ ≤ or 2ПfCE ≥ CE ≥ → CE ≥ 3.38µF Select CE= 10µF Tabular Column: Vin= 1.4 Volts Sl No Frequency(Hz) Vo(Volts) Gain AV= VO/Vi Gain(db)=20log( VO/Vi) 50 60 70 80 100 150 200 500 700 1k 1.5k 100k 200k 300k 400k 500k Frequency Response Graph: Input mpedance Measurement: Output Impedance Measurement: Procedure: A] Maximum Signal Handling Capacity(Vin max): 1. Connect the circuit as shown in ckt fig. 2. The Vcc and Vin are switched on. 3. The voltage Vo is observed on the CRO. 4. The amplitude of the input is varied and the output is observed. 5. For a particular value of input voltage, the output starts clipping. 6. The voltage just before the clipping is noted down. This gives Vinmax. 7. The amplitude of input voltage is reduced. B] Frequency Response 1. Input voltage less than the Vinmax is applied. 2. The amplitude of the input is kept constant and the frequency is varied from 50 Hz to500kHz. 3. Each time the corresponding amplitude of V0 is noted down. 4. The amplitude is reduced to zero and the supply is switched off. 5. Gain in dB is calculated using the formula, Av =20log (Vo/Vin). 6. Frequency response curve is plotted. C] Input Impedance: 1. The amplifier circuit is rigged up. 2. The input frequency is kept constant at 1 KHz, the voltage Vin less than Vinmax is applied. 3. The DRB is connected in series with the input as shown in the figure. 4. The DRB is varied until the output becomes half of the previous value with the same input voltage as in step 2. 5. The DRB resistance will give the input impedance of the amplifier. 6. The input voltage is reduced and supply is switched off. D] Output Impedance: 1. The amplifier circuit is rigged up. 2. The input frequency is kept constant at 1 KHz, the voltage Vin less than Vinmax is applied. 3. The DRB is connected across the output terminals as shown in the figure. 4. The DRB is varied until the output becomes half of the previous value with the same input voltage as in step 2. 5. The DRB resistance will give the output impedance of the amplifier. 6. The input voltage is reduced and supply is switched off. Result: Maximum signal handling capacity= Mid band gain of the amplifier= Bandwidth of the amplifier= Input impedance= Output impedance= Conclusion: VIVA QUESTIONS: What is the necessity of cascading? What is 3dB bandwidth? Why RC coupling is preferred in audio range? Which type of coupling is preferred and why? Explain various types of Capacitors? What is loading effect? Why it is known as RC coupling? What is the purpose of emitter bypass capacitor? Which type of biasing is used in RC coupled amplifier? Date of completion Signature of Staff Remarks Rough Work: Exp No: 4 RC PHASE SHIFT OSCILLATOR Aim: To design and test the RC Phase shift Oscillator for the given frequency. Components: Name Description Quantity Transistor BC107 1 Resistors 47KΩ 2.2KΩ 10KΩ 680Ω 4.7KΩ 5K POT 1 1 1 1 2 1 Capacitors 10μF 0.01μF 1 3 DC Voltage Source 0-30V 1 CRO 20MHz 1 Circuit Diagram: Design of Amplifier Stage VCC= 12V, IC= 2mA, VRC= 40% of VCC = 4.8V VRE = 10% of VCC 1.2V, VCE = 50% of VCC= 6V VRC = ICRC= 4.8V RC= 2.4KΩ 2.2KΩ VRE =IERE =1.2V RE =600Ω, 620Ω VR2 = VBE +VRE = 0.7+1.2 =1.9V VR2 =9IBR2 =1.9V R2=10KΩ VR1=VCC-VR2 =10.1V VR1 =10IBR1 =10.1V R1=4.7KΩ Required Gain =50 RL=845Ω Calculation of resonance frequency and Beta or feedback factor Fig: Feedback network for RC oscillator Procedure: Set up the amplifier part of the oscillator and test the dc condition. Ensure that the transistor is working as an amplifier with the required gain. Connect the feedback network and observe the sine wave on the CRO and measure its amplitude and frequency. Observe the waveform at the base and collector of the transistor simultaneously on the CRO and notice the phase shift. Result: Frequency of Oscillations (practical) = Frequency of Oscillations (Theoretical) = Peak value of the signal= Conclusion: VIVA QUESTIONS: What is the frequency of RC phase shift oscillator? What is a phase shift oscillator? Why RC oscillators cannot generate high frequency oscillations? What are the applications of RC phase shift oscillators? What phase shift does RC phase shift oscillator produce? How is phase angle determined in RC phase shift oscillator? Why we need a phase shift between input and output signal? Date of completion Signature of Staff Remarks Rough Work: Exp No: 5 CRYSTAL OSCILLATOR Aim: To design and test the performance of BJT - Crystal Oscillator for f0>100 kHz Components: Name Description Quantity Transistor CL100 1 Crystal 2 MHz 1 Resistors 2.2kΩ 82kΩ 18kΩ 470Ω 1kΩpot 1 1 1 1 1 Capacitors 0.01µF 0.1µF 47µF 1 1 1 DC Voltage Source 0-30V 1 CRO - 1 Circuit Diagram: Design: Given VCC=10V, β=200, IC=2mA To findRE VRE===1V IERE=1V IE=IC RE=== = 0.5x103=500Ω Choose RE=470Ω To findRC Apply KVLto loop VCC- IC RC- VCE- VRE=0 10V-2x10-3 RC-5V-1V=0 4V-2x10-3 RC=0 RC=2KΩ Choose RC=2.2KΩ From the biasing circuit, VB=VBE+VRE VB=0.7+1 VB=1.7V To find IB IB=== 0.01mA Assume 10 IB flows through R1 R1====83KΩ Choose R1=82KΩ Assume 9 IB flows through R2 R2====18KΩ R2=18KΩ Assume Coupling CapacitorC2=0.001C1=100PF Expected Waveform: f=1/T Hz. Procedure: Make the connections as shown in the circuit diagram. Vary the 1 KΩ potentiometers to get an undistorted sine wave at the output. Note down the frequency of the output wave and compare it with the crystal frequency. Result: Theoretical frequency: Practical frequency: Conclusion: VIVA QUESTIONS: What is crystal osscillator? What is Peizo Electric Effect? What are the merits & demerits of Crystal oscillator? What are the applications of crystal oscillator? Date of completion Signature of Staff Remarks Exp No: 6 CLASS-B PUSH PULL AMPLIFIER Aim: Testing of a transformer less Class-B push pull amplifier and determine its conversion efficiency. Components required: Name Description Quantity Transistors SL100 SK100 1 1 Resistor 470Ω 2 DC power supply 0-30V 1 Ammeter 0-2A 1 CRO 20MHz 1 Signal generator 3MHz 1 Decade Resistance Box 1 Circuit diagram: Expected waveform: Procedure: Connect circuit as shown in the diagram. Measure a sine wave signal of 5V, 5 kHz and apply it as input (Vi) to the circuit. Observe the crossover distorted sine wave as shown on the CRO, takedown same waveform on the tracing sheet. By varying the Value of DRB (RL), note down the value of Vo(p-p) across DRB and calculate conversion efficiency. Tabular column: Sl.No RL(DRB)Ω V0(p-p)V η=πV0(p)/4VCC *100 1. 2. 3. Result: Conclusion: VIVA QUESTIONS: What is cross over distortion? Classify Amplifiers? What is the drawback of class B amplifier? How is this minimized? Date of completion Signature of Staff Remarks Rough Work: Exp No: 7 SIMPLIFICATION, REALIZATION OF BOOLEAN EXPRESSIONS USING LOGIC GATES/UNIVERSAL GATES Date : Aim: To study the operation of various logic gates using respective IC’s and verification of truth table. Apparatus: Digital Trainer Kit Patch cords Digital IC’s 7432 – OR 7408 – AND 7404 – NOT 7400 – NAND 7402 – NOR 7486 – EX-OR 7410 – NAND 3 INPUT 7427 – NOR 3 INPUT Pin Diagram of Three input NAND Gate Procedure: 1. The connections are made as per logic diagram. 2. The power supply is switched ON. 3. Truth table for given expression is verified for the different input combinations. Simplify the given Boolean expression and build the logic circuit. Kmap Simplification (in both forms): Realization using basic gates (SOP): Realization using basic gates (POS): Realization using NAND gates only: Realization using NOR gates only: Result: VIVA QUESTIONS: Why NAND & NOR gates are called universal gates. Realize the EX – OR gates using minimum number of NAND gates. Give the truth table for EX-NOR and realize using NAND gates? What are the different methods to obtain minimal expression? What is a Minterm and Maxterm. State the difference between SOP and POS. What is meant by canonical representation? What is K-map? Why is it used? Date of completion Signature of Staff Remarks Rough Work: Exp No: 8 REALIZATION OF HALF/FULL ADDER AND HALF/FULL SUBTRACTOR USING LOGIC GATES Date : Aim: To design half adder and full adder using logic gates. Apparatus: Digital Trainer Kit Patch cords. Digital IC’s 7486 – EX-OR 7432 – OR 7408 – AND 7404 – NOT Half Adder: Truth Table Logic Circuit: Input Output A B Sum Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Sum = Carry = Full Adder: Truth Table Logic Circuit: Input Output A B C Sum Carry 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Sum = Carry = Full adder using NAND gates only: Half Subtractor: Truth Table Input Output A B Difference Borrow 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 Logic Diagram: Full Subtractor: Truth Table Input Output A B C Difference Borrow 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 Logic Diagram Full Subtractor using NAND gates only: Procedure: 1. Connections are made as shown in the figure. 2. Note down the output for different combinations of the input bits. 3. Compare it with the truth table and verify the output. Implementing full adder using Two Half adders: Expression: Logic Circuit: Implementing full Subtractor using Two Half subtractors: Expression: Logic Circuit: Result: VIVA QUESTIONS: Draw circuit diagram of Half Adder circuit? Draw circuit diagram of Full Adder circuit? Draw Full Adder circuit by using Half Adder circuit and minimum no. of logic gate? Write Boolean function for half adder? Q.5 Write Boolean function for Full adder? Design the half Adder & Full Adder using NAND-NAND Logic. Draw circuit diagram of Half Subtractor circuit? Draw circuit diagram of Full Subtractor circuit? Draw Full Subtractor circuit by using Half Subtractor circuit and minimum no. of logic gate? Write Boolean function for half Subtractor? Write Boolean function for Full Subtractor? Date of completion Signature of Staff Remarks Rough Work: Exp No: 9 i) REALIZATION OF PARALLEL ADDER/ SUBTRACTORS USING 7483 CHIP ii) BCD TO EX-3CODE CONVERSION AND VICE VERSA iii) REALIZATION OF BINARY TO GRAY CODE CONVERSION Date : Aim: Verification of parallel adder/subtractor using IC – 7483 and thereby realize code conversions. Apparatus: Digital Trainer Kit Patch cords. Digital IC’s 7486 – EX-OR 7483 – PARALLEL ADDER 7432 – OR 7408 – AND 7404 – NOT 7411 – AND 3 I/P Logic diagram (Refer data sheet for pin diagram of IC 7483) Truth Table for Adder Inputs Inputs Outputs A3 A2 A1 A0 B3 B2 B1 B0 Cout S3 S2 S1 S0 Truth Table for Subtractor Inputs Inputs Outputs A3 A2 A1 A0 B3 B2 B1 B0 Cout S3 S2 S1 S0 Procedure: The Connections are made as per logic diagram. The power supply is switched ON. Four bit addition is performed by giving inputs to IC 74LS83. Four bit parallel adder/subtractor is designed using EX-OR gates, the input to which are the four bits of B. To perform addition set m=0and to perform subtraction set m=1. BCD to Excess 3 code conversion: Truth Table BCD Excess 3 code Decimal B3 B2 B1 B0 E3 E2 E1 E0 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 Excess-3 to BCD Conversion Decimal E3 E2 E1 E0 B3 B2 B1 B0 0 0 0 1 1 1 0 1 0 0 2 0 1 0 1 3 0 1 1 0 4 0 1 1 1 5 1 0 0 0 6 1 0 0 1 7 1 0 1 0 8 1 0 1 1 9 1 1 0 0 Truth Table Realization using IC 7483 Procedure: Apply BCD code as first operand (A) and and binary 3 as second operand(B) and Cin=0 for realizing BCD to Excess-3-code. Apply Excess-3-code as first operand (A) and binary 3 as second operand(B) and Cin=1 for realizing Excess-3-code to BCD. Verify the Truth Table and observe the outputs. Result: VIVA QUESTIONS: What is Excess-3 code? Why it is called Excess-3 code? What is the application of Excess-3 Code? Excess-3 code is Weighted or Unweighted? What is the difference between serial and parallel addition/subtraction? What is a ripple Adder? What are its disadvantages? Binary to gray code conversion Truth Table: D C B A Y3 Y2 Y1 Y0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 B’A’ B’A BA BA’ D’C’ D’C DC DC’ B’A’ B’A BA BA’ D’C’ D’C DC DC’ Y3= Y2= B’A’ B’A BA BA’ D’C’ D’C DC DC’ B’A’ B’A BA BA’ D’C’ D’C DC DC’ Y1= Y0= Logic Diagram Gray code to binary conversion Truth Table: Y3 Y2 Y1 Y0 D C B A 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 0 1 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1 0 0 1 0 1 1 1 1 0 1 1 0 0 1 1 1 1 0 1 0 0 0 1 1 1 1 Y1’Y0’ Y1’Y0 Y1Y0 Y1Y0’ Y’3Y’2 Y’3Y2 Y3Y2 Y3Y’2 Y1’Y0’ Y’1Y0 Y1Y0 Y1Y0’ Y’3Y2’ Y3’Y2 Y3Y2 Y3Y2’ A= B= Y1’Y0’ Y’1Y0 Y1Y0 Y1Y0’ Y3’Y2’ Y3’Y2 Y3Y2 Y3Y2’ Y’1Y0’ Y1’Y0 Y1Y0 Y1Y0’ Y3’Y2’ Y’3Y2 Y3Y2 Y3Y2’ C= D= Logic Diagram Procedure: The Connections are made as per given diagram (i). The power supply is switched ON. By applying the different input combinations to the given circuit, the concerning truth table is verified for binary to gray code conversion. Now the connections are made as per fig (ii) Different input combinations are applied and the truth table for gray code to binary conversions is now verified. Result: VIVA QUESTIONS: What are code converters? What is the necessity of code conversions? What is gray code? Covert a binary number 101101 to its equaling gray code. Date of completion Signature of Staff Remarks Rough Work: Exp No: 10 DESIGN AND TESTING OF RING COUNTER/JOHNSON COUNTER Date : Aim: To design and implement Ring and Johnson Counter using 4 – bit Shift register. Apparatus: Digital Trainer Kit Patch cords. Digital IC’s IC 7495 IC 7404 - NOT Ring Counter Logic Diagram Clock Time Outputs Q3 Q2 Q1 Q0 Clock 2 t0 (Starting State) t1 (after 1st clock) t2 (after 2nd clock) t3 (after 3rd clock) t4 (after 4th clock) Ds Serial Input data (to be right shifted) D3, D2, D1, D0 Parallel data input to be loaded into the shift register m Mode control Keep m=1 for loading parallel data and to enable clock2. m=0 to enable clock 2. Clock2 For loading input data and for shift left of data Clock1 For right shift of data. Q3. Q2, Q1, Q0 Parallel output of shift register. Procedure: Mode control is made 1 Parallel inputs say 0001 are given to D3, D2, D1, D0 inputs of 7495. Clock 2 is pulsed once. Now D3, D2, D1, D0 parallel inputs appear on Q3, Q2, Q1, Q0 lines. Clock 1 of 7495 is connected to pulsar. Mode control is made 0. When clock pulses are applied ‘1’ circulates around. Johnson Counter Logic Diagram Clock Time Outputs Q3 Q2 Q1 Q0 Clock 2 t0 (Starting State) t1 (after 1st clock) t2 (after 2nd clock) t3 (after 3rd clock) t4 (after 4th clock) Procedure: Mode control is made 1 Parallel inputs say 0000 are given to D3, D2, D1, D0 inputs of 7495. Clock 2 is pulsed once. Now D3, D2, D1, D0 parallel inputs appear on Q3, Q2, Q1, Q0, lines. Clock 1 of 7495 is connected to the pulsar. Mode control is made 0. When clock pulses are applied ‘1’ circulates around clock as shown. Result: VIVA QUESTIONS: What is modulus of a number. What is a shift register. Explain how a shift register can be used as ring and Johnson counter Give the applications of Johnson and ring counters. What are the other technical names for Johnson counter? A ring counter consisting of five Flip-Flops will have how many states? An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds. The pulse width of the strobe is 50ns. The frequency of the input signal which can be used for proper operation of the counter is approximately? Date of completion Signature of Staff Remarks Rough Work: Exp No: 11 DESIGN AND TESTING OF SEQUENCE GENERATOR Date : Aim: To design and set up a sequence generator using IC-7495 Apparatus: Digital Trainer Kit Patch cords. Digital IC’s IC 7495 IC 7486 – EX-OR IC 7408 - AND IC 7404 – NOT To generate 100010011010111: No. of clocks Flip Flop Outputs Serial Output Q3 Q2 Q1 Q0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 1 1 0 1 1 0 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0 1 K-Map Y = Logic Diagram: Procedure: Given Sequence is 100010011010111: Mode control is made 1. Parallel inputs are given at D3, D2, D1, D0. Clock is pulsed once. The parallel inputs appear at Q3, Q2, Q1, Q0. Mode is made 0. As the pulse is applied, required sequence is observed on Q3 line. To generate the sequence 0 – 8 – 12 – 14 – 15 – 0 Truth Table: Present State Next State Q3 Q2 Q1 Q0 D3 D2 D1 D0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 0 K-Map’s Logic Diagram To get a sequence 0 – 8 – 12 – 14 – 15 – 0 Mode is made 1 Clock 2 is pulsed and outputs are observed at Q3, Q2, Q1, Q0 Apply continuous clock pulse of frequency 1 KHz and verify the truth table. Observe the waveforms at Q3, Q2, Q1, Q0 Result: VIVA QUESTIONS: What is the necessity for sequence generation? What are PISO, SIPO, and SISO with respect to shift register? Differentiate between serial data & parallel data. What is the significance of Mode control bit? How many Flip-flops are present in IC 7495? Date of completion Signature of Staff Remarks Rough Work: Exp No: 12 REALIZATION OF 3 BIT COUNTERS AS A SEQUENTIAL CIRCUIT AND MOD-N COUNTER DESIGN USING 7490, 74192, 74193 Date : Aim: To design and study various 3 bit synchronous counters using various IC’s and use it as: a) Decade counter with BCD count sequence b) Divide by N counter. Apparatus: Digital Trainer Kit Patch cords. Digital ICs 7490 7400 – NAND 74192 74193 Pin Diagram of 7490: Truth Table: No of clock Q3 Q2 Q1 Q0 0 1 2 3 4 5 6 7 8 9 10 Timing Diagram: Procedure: Start the count sequence from Q3Q2Q1Q0---0000. MS1 and MS2 inputs are connected to ground. MR1 is connected to logic 1 and MR2 to logic 0 for count mode. Clock input is given to input A and output Q0 and input B are shorted. Circuit then acts as mod 10 counter with BCD count sequence. Verify the truth table and observe the waveform Divide by N counter (MOD 6) The output Q1 and Q2 are connected to reset inputs MR1 and MR2 through 2NAND gates in series. As soon as Q1 and Q2 both becomes 1, the counter is reset to 0000. Logic Diagram: Study of IC 74192: Function Table: Load Clear ClockUp Clock Down mode X 1 X X Reset to Zero 1 0 1 1 Up count 1 0 1 1 Down count 0 0 X X Reset 1 0 1 1 Stop count Truth Table for up counter: No of clocks Q3 Q2 Q1 Q0 0 1 2 3 4 5 6 7 8 9 Procedure: Realization of 74192 as a mod-10 counter (UP-counter): For up counter, after clearing the counter outputs keep clear=0, load=1. Keep clock down=1 and apply clock to clock up input. Observe the count sequence at the outputs Q3, Q2, Q1, and Q0. If the output changes from 1001 to 0000, carry=0 else carry=1. Truth Table for down counter: No of clocks Q3 Q2 Q1 Q0 0 1 2 3 4 5 6 7 8 9 Realization of 74192 as a mod-10 counter (DOWN-counter): For down counting, after clearing the output keep clear=0, load=1. Keep clock up=1 and apply clock to clock down input. Observe the count sequence at the outputs Q3, Q2, Q1, and Q0. If the outputs Q3, Q2, Q1, Q0 changes from 0000 to 1001 borrow=0, else borrow=1. IC 74193 Truth Table for up counter: No of clocks Q3 Q2 Q1 Q0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Truth Table for down counter: No of clocks Q3 Q2 Q1 Q0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Procedure: Realization of 74193 as UP-counter: For up counter, after clearing the counter outputs keep MR=0, PL=1. Keep clock down (Cpd) =1 and apply clock to clock up (Cpu) input. Observe the count sequence at the outputs Q3, Q2, Q1, and Q0. If the output changes from 1111 to 0000, Tcu=0 else Tcu=1. Realization of 74193 as DOWN-counter: For down counting, after clearing the output keep MR=0, PL=1. Keep clock up (Cpu) =1 and apply clock to clock down (Cpd) input. Observe the count sequence at the outputs Q3, Q2, Q1, and Q0. If the outputs Q3, Q2, Q1, Q0 changes from 0000 to 1111 Tcd=0 else Tcd=1. Design up counter for preset value 0010 and N=10 CIRCUIT DIAGRAM: Truth Table: No of clocks Q3 Q2 Q1 Q0 0 1 2 3 4 5 6 7 8 9 10 11 Design of down counter for preset value 1011 and N=10 CIRCUIT DIAGRAM: Truth Table: No of clocks Q3 Q2 Q1 Q0 0 1 2 3 4 5 6 7 8 9 10 11 Result: VIVA QUESTIONS: What is an asynchronous counter? How is it different from a synchronous counter? What are the advantages of synchronous counters? What is an excitation table? Write the excitation table for D, T FF What is a presettable counter? What are the applications of presettable counters? Explain the working of IC 74193. Date of completion Signature of Staff Remarks Rough Work: Electronics Laboratory Manual – 15EEL38 III Semester, E&EE, CEC Page 63