Customizing Controllers to Increase Processor Performance

Rishabh Badjatya et al. / International Journal of Engineering Science and Technology (IJEST) CUSTOMIZING CONTROLLERS TO INCREASE PROCESSOR PERFORMANCE RISHABH BADJATYA Department of Electronics & Communnication Engineering. Shri Vaishnav Institute of Science & Technology,Indore- 453331 [email protected] Mr. PREET JAIN Department of Electronics & Communnication Engineering. Shri Vaishnav Institute of Science & Technology,Indore- 453331 [email protected] Abstract: This paper describes the performance enhancement of a processor in context of enhancing controller that reduces the power consumption as well as increase the speed of a processor. Here we are devising the method which will increase the performance of processor usually when it interacts with slower peripherals. Keywords: enhancement, processor, speed, controller. 1. Introduction It has been found that while driving slow peripheral devices, it take lots of clock cycle which consume power as well as slow the speed of processor. One of the key solutions for improving the processor performance is to customize the controller so that processor doesn’t need to look at the slow peripheral. 2. Literature Survey Majorly the main concern of the performance of processor is on architecture, designer mainly concerned on deep pipelining, cache memory, multithreading, reducing CPI and branch prediction. Processor performance can be increase by optimization of register file [1]. This will increase access time and reduce power consumption. Increasing processor performance involves increasing the frequency by implementing deeper pipelines [2]. He also describe that processor performance is a function of pipeline depth and cache size. A multi-bank register file architecture for increasing the register-access clock frequency by up to 95 % and an access arbitration method for avoiding degradation of the cycle number based processor performance [3].To improve the performance of microprocessor, many kinds of novel architecture, such as multi-thread processor, CMP (Chiplevel multiprocessing), PIM (Processing In Memory), and reconfigurable computing processor, have been proposed [4]. In this paper, processor performance improvement has been shown in context of slow peripheral devices. 3. Design Here is the example of one of the slow peripheral available i.e. interfacing of LCD with microcontroller or microprocessor which is majorly used device in any embedded design. Normally embedded designer required to write code to interact with LCD in the following way, Step 1: Assert RS Step 2: Assert EN Step3: Generate delay for approximately 1 ms Step 4: Dissert EN Step5: Repeat the procedure for updating the Character on to the LCD ISSN : 0975-5462 Vol. 4 No.02 February 2012 663 Rishabh Badjatya et al. / International Journal of Engineering Science and Technology (IJEST) Considering microcontroller single operation cycle to be of 1µs, thus, if designer wants to write 32 letters on to the LCD, excluding initialization phase, it requires 32000 cycles for no operation which is just needed to provide delay between successive write operations on the LCD incomparision with 96 for the actually needed operation. This precious time of processor is wasted just to synchronize the timing of slower peripheral, since it is due to considering the example of a microcontroller which operating at 1 MIPS (Million Instructions Per Second), but in the present situation microcontrollers are being operated at much higher speed than the specified one, so to generate the same delay processor has to waste its time in doing no operation. To overcome from the above situation we can introduce a dedicated controller for the slower peripheral, which could communicate microcontroller at it speed and communicate peripheral with the peripheral speed. In order to prove this concept we had chosen to interact with a slower peripheral like LCD, so we had designed LCD controller which follows the FSM (Finite State Machine) listed below (fig.1) Fig. 1. FSM showing LCD Controller operation Whatever data need to be print on LCD, we’ll first write that data on to the data memory, now to synchronize the speed of controller and the LCD, We had chosen dual port RAM to achieve such kind of configuration, thus with the help of dual port memory, processor need just 8 cycles to transfer 256 bit of ASCII information, after writing data on the memory, processor initiate LCD controller to communicate with LCD (fig.2). Now LCD controller timing and control unit is responsible for generating RS, RW, and EN along with and Data from the memory. Thus processor has been relieved from generating delays to control the successive write on LCD. Fig. 2. Block diagram of LCD interfacing with processor ISSN : 0975-5462 Vol. 4 No.02 February 2012 664 Rishabh Badjatya et al. / International Journal of Engineering Science and Technology (IJEST) 4. Results After implementing design on the target FPGA i.e. Spartan 3A (XC3S700AFG484-4), we find that out of 5888 available slices – RISC processor RISC processor with dedicated controller 726 763 Table1. Shows the comparison of FPGA Resource consumed by Design So Just 37 slices are used by LCD Controller. Simulation results shown below (fig.3) the function of LCD controller which consists of clk, rst, MEM_memwrite, datao, rs and rw. MEM_memwrite is high when data has to be written in RAM. en pin is toggling on every 8-bit data. rs are high when data is data instruction and low when data in command instruction.rw is high to read data from memory of LCD and low for writing of data. Fig. 3.Simulation result of LCD interfacing with processor 5. Conclusion Just by addition of 37 slices of the FPGA resources(fig.4), we have saved 128000 cycles of our processor which is running at 4 MIPS for 32 letter write and we can save 4000 cycles on each successive letter for the LCD. Benefits of asynchronous handshaking, processor free from looking at the slow peripheral devices (SPI, EEPROM, etc.), and 128000 cycles can be used for other work and by designing dedicated controller, we can save processor time. With introduction of such kind of hardware, processor could be relived from doing no operation. Fig.4. Implementation showing the result of LCD Controller. ISSN : 0975-5462 Vol. 4 No.02 February 2012 665 Rishabh Badjatya et al. / International Journal of Engineering Science and Technology (IJEST) 6. References [1] [2] [3] [4] [5] Houman Homayoun, Sudeep Pasricha, MohammadMakhzan, Alex Veidenbaum“Dynamic Register File Resizing and Frequency Scaling to Improve Embedded Processor Performance and Energy-Delay Efficiency” Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE 8-13 June 2008. Eric Sprangle, Doug Carmean. “Increasing Processor Performance by Implementing Deeper Pipelines” 29th Annual International Symposium on Computer Architecture Anchorage, AK, USA - May 25 - 29, 2002. Koh Johguchi, Ken-ichi Aoyama, Tetsuya Sueyoshi, Hans Jürgen Mattausch and Tetsushi Koide “Multi-Bank Register File for Increased Performance of Highly-Parallel Processors” Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European Sept. 2006. YaoYingbiao, Zhang Jianwu “Survey on Microprocessor Architecture and Development Trends” Communication Technology, 2008. ICCT 2008. 11th IEEE International Conference on 10-12 Nov. 2008. ISSN : 0975-5462 Vol. 4 No.02 February 2012 666