Resistive Random Access Memory: A Review of Device Challenges

IETE Technical Review ISSN: 0256-4602 (Print) 0974-5971 (Online) Journal homepage: https://www.tandfonline.com/loi/titr20 Resistive Random Access Memory: A Review of Device Challenges Varshita Gupta, Shagun Kapur, Sneh Saurabh & Anuj Grover To cite this article: Varshita Gupta, Shagun Kapur, Sneh Saurabh & Anuj Grover (2019): Resistive Random Access Memory: A Review of Device Challenges, IETE Technical Review, DOI: 10.1080/02564602.2019.1629341 To link to this article: https://doi.org/10.1080/02564602.2019.1629341 Published online: 25 Jun 2019. Submit your article to this journal View Crossmark data Full Terms & Conditions of access and use can be found at https://www.tandfonline.com/action/journalInformation?journalCode=titr20 IETE TECHNICAL REVIEW https://doi.org/10.1080/02564602.2019.1629341 Resistive Random Access Memory: A Review of Device Challenges Varshita Gupta, Shagun Kapur, Sneh Saurabh and Anuj Grover Department of ECE at IIIT, Delhi 110020, India ABSTRACT KEYWORDS With scaling, existing charge-based memory technologies exhibit limitations due to charge leaking away easily in a smaller device. Therefore, non-charge based memory technologies such as Resistive Random Access Memory (RRAM) become promising for future applications. RRAM is not only more scalable, but is typically faster and consumes less power than the existing memory technologies. However, RRAM suffers from higher impact of variations and reliability issues. In this review paper, we explain the basic aspects of RRAMs, highlight their advantages and elucidate challenges involved in replacing the existing memory technologies with RRAMs. RRAM; Conducting filament; Materials; Variations; Scalability; Resistive switching 1. INTRODUCTION In recent years, innovative applications such as cloud storage, internet of things (IoT), data mining, artificial intelligence etc. have been enabled by the advancements in data storage technology. In general, a system requires both temporary (volatile) and permanent (nonvolatile) storage for its operation. These requirements are currently fulfilled using complementary metal-oxide semiconductor-based (CMOS-based) static random access memory (SRAM), dynamic random access memory (DRAM) and Flash memory [1]. Each of these memories has its own merits and demerits. An SRAM, being a very fast memory, is used for directly interacting with the high speed processor. However, an SRAM is volatile and has a lower density. For large capacity and non-volatile requirements, memories such as Flash are employed. However, a Flash memory is slower than an SRAM [2]. An SRAM cell stores information on the two nodes of a cross-coupled inverter pair. A DRAM cell uses a capacitor to store charge and distinguish between the “0” state and the “1” state. A Flash memory cell stores charge in the floating gate of a transistor and can store different amounts of charge to effectively store more than 1 bit of information per transistor [2]. This charge dependence of the storage mechanisms limit the scaling possibilities of present memory technologies. For example, the SRAM cell scaling is limited by the variability and the consequent impact on the functionality (read/write margins). The DRAM cell scaling is limited by the amount of charge that is stored on the scaled capacitor. The Flash memory scaling is limited due to the requirement of a high electric © 2019 IETE field in the program and the erase operations. Therefore, researchers are actively exploring non-charge-based memories that can be scaled to a greater extent [1,2]. Figure 1 shows different types of charge and non-charge based memories as reported in the “Beyond CMOS” chapter of 2017 international roadmap for devices and systems (IRDS) [1]. It lists down emerging non-volatile memories (NVMs) which can potentially replace the existing charge-based memories, such as ferroelectric RAM (FeRAM), magnetoresistive RAM (MRAM), phase change RAM (PCRAM or PCM) and resistive RAM (RRAM) [3–7]. Among emerging NVMs, RRAM is of great interest because it is scalable, can operate at a higher speed, is CMOS-compatible and consumes less power compared to the existing memory technologies [7]. Therefore, in recent times, extensive research has been carried out on RRAMs, with the focus on improving their performance and removing limitations such as high impact of process-induced variations. The comparison of different types of resistive memories is shown in Table 1. Currently, research on RRAMs is being carried out in several inter-disciplinary areas including material engineering, device optimization and circuit applications. Since RRAMs have a huge potential for future applications, researchers from diverse backgrounds need to comprehend the fundamental aspects of RRAMs and become familiar with the latest research on RRAMs. However, with a plethora of papers appearing on RRAMs, keeping track of the latest research is a challenge. Therefore, in this paper, we carry out an extensive review of the latest 2 V. GUPTA ET AL.: RESISTIVE RANDOM ACCESS MEMORY Figure 1: Memory taxonomy listing various NVMs [1,2] Table 1: Comparison (Table BC2.7 in [1]) of different resistive memories Figure 2: Schematic diagram of RRAM: (a) simple metal–insulator–metal structure and (b) multilayered structure (Aluminium Copper (AlCu), Titanium Nitride (TiN), Hafnium Oxide (HfO2 ), Tungsten (W)) [7,10] between two metal electrodes, as shown in Figure 2(a). The metal electrodes can be Titanium (Ti), Platinum (Pt), etc. [7,10]. The structure of RRAMs can also be in the form of multilayered stacks, as shown in Figure 2(b). The multilayered RRAMs have shown improved uniformity in the device parameters such as SET and RESET voltages, HRS and LRS resistance levels, etc. [11]. research on RRAMs with a focus on fundamental aspects and challenges at the device level. This will be of help not only to the researchers starting to work on RRAMs, but also to the researchers already working on RRAMs by providing a comprehensive review of the important works related to RRAMs, particularly at the device level. The rest of this paper is organized as follows. In Section 2, we describe the operating principle of different types of RRAMs. In Section 3, we give an overview of various figures-of-merit (FOMs) of RRAMs, and in Section 4, we highlight the variability issues in RRAMs. In Section 5, we examine the materials employed in realizing RRAMs. In Section 6, we explain circuit design and applications of RRAMs and conclude in Section 7. 2. OPERATING PRINCIPLE OF RRAM In simple terms, RRAM is a resistance-based device having a metal–insulator–metal (MIM) structure. The insulator is typically an oxide of elements such as Hafnium (Hf), Tantalum (Ta), Titanium (Ti), etc. Other materials such as chalcogenides have also been used as an insulator in RRAMs. Some 2D-materials such as hexagonal boron nitride (h-BN) have also been explored as an insulator in RRAMs [8,9]. The oxide insulator is sandwiched RRAM is based on resistive switching (RS) between two stable states, namely: the high resistance state (HRS) and the low resistance state (LRS). Depending on these states, the device is said to store a bit “1” or a bit “0” [12]. However, multilevel resistive switching for ultra-high-density applications can also be employed in RRAMs. This can be utilized in multibit memories by assigning multiple bits to the different levels of resistance [13–17]. The resistive switching in RRAM is carried out by the SET and the RESET operations. The RRAM operation is enabled after a conducting path is formed inside the insulator when an appropriate bias is applied to the device. It is worth pointing out that the filament-based RRAMs are the most intensely investigated RRAMs in which the conducting path is provided by the conducting filaments (CFs). The formation of CFs is attributed to the defects in the insulator (cations or oxygen vacancies). The mechanism of CF formation is described in detail in the following paragraphs. During the SET operation, the device resistance reduces due to the formation of CFs, the device switches to the LRS, the current flows easily through the device, and the device is said to be in the “ON-state”. During the RESET operation, the device resistance increases due to the rupture of CFs, the device switches back to the HRS, the current flow is obstructed in the device, and the V. GUPTA ET AL.: RESISTIVE RANDOM ACCESS MEMORY device is said to be in the “OFF-state” [7,8,18]. During the SET operation, the current limit, called the compliance current, protects the device from an uncontrolled CF formation and avoids permanent damage to the device [19]. However, some RRAMs can exhibit self-compliance during the SET operation, eliminating the need for an extra circuitry for the current compliance [20]. For RRAM to operate, a one-time step called the forming process needs to be carried out during electrical measurements. In a fresh device, the insulator contains few defects and the current conduction is inhibited. A high voltage forming process is required for the soft breakdown of the insulator layer [21]. This results in increased availability of defects in the insulator and is required for obtaining a high current during regular operation. Once the forming is done, the RRAM works by employing the SET/RESET operations. However, some RRAMs, known as formingfree devices, do not require the forming process [11,13]. The defects in the insulator obtained during fabrication permit easy conduction in these devices and thus can be utilized in the SET/RESET operations without the need of the high-voltage forming process [13]. Depending upon the materials used and the fabrication processes, RRAMs can exploit a variety of physical phenomena in their switching mechanism. Some of the important mechanisms of switching that are exploited in RRAMs are: (1) Thermochemical: The devices that exploit reduction-oxidation (redox) reactions triggered by heat are known as thermochemical RRAMs (TCMRRAMs) [8]. The CF formation/rupture occurs due to the generation-recombination of ions by redox reactions. The redox reactions are accelerated by Joule heating and consequent temperature rise in the insulator [8]. During the RESET operation, the initial dissolution of a CF at a hotspot results in a local reduction in the cross-sectional area leading to a sudden current crowding [22]. This increases the temperature of the CF, which further accelerates their dissolution, resulting in a self-accelerated dissolution process [22]. (2) Electrochemical: The devices that are based on the electric field-induced movement of metallic ions are known as electrochemical metallization RRAMs (ECM-RRAMs) or conductive bridge RRAMs (CBRAMs) [8]. The switching is triggered by cations that are driven by an electric field and form a metallic CF in the insulator [8]. In an ECM-RRAM, the MIM stack is typically composed of an electrochemically active or metallic electrode 3 such as Cu, an inert counter electrode such as Pt and electrolyte sandwiched between them [23]. In the SET operation, the metallic ions from the active electrode diffuse into the insulator and get reduced on reaching the inert electrode, thus forming a CF [8,23]. In the RESET operation, the metallic atoms in the CF get oxidized, thus rupturing the CF and obstructing the flow of current, as shown in Figure 3[8,23]. (3) Valence-change: The devices that are based on the movement of mobile oxygen ions in the insulator are known as valence-change RRAMs (VCM-RRAMs) [8]. When an appropriate bias is applied, oxygen atoms get knocked out from the insulator and move to the electrode leaving behind oxygen vacancies, as shown in Figure 3. Consequently, defects are generated and CFs are formed [12,24]. In a VCM-RRAM, inert electrodes such as Pt are typically used to obstruct the ion flow from the electrodes. However, active electrodes that aid the switching process can also be used [23]. It is important to note that the above mechanisms of switching can also be combined in a single RRAM device. For example, in Ti/ZrO2 /n+ -Si structure, three different resistance states are obtained when a portion of ZrO2 is doped with Cu during fabrication [16]. An ionic filament is formed in the device with an undoped ZrO2 , whereas a metallic filament is formed in the device with Cu-doped ZrO2 [16]. Thus, multilevel stable states can be obtained by utilizing both ionic and metallic filaments in a single RRAM device [16]. Additionally, different types of RRAMs utilize different bias schemes for resistive switching, as illustrated in Figure 4 and described below: (1) Unipolar: In a unipolar RRAM, the SET/RESET operations are triggered by voltage impulses of the same polarity [8,18]. The unipolar characteristics allow obtaining higher integration density in certain applications by employing diodes as the selectors in crossbar arrays and utilizing a simpler control circuitry [25]. (2) Bipolar: In a bipolar RRAM, the SET/RESET operations are triggered by voltage impulses of opposite polarities [8,18]. Typically, bipolar RRAMs are superior to unipolar RRAMs in terms of power consumption, endurance and variability [25,26]. (3) Non-polar: In a non-polar RRAM, the SET/RESET operations can be triggered by voltage impulses of any polarity [18]. The materials such as HfO2 and NiO both exhibit non-polar switching characteristics in a TiN/Ti/Pt/oxide/Pt/TiN stack [27]. 4 V. GUPTA ET AL.: RESISTIVE RANDOM ACCESS MEMORY (4) Threshold RS: A threshold RS device can be SET to a volatile LRS using a voltage impulse. Once the SET voltage is removed, a threshold RS device switches back from the LRS to the HRS [18,28,29]. Additionally, the switching in RRAMs can be filamentary or distributed. In filamentary switching, the formation/rupture of one or more CFs in the insulator is confined to a small location. Therefore, resistance is predominantly area-independent. Typically, filamentary switching is fast and results in a high LRS/HRS current ratio, though it consumes more power due to a high LRS current [8,18,23]. However, distributed switching is a homogeneous phenomenon and takes place in the entire volume of the insulator, and the defects are created laterally or at the same depths within the insulator. In contrast to the filamentary switching, the resistance in the distributed switching depends on the area of the insulator [8,18,23]. Although distributed switching consumes less power in comparison to filamentary switching, the switching speed and the current ratios of filamentary RRAMs are superior [18,30]. It is worthy to point out that a combination of filamentary and distributed switching in a single device can be used to improve the electrical characteristics of the device [30]. 3. KEY FIGURES-OF-MERIT OF RRAM DEVICES Figure 3: Schematic of Resistive Switching (RS) in RRAM for (a) electrochemical (cation-based) RS – SET, (b) electrochemical (cation-based) RS – RESET and (c) valence-change RS – SET, (d) valence-change RS – RESET The characteristics of RRAMs realized using different materials and employing different switching mechanisms vary widely. In literature, there are several demonstrations of RRAMs excelling in terms of individual figuresof-merit (FOM) such as endurance, data retention, speed, power consumption, etc. In this review, we mention some of the best results reported on RRAMs. We also highlight the important factors deciding various FOMs in RRAMs. 3.1 Endurance Figure 4: Illustration of I–V curves for (a) unipolar operation, (b) bipolar operation, (c) non-polar operation and (d) threshold RS (CC denotes compliance current) [18] The endurance of a device is defined as the number of program/erase or SET/RESET cycles it can undergo while staying above a certain resistance ratio [31]. Since the resistance ratio of the device degrades with increasing program/erase cycles, the device is said to have failed when the ON/OFF current ratio reaches below a certain threshold. This threshold can be defined differently for different applications. RRAMs with endurance up to 1012 cycles have been reported in devices employing Pt/Ta2 O5−x /TaO2−x /Pt and Ta/TaOx /TiO2 /Ti stacks [18,32,33]. It has been noted that tantalum oxides typically show very high endurance values when used as the resistive switching layer [18]. V. GUPTA ET AL.: RESISTIVE RANDOM ACCESS MEMORY 3.2 Data Retention Retention is defined as the length of time for which the LRS and the HRS of the RRAM remain stable after the SET/RESET operations [31]. It has been observed that retention in the LRS strongly depends on the compliance current used during the SET operation [28]. Moreover, at high temperatures, the retention time decreases due to a possibility of frequent atomic rearrangements [18]. The projected retention time for RRAMs based on Pt/TaOx /Pt and Pt/Al2 O3 /HfO2 /Al2 O3 /TiN/Si stacks at 85◦ C is 10 years [34,35]. 3.3 Variability One of the biggest obstacles preventing RRAMs from being widely deployed are the variability issues. Similar to CMOS, cell-to-cell variability occurs in RRAMs due to the variations in the fabrication process. However, cycleto-cycle variability is an inherent feature of the resistive switching and is strongly influenced by the applied electrical stresses that control the shape of the CF. Since the formation and rupture of CFs is a stochastic process, controlling their shape is difficult and unpredictable [18,31]. It may be noted that the variability issues are aggravated in multi-bit RRAMs due to decreased resistance window [7]. The variability issues in RRAMs are explained in detail in the following section. 3.4 Scalability RRAMs exhibit high scalability as compared to other memory technologies. Several works have demonstrated successful switching operations in devices scaled to a few nanometres. For example, an Hf/HfOx stack with an area of less than 10 × 10 nm2 is reported to exhibit switching energy per bit < 0.1 pJ and endurance > 5 × 107 cycles [36]. In ECM cells, the maximum theoretical scalability is limited by the discrete Landauer conductance levels (multiples of 2e2 /h) [37]. It is worthy to point out that RS characteristics are often reported for larger devices. However, conclusions drawn for large devices cannot be directly applied to smaller devices because the operating mechanism depends on the size of the RRAMs [18]. 3.5 Speed A key FOM for a memory is the read/write time. For a phase change RAM (PCRAM), a phase change speed of 2.4 ns is reported [38]. For a spin transfer torque-RAM (STT-RAM), an operation speed < 10 ns can be attained [39]. These emerging technologies are faster than the 5 widely used NAND Flash which can exhibit write time of 100 µs [40]. Among RRAMs, a filamentary switching RRAM is reported to have switching speeds down to 300 ps [41]. A record switching speed of < 85 ps is reported for a nitride-based resistive switch [42]. This makes filamentary RRAMs one of the fastest memory devices. 3.6 Power Consumption Depending on the material and the switching mechanism, the power consumption in RRAMs can vary widely. In a filamentary RRAM, the CF is consistently built for the LRS and then ruptured for the HRS. This causes high power consumption. In contrast, a distributed RRAM does not completely build and rupture the CFs. Therefore, it has a lower power consumption [18]. RRAMs have been shown to have power consumption as low as 0.1 pj/bit in a TiN/Hf/HfOx /TiN structure [36]. In a different demonstration, using Al/Ti/Al2 O3 /sCNT structure, power consumption of 0.1–7 pj/bit has been reported [43]. 4. VARIABILITY In general, the variability in RRAMs depends on the materials used and their switching mechanisms. In this section, we describe the variability issues in CF-based RRAMs which are being intensely investigated. It has been noticed that, compared to the LRS, it is more difficult to characterize and map the variations in the HRS. The LRS is obtained by the formation of CF, and the resistance varies due to the variation in the thickness and the number of CFs. The characteristics of the LRS are typically ohmic, though in certain cases it can be dominated by tunnelling or non-ohmic behaviour [44]. The HRS is obtained when the CFs are ruptured. The mechanism of conduction in the HRS can be Poole-Frenkel emission, Schottky emission, space charge limited current characteristic, etc. [7]. Since it is difficult to predict the conduction paths and the conduction mechanism in the HRS, it becomes difficult to characterize the variability in the HRS [8]. Some of the factors that impact the conduction mechanism and the device variability in the HRS are dielectric properties of the oxide, fabrication process conditions, and interfacial properties of the oxide and the electrode [7]. It has been observed that for the first few cycles, a CF forms and breaks consistently. However, as the number of cycles increases, the behaviour of RRAMs becomes inconsistent and unpredictable. Though cycle-to-cycle Tight distribution of high resistive state TiOx with embedded platinum Chang et al. [48] Improving device uniformity Stable resistive switching and improved retention Reduces device-to-device variations TaN/Al2 O3 : RuNCs : Al2 O3 /Pt Chen et al. [47] Circuit-Level Improvements Liu et al. [51] Butcher et al. [50] Kalantarian et al. [49] Set a constant forming voltage for all devices Forming devices at high temperatures and low voltage bias Ramp the gate voltage, keep source and drain constant Low switching voltage, large ON/OFF ratio HfOx /TiOx Better filament formation than conventional HfO2 Improved set and reset voltage HfOx /AlOx multilayer Fang et al. [11] Author Some researchers have modified materials used in RRAMs by inserting implants or introducing doping in the device. In one of the modifications, a large resistance ratio was exhibited by embedding Ru nanocrystals in the TaN/Al2 O3 /Pt structure to create a TaN/Al2 O3 :RuNCs:Al2 O3 /Pt device [47]. This improvement in characteristics can be attributed to the ease in the formation and breaking of CFs due to an increased electric field near Ru nanocrystals [47]. Another work showed an improvement in device characteristics by embedding Pt nanocrystals in TiO2 thin-film RRAMs. These nanocrystals cause local enhancement of the electric field around them and thus improve the stability of resistive switching and retention properties [48]. Table 2: Techniques to address variability in RRAMs An HfOx /AlOx multilayer structure exhibits a better shape of filament when compared to the conventional HfO2 memory. Due to the addition of the AlOx layer, the overall shape of the filament becomes “funnel-shaped” instead of “hour-glass-shaped”. As a result, the CF formation becomes more deterministic and exhibits a lower spread in the OFF-state resistance [46]. Additionally, an HfOx /TiOx multilayer structure improves the uniformity of SET/RESET voltage distribution, along with obtaining a predictable LRS and HRS resistance distributions [11]. The different dielectric layers cause confinement of the CF. The authors have attributed this improvement in the uniformity to the titanium doping and the confinement effects [11]. Salient Features 4.1 Material-Level Improvements in Variability Raghavan et al. [46] Impact of the Technique Since tackling variability in RRAMs is critical for future applications, several techniques based on material engineering, programming methodology and fabrication process improvements have been proposed. Some of the important techniques that address variability issues in RRAMs are listed in Table 2. Material-Level Improvements Technique Used to Reduce Variability variation in RRAMs is a serious problem, in certain applications such as neuromorphic computation where only a few cycles are required for image recognition, this drawback may not inhibit their applications. In such applications, the speed and power advantages of RRAMs can be utilized despite high cycle-to-cycle variations. Nevertheless, there are certain applications such as long term storage, where the cycle-to-cycle variations of RRAMs can severely affect the functionality and must be controlled. However, reducing cycle-to-cycle variations would necessitate a deeper understanding of the variation mechanisms in RRAMs and a better device control [45]. Introducing the Aluminium layer streamlines the filament into a predictable pattern Different dielectric layers cause confinement of conductive filament Electric field near RuNCs high, causes easy formation and breaking of CF Concentrated electric field near platinum causes stable resistive switching behaviour Setting low constant forming voltage suppresses parasitic overshoot current causing controlled filament growth High temperature reduces forming time, low voltage bias improves uniformity Gate voltage ramped while keeping source–drain voltage constant V. GUPTA ET AL.: RESISTIVE RANDOM ACCESS MEMORY Category 6 V. GUPTA ET AL.: RESISTIVE RANDOM ACCESS MEMORY 7 Figure 5: Development of RRAM devices and materials in chronological order 4.2 Circuit-Level Improvements in Variability To tackle the variability issues, various techniques that set a constant forming voltage have been proposed [49,50]. By setting a constant forming voltage for all devices, the device-to-device variations are reduced. Additionally setting a low forming voltage can tackle variability issues by suppressing the parasitic overshoot current and leading to a controlled filament growth [49]. The forming voltage can be reduced by operating at elevated temperatures, thus reducing the variability in RRAMs [50]. Another technique to reduce the variability is to use gate voltage ramping (GVR) rather than source–drain voltage ramping in the SET/RESET operations [51]. The GVR scheme creates a positive feedback from Joule heating and results in a faster rupture of filaments and attains full RESET. As a result, the variability in the HRS reduces [51]. 5. MATERIALS USED IN REALIZING RRAMS The research on RRAM materials has been undertaken since the early 1960s. The progress in the development of the RRAM device is shown in Figure 5. The first demonstration of negative resistance was shown using thin oxide films such as SiO, Al2 O3 , Ta2 O5 , ZrO2 and TiO2 in a metal-insulator-metal structure by Hickmott in 1962 [52]. After Hickmott’s discovery, switching properties of materials such as thin NiO films were explored, and further investigations were carried out on the properties of Al2 O3 , Ta2 O5 and SiO [53,54]. Thereafter, in the 1990s, oxides such as perovskite oxides, Cr-doped SrTi(Zr)O3 , Pr0.7 Ca0.3 MnO3 (PCMO) and PbZr0.52 Ti0.48 were explored, though they were not stable enough to be used for memory applications [33]. In 2004, an OxRRAM based on a binary-transition metal oxide (TMO) was developed [33]. The OxRRAM was fully compatible with the CMOS technology and was integrated with the 0.18 µm CMOS technology. The OxRRAM was stable even up to 300◦ C and operated at voltage levels lower than 3 V [33]. This was groundbreaking work and motivated further research into RRAM materials and devices. Since 2004, several new materials have been explored, including binary metal oxides, ternary metal oxides, chalcogenides, nitrides, polymers and 2D layered materials [8,9]. Among metal oxides, binary metal oxides are found to be more compatible with the CMOS processes as compared to the non-binary metal oxides. Some of the important materials under these categories are listed in Table 3. However, it is worthy to point out that Table 3 is not an exhaustive list of materials, and novel materials such as La2 CuO4 , HoScOx , Ag2 S, poly(o-anthranilic acid) (PARA), poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS), etc. are also being investigated for RRAM applications [75–79]. Transition metal oxides have been thoroughly explored as the dielectric in the MIM stack. Moreover, 2D materials such as hexagonal boron nitride (h-BN), Graphene oxide (GO), MoS2 , etc. have several advantages over traditional TMO-based resistive switching devices, including flexibility, high thermal dissipation, chemical stability and transparency [72–74]. Hexagonal boron nitride (h-BN) is reported to have forming-free bipolar, threshold-type resistive switching with enhanced reliability, excellent thermal conductivity (600 W/mK), high chemical stability (> 1500◦ C), ability to handle high mechanical stress (500 N/m), low variability, high ON/OFF resistance ratio (up to 104 ), low operational voltages (down to 0.4 V) and long retention times (over 10 hours) [9,28]. Another major advantage of h-BN is the simple fabrication process. Chemical vapour deposition (CVD) is used to grow multilayer h-BN sheets which inherently contain some defects that become useful in resistive switching as they reduce the energy-tobreakdown, thus allowing the devices to be forming-free – 0.1 0.5 – 0.05 10 2 50 10 10 1 0.01 10 1 – 1 – 108 104 104 104 103 104 104 103 – 105 106 108 105 105 104 105 103 30 108 103 5 × 107 200 150 1012 75 100 – 50 107 109 130 100 350 – – 107 – 10 × 10 – 105 × 105 30 × 30 2 × 1011 – – 4.9 × 1010 20 100 × 100 2000 × 2000 104 × 104 – – −1.1 /1.7 0.25/−0.42 1/−1 0.5/0.5 −0.28 /−1.2 or 0.36/1.44 1.2/−0.4 to −1.5 −1 /2 0.65/−1.15 – 0.5/2.1–4.1 7/2 1.2/−1.25 2/−2 3/−0.6 0.7/−0.5 −0.47 to −1.04/1.91 to 3.93 2/−2 Polymers 2D Layered Materials Chalcogenides and Nitrides Ternary Metal Oxide GaIn/TiO2 -CuO/ITO ITO/WO3 /ITO SiO2 /ZrO2 /SiO2 TiN/Hf/HfOx /TiN TiN/TiOx Ny /TiO2−x /Pt Pt/Ta(2 nm)/NiO(50 nm)/Cu Pt/Ta2 O5−x /TaO2−x /Pt Ti/AlOx /Ti LaAlO3 /Nb-doped SrTiO3 Pt/TiO2 /SiO2 /Si/ La0.7 Sr0.3 MnO3 /BiFeO3 /Pt Al/V-doped SZO/LaNiO3 W/Si3 N4 /GeSx /Ag Si/SiO2 /Ti/Pt/SiN Pt/parylene-C/W Metal/h-BN/Metal Pt/rGOth/Pt rGO/MoS2 /ITO/SiO2 Binary Metal Oxide CuOx [55] WOx [56,57] ZrOx [58] HfO2 [36,59] TiOx [60] NiO[61,62] TaOx [32,63] AlOx [64] LaAlO3 [65,66] BiFeO3 [67] SrZrO3 [68] GeSx [69] SiN[70] Parylene-C[71] h-BN [9,72] GO[73] MoS2 [74] 3000 102 100 104 100 106 10 103 104 104 107 106 102 – 104 106 104 Cell size (nm2 ) Metal-insulator–metal materials Material Type of material Table 3: Table comparing some of the materials used in RRAM devices Resistance ON/OFF ratio Operating Voltage (V) (SET/RESET) Endurance (cycles) Compliance current (mA) V. GUPTA ET AL.: RESISTIVE RANDOM ACCESS MEMORY Retention (s) 8 Figure 6: Schematic representation of (a) 1T1R and (b) crosspoint structure of RRAM array [80] [9]. There is a significant amount of device-to-device variability due to the variable thickness of grain boundaries formed during CVD growth, however the cycle-tocycle variability is low [72]. While 2D materials appear promising, currently, TMO-based RRAMs have better performance [9]. 6. RRAM BASED CIRCUITS AND APPLICATIONS RRAM array can be implemented as a 1 selector–1 resistor (1S1R) structure. In a 1 transistor–1 resistor (1T1R) structure, as shown in Figure 6(a), the selector is a front-end-of-line (FEoL) device such as a CMOS transistor, a BJT or a gate-all-around transistor [81]. However, the selectors severely increase the bit cell area, the process cost and the complexity [81]. Therefore, structures utilizing back-end-of-line (BEoL) devices called cross-point arrays, shown in Figure 6(b), are considered. In cross-point arrays, RRAMs are placed at each intersection of the word-lines and the bit-lines. These structures integrate the BEoL selector in the RRAM stack, thus achieving a high bit cell density [81]. One such BEoL selector device is the field-assisted superlinear threshold (FAST) selector [82]. The FAST selector based device exhibits excellent performance, a small switching slope and a high current drivability. Several other devices including mixed-ionic-electronicconduction (MIEC) materials and varistor-type bidirectional switches have also been explored as BEoL selector devices [83,84]. Some circuit designs embedding RRAM with two transistors (2T1R) to overcome sneak current limitation have also been investigated [85,86]. Similar to SRAM cells, RRAM cells are accessed using the two transistors by enabling WL[0] and WL[1] lines. The BL[0] and BL[1] lines are used for the SET/RESET operations [85,86]. Some of the important limitations of a 2T1R structure are low current density, severe body effects, area inefficiency V. GUPTA ET AL.: RESISTIVE RANDOM ACCESS MEMORY and a need for large driving inverters [85,86]. To alleviate these limitations, 4T1R designs have also been investigated [85]. The 4T1R cell is embedded with two n-type and two p-type transistors and is programmed using the gate bias of these transistors. Compared to 2T1R structures, 4T1R structures exhibit higher current density and a better area efficiency [85]. It is well-known that Von Neumann architecture-based systems suffer from bandwidth constraints and related speed impact due to separate processing and memory units. In-memory computing alleviates these limitations by integrating the processing unit and the memory [87,88]. This makes neuromorphic computing using RRAMs promising due to the possibility of in-memory computation [89,90]. Some synaptic devices based on oxides such as Pr1−x Cax MnO3 (PCMO), HfOx , TaOx , TiOx , NiOx , AlOx , WOx , etc. have been explored in the literature [91]. Additionally, the need to realize highdensity neural networks have made RRAMs a potential candidate for these applications [92]. In recent times, hybrid combinations of transistors and RRAMs such as 1T1R, 2T1R, and 4T1R structures are gaining significant interest in these applications [89,93]. 7. CONCLUSION In this work, we have discussed the operating mechanism and the figures-of-merit for RRAMs. We have also reviewed the challenges of controlling variability by device design methods and also by exploring new materials and material combinations. RRAMs show promise to be used as Universal Memory. They are dense, nonvolatile, scalable and do not require very high voltages for their operation. Hence, RRAMs can replace Flash memories in many applications. The high density and speed of RRAMs also make them well-suited to replace on-chip DRAMs which are not scalable and also consume more power due to the refresh requirements. The low latency of RRAMs make them suitable to replace L2 and L3 SRAM caches in many applications. The high density and the low power consumption make RRAMs attractive for use in applications such as IoT, edge-computing, and neuromorphic computing. However, the biggest challenge to industrialize RRAMs lie in tackling the variability issues. While some applications such as neuromorphic computing and machine learning are error resilient and can adopt currently developed RRAMs, other applications such as automotive, smart industry etc. would use RRAMs only after variability control is demonstrated not only at the nominal operating conditions but also at high temperatures. 9 DISCLOSURE STATEMENT No potential conflict of interest was reported by the authors. REFERENCES 1. International Roadmap for Devices and Systems. “Beyond CMOS,” 2017. 2. A. Chen, “Emerging research device roadmap and perspectives,” in 2014 IEEE International Conference on IC Design Technology, Austin, TX, May 2014, pp. 1–4. DOI:10.1109/ICICDT.2014.6838616. 3. A. Chen, “A review of emerging non-volatile memory (NVM) technologies and applications,” Solid State Electron., Vol. 125, pp. 25–38, 2016. DOI:10.1016/j.sse.2016. 07.006. 4. M. Trentzsch et al., “A 28 nm HKMG super low power embedded NVM technology based on ferroelectric FETs,” in 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2016, pp. 11.5.1–4. DOI:10. 1109/IEDM.2016.7838397 5. D. Apalkov, B. Dieny, and J. M. Slaughter, “Magnetoresistive random access memory,” Proc. IEEE, Vol. 104, no. 10, pp. 1796–830, 2016. DOI:10.1109/JPROC.2016.2590142. 6. G. W. Burr et al., “Recent progress in phase-change memory technology,” IEEE J. Emerg. Sel. Top. Circ. Syst., Vol. 6, no. 2, pp. 146–62, 2016. DOI:10.1109/JETCAS.2016. 2547718. 7. H.-S. Philip Wong et al., “Metal oxide RRAM,” Proc. IEEE, Vol. 100, no. 6, pp. 1951–970, Jun. 2012. DOI:10.1109/ JPROC.2012.2190369. 8. M. A. Villena, J. B. Roldn, F. Jimnez-Molinos, E. Miranda, J. Su, and M. Lanza, “SIM2 RRAM: A physical model for RRAM devices simulation,” J. Comput. Electron., Vol. 16, no. 4, pp. 1095–120, 2017. DOI:10.1007/s10825-0171074-8. 9. C. Pan et al., “Coexistence of grain-boundaries-assisted bipolar and threshold resistive switching in multilayer hexagonal boron nitride,” Adv. Funct. Mater., Vol. 27, no. 10, p. 1604811, 2017. DOI:10.1002/adfm.v27.10. 10. T.-C. Chang, K.-C. Chang, T.-M. Tsai, T.-J. Chu, and S. M. Sze, “Resistance random access memory,” Mater. Today, Vol. 19, no. 5, pp. 254–64, Jun. 2016. DOI:10.1016/j.mattod. 2015.11.009. 11. Z. Fang, H. Y. Yu, X. Li, N. Singh, G. Q. Lo, and D. L. Kwong, “HfOx /TiOx /HfOx /TiOx Multilayer-based forming-free RRAM devices with excellent uniformity,” IEEE Electron Device Lett., Vol. 32, no. 4, pp. 566–68, 2011. DOI:10.1109/LED.2011.2109033. 10 V. GUPTA ET AL.: RESISTIVE RANDOM ACCESS MEMORY 12. F. Pan, C. Chen, Z.-S. Wang, Y.-C. Yang, J. Yang, and F. Zeng, “Nonvolatile resistive switching memoriescharacteristics, mechanisms and challenges,” Prog. Nat. Sci. Mater. Int., Vol. 20, pp. 1–15, 2010. DOI:10.1016/S10020071(12)60001-X. 13. L. F. Liu et al., “Multilevel set/reset switching characteristics in Al/CeOx /Pt RRAM devices,” in 2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC). Bangkok, Thailand: IEEE, 2012, pp. 1–3. 14. Z. Chen et al., “Ultrafast multilevel switching in Au/YIG/nSi RRAM,” Adv. Electron. Mater., Vol. 5, no. 2, p. 1800418, 2019. DOI:10.1002/aelm.v5.2. 15. S. Yu, Y. Wu, and H.-S. Philip Wong, “Investigating the switching dynamics and multilevel capability of bipolar metal oxide resistive switching memory,” Appl. Phys. Lett., Vol. 98, no. 10, p. 103514, Mar. 2011. DOI:10.1063/1.3564883. 16. M. Liu, Z. Abid, W. Wang, X. He, Q. Liu, and W. Guan, “Multilevel resistive switching with ionic and metallic filaments,” Appl. Phys. Lett., Vol. 94, no. 23, p. 233106, 2009. DOI:10.1063/1.3151822. 17. X. Ding, D. Zhu, Y. Feng, L. Cai, P. Huang, L. Liu, and J. Kang, “Low-power, multilevel and analog characteristics in the multi-layer-oxide based RRAM devices compatible with CMOS technology,” in 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). Qingdao: IEEE, 2018, pp. 1–3. 18. M. Lanza et al., “Recommended methods to study resistive switching devices,” Adv. Electron. Mater., Vol. 5, no. 1, p. 1800143, 2019. DOI:10.1002/aelm.v5.1. 19. D. C. Gilmer and G. Bersuker, Fundamentals of metaloxide resistive random access memory (RRAM),” in Semiconductor Nanotechnology: Advances in Information and Energy Processing and Storage. Cham: Springer International Publishing, 2018, pp. 71–92. 20. C. Ye et al., “Low-power bipolar resistive switching TiN/HfO2 /ITO memory with self-compliance current phenomenon,” Appl. Phys. Express, Vol. 7, no. 3, p. 034101, 2014. DOI:10.7567/APEX.7.034101. 21. Y. Li et al., “Conductance quantization in resistive random access memory,” Nanoscale Res. Lett., Vol. 10, no. 1, p. 420, 2015. DOI:10.1186/s11671-015-1118-6. 22. U. Russo, D. Ielmini, C. Cagli, and A. L. Lacaita, “Selfaccelerated thermal dissolution model for reset programming in unipolar resistive-switching memory (RRAM) devices,” IEEE Trans. Electron Devices, Vol. 56, no. 2, pp. 193–200, 2009. DOI:10.1109/TED.2008.2010584. 23. R. Waser and M. Aono, “Nanoionics-based resistive switching memories,” Nat. Mater., Vol. 6, no. 11, pp. 833–40, 2007. DOI:10.1038/nmat2023. 24. S. Yu, X. Guan, and H.-P. Wong, “On the stochastic nature of resistive switching in metal oxide RRAM: Physical modeling, Monte Carlo simulation, and experimental characterization,” in 2011 International Electron Devices Meeting, Washington, DC, Dec. 2011, pp. 17.3.1–4. DOI: 10.1109/IEDM.2011.6131572. 25. S. Gao et al., “Improving unipolar resistive switching uniformity with cone-shaped conducting filaments and its logic-in-memory application,” ACS. Appl. Mater. Interfaces, Vol. 10, no. 7, pp. 6453–62, 2018. DOI:10.1021/ acsami.7b19586. 26. Y. Li et al., “Bipolar one diode-one resistor integration for high-density resistive memory applications,” Nanoscale, Vol. 5, no. 11, p. 4785, 2013. DOI:10.1039/c3nr 33370a. 27. V. Jousseaume et al., “Comparative study of non-polar switching behaviors of NiO- and HfO2 -based oxide resistive-rams,” in 2010 IEEE International Memory Workshop, Seoul, 2010, pp. 1–4. DOI:10.1109/IMW.2010.548 8316. 28. Y. Shi et al., “Coexistence of volatile and non-volatile resistive switching in 2D h-BN based electronic synapses,” in 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 5.4.1–4. DOI:10.1109/IEDM. 2017.8268333. 29. Y. Shi et al., “Electronic synapses made of layered twodimensional materials,” Nat. Electron., Vol. 1, no. 8, pp. 458–65, 2018. DOI:10.1038/s41928-018-0118-9. 30. N. Xiao et al., “Resistive random access memory cells with a bilayer TiO2 /SiOx insulating stack for simultaneous filamentary and distributed resistive switching,” Adv. Funct. Mater., Vol. 27, no. 33, p. 1700384, 2017. DOI:10.1002/adfm.201700384. 31. F. Hui, E. Grustan-Gutierrez, S. Long, Q. Liu, A. K. Ott, A. C. Ferrari, and M. Lanza, “Graphene and related materials for resistive random access memories,” Adv. Electron. Mater., Vol. 3, no. 8, p. 1600195, 2017. DOI:10.1002/aelm.v3.8. 32. M.-J. Lee et al., “A fast, high-endurance and scalable nonvolatile memory device made from asymmetric Ta2 O5−x / TaO2−x bilayer structures,” Nat. Mater., Vol. 10, pp. 625–30, 2011. DOI:10.1038/nmat3070. 33. I. G. Baek et al., “Highly scalable non-volatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses,” in IEDM Technical Digest. IEEE International Electron Devices Meeting, San Francisco, CA, 2004, pp. 587–90. DOI:10.1109/IEDM.2004.1419228. 34. Z. Wei et al., “Highly reliable TaOx ReRAM and direct evidence of redox reaction mechanism,” in 2008 IEEE International Electron Devices Meeting, San Francisco, CA, 2008, pp. 1–4. DOI:10.1109/IEDM.2008.4796676. V. GUPTA ET AL.: RESISTIVE RANDOM ACCESS MEMORY 11 35. L.-G. Wang, X. Qian, Y.-Q. Cao, Z.-Y. Cao, G.-Y. Fang, A.-D. Li, and D. Wu, “Excellent resistive switching properties of atomic layer-deposited Al2 O3 /HfO2 /Al2 O3 trilayer structures for non-volatile memory applications,” Nanoscale Res. Lett., Vol. 10, no. 1, p. 135, 2015. DOI:10.1186/s11671-015-0846-y. 46. N. Raghavan, R. Degraeve, A. Fantini, L. Goux, D. J. Wouters, G. Groeseneken, and M. Jurczak, “Stochastic variability of vacancy filament configuration in ultra-thin dielectric RRAM and its impact on OFF-state reliability,” in 2013 IEEE International Electron Devices Meeting, Washington, DC, Dec. 2013, pp. 21.1.1–4. 36. B. Govoreanu et al., “10 × 10 nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and lowenergy operation,” in 2011 International Electron Devices Meeting, Dec. 2011, pp. 31.6.1–4. 47. L. Chen et al., “Enhancement of resistive switching characteristics in Al2 O3 -based RRAM with embedded ruthenium nanocrystals,” IEEE Electron Device Lett., Vol. 32, no. 6, pp. 794–6, Jun. 2011. DOI:10.1109/LED.2011.2125774. 37. R. Waser, R. Dittmann, G. Staikov, and K. Szot, “Redoxbased resistive switching memories – nanoionic mechanisms, prospects and challenges,” Adv. Mater., Vol. 21, no. 25-26, pp. 2632–63, 2009. DOI:10.1002/adma.20090 0375. 48. W.-Y. Chang, K.-J. Cheng, J.-M. Tsai, H.-J. Chen, F. Chen, M.-J. Tsai, and T.-B. Wu, “Improvement of resistive switching characteristics in TiO2 thin films with embedded Pt nanocrystals,” Appl. Phys. Lett., Vol. 95, no. 4, p. 042104, 2009. DOI:10.1063/1.3193656. 38. R. Zhang, Y. Hu, X. Zhu, Q. Chou, and T. Lai, “Simultaneously good stability and high speed based on oxygen-doped Zn15 Sb85 material,” ECS. J. Solid. State. Sci. Technol., Vol. 7, no. 9, pp. P452–5, 2018. DOI:10.1149/2.0071809jss. 49. A. Kalantarian et al., “Controlling uniformity of RRAM characteristics through the forming process,” in 2012 IEEE International Reliability Physics Symposium (IRPS), Anaheim, CA, Apr. 2012, pp. 6C.4.1–5. DOI:10.1109/IRPS. 2012.6241874. 39. Y. Huai et al., “High density 3D cross-point STT-MRAM,” in 2018 IEEE International Memory Workshop (IMW). Kyoto: IEEE, 2018, pp. 1–4. 40. W. Cheong et al., “A flash memory controller for 15 µs ultra-low-latency SSD using high-speed 3D NAND flash with 3 µs read time,” in 2018 IEEE International Solid – State Circuits Conference – (ISSCC), San Francisco, CA, 2018, pp. 338–40. DOI:10.1109/ISSCC.2018.8310322. 50. B. Butcher et al., “Hot forming to improve memory window and uniformity of low-power HfOx -based RRAMs,” in 2012 4th IEEE International Memory Workshop, Milan, May 2012, pp. 1–4. DOI:10.1109/IMW.2012.6213 647. 51. H. Liu et al., “Uniformity improvement in 1T1R RRAM with gate voltage ramp programming,” IEEE Electron Device Lett., Vol. 35, no. 12, pp. 1224–6, Dec. 2014. DOI:10.1109/LED.2014.2364171. 41. H. Y. Lee et al., “Evidence and solution of over-RESET problem for HfOx based resistive memory with sub-ns switching speed and high endurance,” in 2010 International Electron Devices Meeting, San Francisco, CA, 2010, pp. 19.7.1–4. DOI:10.1109/IEDM.2010.5703395. 52. T. W. Hickmott, “Low frequency negative resistance in thin anodic oxide films,” J. Appl. Phys., Vol. 33, no. 9, pp. 2669–82, Sept. 1962. DOI:10.1063/1.1702530. 42. S. Menzel, M. von Witzleben, V. Havel, and U. Böttger, “The ultimate switching speed limit of redox-based resistive switching devices,” Faraday Discuss., Vol. 213, pp. 197–213, 2019. DOI:10.1039/C8FD00117K. 53. J. F. Gibbons and W. E. Beadle, “Switching properties of thin NiO films,” Solid. State. Electron., Vol. 7, no. 11, pp. 785–90, Nov. 1964. DOI:10.1016/0038-1101(64)901 31-5. 43. C. Ahn, Z. Jiang, C. Lee, H. Chen, J. Liang, L. S. Liyanage, and H.-P. Wong, “1D selection device using carbon nanotube FETs for high-density cross-point memory arrays,” IEEE Trans. Electron Devices, Vol. 62, no. 7, pp. 2197–204, 2015. DOI:10.1109/TED.2015.2433956. 54. G. Dearnaley, A. M. Stoneham, and D. V. Morgan, “Electrical phenomena in amorphous oxide films,” Rep. Prog. Phys., Vol. 33, no. 3, pp. 1129–91, Sept. 1970. DOI:10.1088/0034-4885/33/3/306. 44. M. A. Villena, J. B. Roldán, M. B. González, P. GonzálezRodelas, F. Jiménez-Molinos, F. Campabadal, and D. Barrera, “A new parameter to characterize the charge transport regime in Ni/HfO2 /Si-n+ -based RRAMs,” Solid State Electron., Vol. 118, pp. 56–60, 2016. DOI:10.1016/j.sse. 2016.01.007. 45. C. Cagli et al., “About the intrinsic resistance variability in HfO2 -based RRAM devices,” in 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Athens, Apr. 2017, pp. 31–4. DOI:10.1109/ULIS.2017.7962593. 55. J.-C. Li, B. Chen, and Y. Qian, “Effect of fatigue fracture on the resistive switching of TiO2 -CuO film/ITO flexible memory device,” Curr. Appl. Phys., Vol. 18, no. 9, pp. 953–60, Sept. 2018. DOI:10.1016/j.cap.2018.05.009. 56. K. Qian, G. Cai, V. C. Nguyen, T. Chen, and P. S. Lee, “Direct observation of conducting filaments in tungsten oxide based transparent resistive switching memory,” ACS. Appl. Mater. Interfaces, Vol. 8, no. 41, pp. 27885–91, Oct. 2016. DOI:10.1021/acsami.6b08154. 57. T. Tsai, Y. Lin, and T. Tseng, “Resistive switching characteristics of WO3 /ZrO2 structure with forming-free, 12 V. GUPTA ET AL.: RESISTIVE RANDOM ACCESS MEMORY self-compliance, and submicroampere current operation,” IEEE Electron Device Lett., Vol. 36, no. 7, pp. 675–77, July 2015. DOI:10.1109/LED.2015.2428719. 58. D. Kumar, R. Aluguri, U. Chand, and T. Y. Tseng, “High performance bipolar resistive switching characteristics in SiO2 /ZrO2 /SiO2 tri-layer based CBRAM device,” in 2017 International Conference on Electron Devices and SolidState Circuits (EDSSC), Hsinchu, Oct. 2017, pp. 1–3. DOI: 10.1109/EDSSC.2017.8126482. 59. Y. Su et al., “A method to reduce forming voltage without degrading device performance in hafnium oxide-based 1t1r resistive random access memory,” IEEE J. Electron Devices Soc., Vol. 6, pp. 341–5, 2018. DOI:10.1109/JEDS. 2018.2805285. 60. D. Panda, F. M. Simanjuntak, and T.-Y. Tseng, “Temperature induced complementary switching in titanium oxide resistive random access memory,” AIP Adv., Vol. 6, no. 7, p. 075314, July 2016. DOI:10.1063/1.4959799. 61. G. Ma, X. Tang, H. Su, H. Zhang, J. Li, and Z. Zhong, “Effects of electrode materials on bipolar and unipolar switching in NiO resistive switching device,” Microelectron. Eng., Vol. 129, pp. 17–20, Nov. 2014. DOI:10.1016/j.mee. 2014.06.019. 62. G. Ma, X. Tang, H. Zhang, Z. Zhong, X. Li, J. Li, and H. Su, “Ultra-high ON/OFF ratio and multi-storage on NiO resistive switching device,” J. Mater. Sci., Vol. 52, no. 1, pp. 238–46, Jan. 2017. DOI:10.1007/s10853-0160326-5. 63. A. Zaffora, D.-Y. Cho, K.-S. Lee, F. Di Quarto, R. Waser, M. Santamaria, and I. Valov, “Electrochemical tantalum oxide for resistive switching memories,” Adv. Mater., Vol. 29, no. 43, p. 1703357, 2017. DOI:10.1002/adma.2017 03357. 64. I. Varun, D. Bharti, V. Raghuwanshi, and S. P. Tiwari, “Multi-temperature deposition scheme for improved resistive switching behavior of Ti/AlOx /Ti MIM structure,” Solid State Ionics, Vol. 309, pp. 86–91, Oct. 2017. DOI:10.1016/j.ssi.2017.07.013. 65. K.-C. Liu et al., “Investigation of the effect of different oxygen partial pressure to LaAlO3 thin film properties and resistive switching characteristics,” Thin Solid Films, Vol. 520, no. 4, pp. 1246–50, 2011. DOI:10.1016/j.tsf.2011. 04.205. 66. H. F. Tian, Y. G. Zhao, X. L. Jiang, J. P. Shi, H. J. Zhang, and J. R. Sun, “Resistance switching effect in LaAlO3 /Nb-doped SrTiO3 heterostructure,” Appl. Phys. A, Vol. 102, no. 4, pp. 939–42, 2011. DOI:10.1007/s00339-011-6276-5. 67. L. Liu, S. Zhang, Y. Luo, G. Yuan, J. Liu, J. Yin, and Z. Liu, “Coexistence of unipolar and bipolar resistive switching in BiFeO3 and Bi0.8 Ca0.2 FeO3 films,” J. Appl. Phys., Vol. 111, no. 10, p. 104103, 2012. DOI:10.1063/1.4716 867. 68. C.-C. Lin, C.-Y. Lin, M.-H. Lin, C.-H. Lin, and T.Y. Tseng, “Voltage-polarity-independent and high-speed resistive switching properties of V-doped SrZrO3 thin films,” IEEE Trans. Electron Devices, Vol. 54, pp. 3146–51, 2007. DOI:10.1109/TED.2007.908867. 69. R. Symanczyk et al., “Conductive bridging memory development from single cells to 2mbit memory arrays,” in 2007 Non-Volatile Memory Technology Symposium, Albuquerque, NM, 2007, pp. 71–75. DOI:10.1109/NVMT.2007. 4389950. 70. H.-D. Kim, H.-M. An, S. M. Hong, and T. G. Kim, “Forming-free SiN-based resistive switching memory prepared by RF sputtering,” Phys. Status Solidi (A), Vol. 210, no. 9, pp. 1822–7, 2013. 71. Y. Kuang, R. Huang, Y. Tang, W. Ding, L. Zhang, and Y. Wang, “Flexible single-component-polymer resistive memory for ultrafast and highly compatible nonvolatile memory applications,” IEEE Electron Device Lett., Vol. 31, no. 7, pp. 758–60, 2010. DOI:10.1109/LED.2010.2048297. 72. F. M. Puglisi, L. Larcher, C. Pan, N. Xiao, Y. Shi, F. Hui, and M. Lanza, “2D h-BN based RRAM devices,” in 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2016, pp. 34.8.1–4. DOI:10.1109/IEDM.2016. 7838544. 73. B. Hu, “Electrically controlled electron transfer and resistance switching in reduced graphene oxide noncovalently functionalized with thionine,” J. Mater. Chem., Vol. 22, no. 32, pp. 16422–30, 2012. DOI:10.1039/c2jm32121a. 74. X.-Y. Xu, Z.-Y. Yin, C.-X. Xu, J. Dai, and J.-G. Hu, “Resistive switching memories in MoS2 nanosphere assemblies,” Appl. Phys. Lett., Vol. 104, no. 3, p. 033504, 2014. DOI:10.1063/1.4862755. 75. A. Sawa, T. Fujii, M. Kawasaki, and Y. Tokura, “Colossal electro-resistance memory effect at metal/La2 CuO4 interfaces,” Jpn. J. Appl. Phys., Vol. 44, no. 9L, p. L1241, 2005. DOI:10.1143/JJAP.44.L1241. 76. W. Z. Chang, J. P. Chu, and S. F. Wang, “Resistive switching behavior of a thin amorphous rare-earth scandate: Effects of oxygen content,” Appl. Phys. Lett., Vol. 101, no. 1, p. 012102, 2012. DOI:10.1063/1.4732079. 77. M. Morales-Masis, S. J. van der Molen, W. T. Fu, M. B. Hesselberth, and J. M. van Ruitenbeek, “Conductance switching in Ag2 S devices fabricated by in situ sulfurization,” Nanotechnology, Vol. 20, no. 9, p. 095710, 2009. DOI:10.1088/0957-4484/20/9/095710. 78. S. Baek, D. Lee, J. Kim, S.-H. Hong, O. Kim, and M. Ree, “Novel digital nonvolatile memory devices based on semiconducting polymer thin films,” Adv. Funct. Mater., Vol. 17, no. 15, pp. 2637–44, 2007. DOI:10.1002/(ISSN)1616-3028. 79. H. Ha and O. Kim, “Bipolar switching characteristics of nonvolatile memory devices based on V. GUPTA ET AL.: RESISTIVE RANDOM ACCESS MEMORY 13 poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) thin film,” Appl. Phys. Lett., Vol. 93, no. 3, p. 033309, 2008. DOI:10.1063/1.2960998. based FPGA architectures,” IEEE Trans. Circ. Syst. I: Regul. Pap., Vol. 63, no. 4, pp. 503–16, Apr. 2016. DOI:10.1109/TCSI.2016.2528079. 80. L. Chen, J. Li, Y. Chen, Q. Deng, J. Shen, X. Liang, and L. Jiang, “Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar,” in Design, Automation Test in Europe Conference Exhibition (DATE), Lausanne, 2017, Mar. 2017, pp. 19–24. DOI:10.23919/DATE.2017.7926952. 87. R. Degraeve et al., “Opportunities and challenges of resistive RAM for neuromorphic applications,” in 2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, 2018, pp. 1–5. DOI:10.1109/IPFA.2018.8452548. 81. A. Levisse, P. Royer, B. Giraud, J. P. Noel, M. Moreau, and J. M. Portal, “Architecture, design and technology guidelines for crosspoint memories,” in 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Newport, RI, July 2017, pp. 55–60. DOI:10.1109/NANOARCH.2017.8053733. 82. P. Chen and S. Yu, “Compact modeling of RRAM devices and its applications in 1T1R and 1S1R array design,” IEEE Trans. Electron Devices, Vol. 62, no. 12, pp. 4022–8, Dec. 2015. DOI:10.1109/TED.2015.2492421. 83. K. Virwani et al., “Sub-30 nm scaling and high-speed operation of fully-confined access-devices for 3D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC) materials,” in 2012 International Electron Devices Meeting, San Francisco, CA, Dec. 2012, pp. 2.7.1–4. DOI:10.1109/IEDM.2012.6478967. 84. W. Lee et al., “Varistor-type bidirectional switch (JMAX > 107 A/cm2 , selectivity ∼ 104 ) for 3D bipolar resistive memory arrays,” in 2012 Symposium on VLSI Technology (VLSIT), Honolulu, HI, Jun. 2012, pp. 37–8. DOI:10.1109/VLSIT.2012.6242449. 85. X. Tang, “Circuit design, architecture and CAD for RRAMbased FPGAs,” Ph.D. thesis, IINFCOM, Lausanne, 2017, p. 240. 86. X. Tang, G. Kim, P. Gaillardon, and G. De Micheli, “A study on the programming structures for RRAM- 88. D. Ielmini and H.-S. P. Wong, “In-memory computing with resistive switching devices,” Nat. Electron., Vol. 1, no. 6, p. 333, 2018. DOI:10.1038/s41928-018-0092-2. 89. G. Pedretti et al., “Stochastic learning in neuromorphic hardware via spike timing dependent plasticity with RRAM synapses,” IEEE J. Emerg. Sel. Top. Circ. Syst., Vol. 8, no. 1, pp. 77–85, 2018. DOI:10.1109/JETCAS.550 3868. 90. Y. Li, Z. Wang, R. Midya, Q. Xia, and J. J. Yang, “Review of memristor devices in neuromorphic computing: Materials sciences and device challenges,” J. Phys. D: Appl. Phys., Vol. 51, no. 50, p. 503002, 2018. DOI:10.1088/1361-6463/aade3f. 91. X. L. Hong, D. J. J. Loy, P. A. Dananjaya, F. Tan, C. M. Ng, and W. S. Lew, “Oxide-based RRAM materials for neuromorphic computing,” J. Mater. Sci., Vol. 53, no. 12, pp. 8720–46, 2018. DOI:10.1007/s10853-018-2134-6. 92. C.-H. Kim et al., “Emerging memory technologies for neuromorphic computing,” Nanotechnology, Vol. 30, no. 3, p. 032001, 2018. DOI:10.1088/1361-6528/aae975. 93. V. Milo, G. Pedretti, R. Carboni, A. Calderoni, N. Ramaswamy, S. Ambrogio, and D. Ielmini, “A 4-transistors/ 1-resistor hybrid synapse based on resistive switching memory (RRAM) capable of spike-rate-dependent plasticity (SRDP),” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 26, no. 12, pp. 2806–15, 2018. DOI:10.1109/ TVLSI.92. 14 V. GUPTA ET AL.: RESISTIVE RANDOM ACCESS MEMORY Authors Varshita Gupta is pursuing B.Tech. in ECE from IIIT Delhi. Her research interests are in VLSI and Memory Design. Email: [email protected] Shagun Kapur is pursuing B.Tech. in ECE from IIIT Delhi. Her research interests are in Memory Design and Nanoelectronics. Email: [email protected] Sneh Saurabh is an Associate Professor at IIIT Delhi in the Department of Electronics and Communication Engineering. He obtained his Ph.D. from IIT Delhi in the year 2012 and B.Tech. (EE) from IIT Kharagpur in the year 2000. Before joining IIIT Delhi in June 2016, he has worked in the semiconductor industry for around sixteen years. His current research interests are in the areas of Nanoelectronics, Exploratory Electronic Devices, EnergyEfficient Systems and CAD for VLSI. Currently, he is Senior Member, IEEE and an Editor of IETE Technical Review. Corresponding author. Email: [email protected] Anuj Grover is an Assistant Professor in the Department of Electronics and Communication Engineering at IIIT Delhi. He obtained PhD from IIT Delhi (2015), MS (Electronic Circuits and Systems) from UCSD (2003), and B.Tech. (EE) from IIT Delhi (2000). Prior to joining IIIT Delhi, he worked for 19 years in the memory design team at STMicroelectronics. His current research interests include Ultra Low Power In-Memory Compute for edge computing and machine learning applications; safety and security in hardware; and error resilient energy efficient systems. Email: [email protected]