Experiments in Digital Electronics-V S Bist

Experiments in DIGITAL ELECTRONICS {For B.E./B.Tech. Degree/Diploma courses in Electrical/Electronics/computer related disciplines, and post graduate degree (M.Sc.) in Electronics/MCA} Dr. V. S. Bist Senior Technical Officer (Electronics) Department of Instrumentation Engineering-USIC School of Engineering & Technology H. N. B. Garhwal University (Central University), Srinagar (Garhwal), Uttarakhand Er. A. S. Bahuguna Assistant Professor Department of Electronics and Communication Engineering School of Engineering & Technology H. N. B. Garhwal University (Central University), Srinagar (Garhwal), Uttarakhand Dr. Sunil Semwal Associate Professor, Department of Electronics and Communication Engineering Model Institute of Engineering and Technology (Autonomous), Jammu, Jammu and Kashmir Neel Kamal Prakashan Shahdara, Delhi- 32 Published by : NEEL KAMAL PRAKASHAN 1/11052-A, Subash Park, Shahdara, Delhi-110032 email : [email protected] Mob: 9411006565 © The subject matter of this book or any part thereof may not be reproduced in any way without the written permission of the authors and publishers. ISBN : 978-81-952786-5-7 Price : Rs. 595.00 First Edition : 2021, Reprint in 2023-24 Printing at : NEEL KAMAL PRAKASHAN Experiments in Digital Electronics [iii] Preface Digital electronics circuits are the engines of cell phones, MPEG players, digital cameras, computers, data servers, personal digital devices, GPS displays, and many other consumer products that process and use information in a digital format. This experimental book elaborates on basic theories and experimental hands-on treatment of digital circuit design. This experimental book is suitable not only for basic theoretical concepts but also for laboratory work for B.E / B.Tech. Degree courses in Electrical / Electronics / Computer-related disciplines, Diploma courses in Electrical / Electronics / Computer-related disciplines, and postgraduate degree courses (M.Sc.) in Electronics and Master in Computer Application. This book covers most of the experiments in digital electronics. The digital circuits can be designed and constructed using standard digital integrated circuits (ICs) mounted on protoboards / breadboards easily assembled in the laboratory. In this book, a summary of the experiments is covered in nine sections. The brief theory given for each experiment is sufficient for students to understand an experiment and benefit from it. The lab experiments can be used in a stand-alone manner and can be accomplished by the traditional approach, with a protoboard / breadboard and TTL circuits. The operation of the integrated circuits used in the experiments is explained by referring to a diagram of similar components introduced in the experiments. Each experiment is presented informally, and the student is expected to produce a circuit diagram and formulate a procedure for verifying the operation of the circuits in the laboratory. Before going to the experimental work, this book provides the introductory part of the digital lab components, precautions for handling IC’s, testing, troubleshooting, safety measures used in the laboratory, etc. This book contains nine sections of the experiments. The first section deals with the experiments on Digital Logic Gates. This includes verifying the operation of basic gates, universal gates, exclusive-OR, and exclusive-NOR using ICs. The use of one input as a data control means enables/inhibits gates. The expanding gate input technique of the gate has lower input gate ICs. The second section deals with the experiments on the use of Universal Gates in digital logic circuits. Here we can verify the operation of all gates using universal gates. The third section is experiments based on the Simplification of Boolean Functions. Verify Boolean laws, De-Morgan’s and the duality theorems. Designing a circuit with universal gates that implement the given Boolean functions is also a part of this section. The fourth to sixth sections deal with Combinational Logic Circuits, consisting of the design of combinational circuits (adder/subtraction, code converters, IC Comparator, even/odd-parity bit, and data processing circuits). The seventh to ninth Experiments in Digital Electronics [iv] sections outline the formal procedure for the design of Sequential Circuits. Beginning with crossed NAND/NOR and progressing through gated, transparent data, masterslave, JK Flip-Flop and T flip-flop and their inter conversion between one flip-flop to another. Secondly, the applications of flip-flops are shift registers, universal shift register, ring counter, Johnson counter, serial adder, asynchronous binary counter, decade counter, and synchronous binary counter. Appendix-A contains the standard graphic symbol for logic functions recommended by an the ANSI/IEC standard. Appendix-B contains the circuits used in the digital laboratory. Appendix-C contains a brief description of the Digital ICs (TTL) used in the laboratory and Appendix-D contains the bibliography. We hope that this practical book provides a booster for students to enhance their practical knowledge and have a thorough understanding of the concepts, principles, and procedures involved in it. It will bring effective utilization of the time allocated to laboratory experiments. The authors will be delighted to receive comments and criticism on this experimental book so that its second edition can be brought out to the satisfaction of its users. Any constructive criticism will be highly appreciated and acknowledged. Writers [v] Experiments in Digital Electronics Dedicated to Late (Sri) Ram Singh Bist (Father) and Late (Sri) Harendra Singh Bist (Younger Brother). -Vijay Singh Bist Late (Sri ) Salik Ram Bahuguna (Dada Ji) and Late (Sri) Raghwanand Gairola (Nana Ji) -Arun Shekhar Bahuguna The Goddess “Holy Maa Ganga” and my sweet family. -Sunil Semwal Experiments in Digital Electronics [vi] Acknowledgements We are highly indebted to Prof. Annpurna Nautiyal, Vice-Chancellor, HNB Garhwal University, Srinagar (Garhwal) and Prof. N.S.Panwar, Head, Department of Instrumentation Engineering-USIC, for encouragement and providing all the necessary facilities. We wish to express our sincere thanks to Prof. B. S. Semwal, former Pro Vice-Chancellor, HNB Garhwal University, Srinagar (Garhwal), for their constant encouragement and moral support, without which it could not have been possible to complete this task. We are incredibly thankful to Prof. Y. P. Raiwani, Dean, School of Engineering & Technology, and Professor M.M.S.Rauthan, Prof. M.P.Thapliyal, Department of Computer Science and Engineering, Er B.S.Bhandari, Department of Instrumentation Engineering-USIC, all faculty and staff members of the School of Engineering and Technology, HNB Garhwal University, Srinagar Garhwal. We are also thankful to Prof. Ankur Gupta, Director MIET, Jammu, and Prof. (Dr.) Ashok Kumar, Head of the Department of Electronics and Communication Engineering, MIET, Jammu, for their encouragement and support. We wish to express our gratitude and thanks to all those who inspired us to write this book. Much needed moral support and encouragement are provided on numerous occasions by our whole family members. We wish to thank Dr. S.R.Sharma, Neel Kamal Prakashan, New Delhi, for publishing this book and endowing its with excellence. Finally, we wish to thank all those who helped us directly and indirectly for their support during the long process. Dr. V.S.Bist Er. A.S.Bahuguna Dr. Sunil Semwal Experiments in Digital Electronics [vii] Contents S.N. Chapter Name Page Number Preface iii - iv Dedicated to v Acknowledgements vi Digital Electronics Experiments -An Introduction 01 - 17 Experiments: 1 Digital Logic gates 1.1 1.2 1.3 1.4 2 3 4 18 - 39 To study and verify the truth tables of basic gates, and universal gate using ICs. 18 To study and verify the truth tables of EX-OR and EX-NOR gates using ICs. 26 To study and verify the use of data control to enable/ inhibit of gates. 29 To study and verify the expanding the inputs of gates. 34 Universal gates 40 - 48 2.1 To study and verify the use of the NAND gate as a Universal gate. 40 2.2 To study and verify the use of the NOR gate as a Universal gate. Simplification of Boolean functions 44 49 - 64 3.1 To study and verify De-Morgan’s and duality theorem. 49 3.2 To study and verify the Boolean laws. 51 3.3 Design and verify a circuit with universal gates that implements the given Boolean functions. 61 Combinational Logic Circuits-Arithmetic Circuits 4.1 Design and verify the operation of a half-adder circuit using a minimum numbers of gates. 65 - 93 65 [viii] Experiments in Digital Electronics 4.2 Design and verify the operation of a full-adder circuit using a minimum number of gates. 68 4.3 To study the 4-bit full adder IC7483 and verify its operation. 72 4.4 Design and verify the operation of BCD adder using IC 7483 and basic gates. 75 Design and verify the operation of half-subtraction circuits with a minimum number of gates. 78 Design, construct and verify full-subtraction circuits with a minimum number of gates. 81 Design, construct and verify the operation of 1’s complement adder/subtractor circuit. 85 Design, construct and verify the operation of 2’s complement adder/subtraction circuits. 89 4.5 4.6 4.7 4.8 5 Combinational Logic Circuits-Code Converters 5.1 5.2 6 94 - 115 To study and verify the Binary-to-BCD code converter circuit and vice versa. 94 To study and verify the Binary-to-Gray code converter and vice versa. 100 5.3 To study and verify the BCD-to-EX-3 code converter. 104 5.4 To study the use of comparator and verify its operation. 107 5.5 Design, construct, and test a circuit that generates and checks an even/odd- parity bit from message bits. Use XOR gates. 111 Combinational Logic Circuits-Data Processing Circuits 6.1 6.2 6.3 116 - 153 Design a combinational circuit with four inputs (A, B, C, and D) and an out put (Y). The output is to be equal to 1 when A=1 provided that B=0, or when B=1 provided that either C or D is also equal to 1. Otherwise, the output is to equal to zero. 116 To study and verify the workings of the multiplexer and its operation as a logic function generator. 119 To study and verify the operation of the demultiplexer as a logic function generator. 131 Experiments in Digital Electronics [ix] 6.4 To study and verify the operation of decoders-drivers. 138 6.5 To study and verify the operation of display devices and their decoders-drivers. 141 6.6 7 Sequential Circuits-Flip-Flops 7.1 8 154 - 177 To study and verify the operation of SR, D, JK, and T Flip-Flops using universal gate ICs. 154 7.2 To study and verify Flip-Flops using ICs. 163 7.3 To study and verify the conversion of Flip-Flops. 166 Sequential Circuits-Registers 8.1 8.2 8.3 8.4 8.5 8.6 9 To study encoder logic circuits and verifies their operations. 147 To study and verify the operation of the 4-bit shift right register using D-Flip-Flops. 178 To study and verify the operation of the 4-bit shift right register using registers ICs. 182 To study and verify the function table operation of the 4- bit shift right register using registers IC. 186 To study and verify the operation of universal shift register IC. 189 To study and verify the operation of 4- bit Ring counter and Johnson counter using IC-74195. 191 Design, construct and verify a 4-bit serial adder. 195 Sequential Circuits-Counters 9.1 9.2 9.3 9.4 178 - 197 198 - 214 To design and verify the operation of 4-bit asynchronous binary counter using IC 7473 (JK Flip-Flops). 198 To design and verify the operation of an asynchronous decade counter using IC 7473 (JK Flip-Flops). 201 To design and verify the operation of a 4-bit synchronous binary counter using JK Flip-Flops. 204 To study and verify the counters using ICs. 207 Experiments in Digital Electronics [x] Appendix-A: Standard Graphic Symbols 215 - 222 Appendix-B: Circuits used in digital laboratories 223 - 226 Appendix-C: Brief description of digital ICs 227 - 288 Appendix-D: Bibliography 289 - 290 [1] Digital Electronics Experiments - An Introduction 1. Introduction to Experiments This experimental book gives an idea and approach to laboratory experiments based on digital circuits and logic designs, and also provides a hands-on-experience for students. With the help of standard integrated circuits (ICs) mounted on breadboards, these digital circuits can be constructed. The following tools/components/devices are required for performing these experiments on the breadboard: 1. LED indicator lamps. 2. Switches (DPST toggle switch) to provide logic-0 and logic-1 signals. 3. Pulsers with push buttons. 4. A clock pulse generator with at least two frequencies: (a) low frequency (1 pulse/sec) to observe slow changes in signals. (b) A high frequency (1000 pulses/sec). 5. Multivoltage power supply. 6. Socket strips for mounting the ICs. 7. Solid hookup wire 8. A pair of wire strippers for cutting the wires. Laboratory experiments can also be performed on digital logic trainers that include the various required tools which are available from several manufacturers. A digital logic trainer contains power supplies, LED lamps, toggle switches, pulsar, a variable clock frequency generators, and IC socket strips. In some experiments, additional switches, lamps, or IC socket strips, extended breadboard with some solderless sockets and plug-in-switches may be required. The Standard Graphic Symbols for digital ICs are given in Appendix-A, the circuits used in the digital laboratory are given in Appendix-B, and the brief descriptions of digital ICs used in the labs are given in Appendix-C. In these experiments, the integrated circuits which are used can be classified on the basis of integration, such as SSI (small scale integration), MSI (medium scale integration). SSI contains the individual gates or flip-flops, whereas MSI performs the specific digital functions. For the experiments of two input OR, AND, NAND, NOR, XNOR gates, inverter and four input NAND gates, eight SSI gate ICs are needed. Experiments in Digital Electronics [2] 2. Use of Protoboard/Breadboard in digital circuits: A breadboard is used to build and test circuits quickly before finalizing the design of any circuit. Fig.1 shows the use of a protoboard/breadboard for designing digital circuits in a digital electronics laboratory. The protoboard has buses across the top that you can connect to logic-1 (in the case of TTL family-+5V dc) and logic-0 (ground). Each bus has two halves. You must install jumper wires (single core) across the hookup wire to have a continuous bus. ICs are plugged into the protoboard so that they span the gap. You then have access to each pin via vertical groups of five continuous connections. Short wires are connected to the power supply connection of each IC to be used. Switches can be used to supply logic-1 (+5V) and logic-0 (ground) to the inputs, or inputs can be wired directly to logic-1 and logic-0 with hook-up wire in the inputs of the gate. Outputs are connected to LEDs through current limiting resistors of approximately 330 �, 0.25 watt. Fig.1: Protoboard/Breadboard layout. 3. Use of display devices: 3.1. Light Emitting Diode (LED): When electrons fill a positive hole at the junction of PN material, the electrons lose some energy. This energy is given off as heat and light. All PN junctions do this, but the PN junction made of gallium emits a sufficient amount of light to be used as a visible light source. Depending on the type and amount of crystal doping, the light emitted can be red, green, or yellow. If the semiconductor material is gallium arsenide, the energy is released as infra-red radiation. By mixing other materials with the gallium, the visible light is observed. The diode must be forward biased and pass a few milliamps of current. The LED, like a PN junction, conducts current when forward biased and blocks the current when reverse biased. LEDs are not reverse-biased because, with more than a few volts of reverse bias, the LED is aged. The light output of the LED increases with increasing current until the junction gets too hot and burns out. A resistor is, therefore, invariably used in series with the LED to limit the current. Digital Lab Components - An Introduction [3] In a PN junction diode which is forward biased, the voltage drop is about 1.75 volts for a typical red LED. The forward-biased voltage is higher for yellow and green LEDs. To be easily seen, a typical LED needs between 5 mA and 20 mA. Table- 1: Typical LED data. S.No. 1. Material Gallium arsenide (GaAs) Gallium phosphide (GaP) Gallium indium phosphide (GalnP) 2. 3. Color Red V F (in volt) 2.0 at IF(in mA) 10 Green 2.2 10 Yellow 2.4 10 Because the diodes have a maximum current, unless this current is limited, the diode will be damaged. A series current limiting resistor is therefore needed. 3.1.1. Determining the value of the series resistor: A (GaP) LED is to be fed from a 5V supply and requires a current of 10 mA. The value of the current limiting resistor can be obtained by Ohm’s law as;Resistance value = voltage across the diode 5V � 2.2V � � 280� current in the resistor 10mA The nearest preferred value to this will be 270 ohm. A good bright glow is obtained with a currents of only 10 mA (power of 20mW). The LED is very efficient because electrical energy is converted directly into light. The LED requires approximately 12 mA current to burn brightly.TTL can handle more current in the ‘0’ mode than in the ‘1’ mode. This signal will be inverted to drive the LED in the active low mode. A red LED drops about 1.6V or 1.7V (when lit, LED voltage drops vary greatly with different colors). This leaves 5V - 1.7V = 3.3V to be dropped across the resistor. Ohm’s law dictates that the resistor should be about equal to 275� . Therefore, a 330 � resistor,, the nearest standard size, will be used to limit the current through the LED. 3.1.2. Identification of LED: Fig. 2 shows the LED identification. We can identify the LED by just seeing the anode lead from the cathode lead is listed as: (i) The cathode lead has a flat (thick portion). (ii) The anode lead is usually longer than the cathode lead. (iii) The flat edge of the package is on the cathode side of the LED. (iv) Connect the LED in a test circuit. If it does not light, turn the LED around. Experiments in Digital Electronics [4] When lit, the lead connected to ground is the cathode lead. Do not forget to connect current-limiting resistor with LED before making the connection otherwise it will damage. Fig.2: LED identification. 3.2. Seven-segment display: The seven-segment display is actually eight separate LEDs (seven segments and one decimal point). The seven-segment display format is used in other types of displays and can display any number from 0 to 9. Figure 3 shows the layout of the seven segment displays. The seven LEDs are labeled a through h. Fig.3: layout of seven segment display. By forward-biasing different LEDs, we can display the decimal numbers 0 to 9 plus a few letters of the alphabet. For instance, to display a 0; we need to light up segments a, b, c, d, e, and f. To light up a 5, we need segments a, c, d, f, and g. There are two types of seven-segment displays: common anode and common cathode. As can be seen in Fig.4, the common anode has all the anodes of the seven Digital Lab Components - An Introduction [5] segments connected together, and the common cathode is the same except that the cathode is all tied together. Also, notice the way the segments are labeled. With a common-anode type, you have to connect a current-limiting resistor between each LED and ground. The size of this resistor determines how many current flow through the LED. The typical LED current is between 1mA and 50 mA. (a) (b) Fig.4: Seven segment displays (a) Common cathode and (b) Common anode 4. Power Supply The power supply has a fixed +5V output for work in TTL or a variable supply for work in CMOS. Be sure that the supply is set to TTL. If your trainer or DC power supply does not have a fixed +5V output, connect the voltmeter across the output of a variable supply and adjust it to +5V. A higher supply voltage can destroy a TTL integrated circuit. Switch off supply voltages before inserting or removing integrated circuits (ICs). 5. Digital Integrated Circuits 5.1. Logic families: Digital logic integrated circuits may contain many transistors, diodes, and resistors, together with all the interconnections to form a complete circuit or logic function. The integrated circuit is formed on a substrate and the transistors may be formed using either bipolar devices (NPN or PNP transistors) or unipolar (Field Effect Transistor) and classified as: [6] Experiments in Digital Electronics Bipolar Families: Diode-Transistor Logic (DTL): this design, once popular, is now obsolete. Transistor-Transistor Togic (TTL): the most popular family of SSI and MSI chips. Emitter-Coupled Logic (ECL): the fastest logic family is used at high speed applications. MOS (Unipolar) Families: PMOS (p-channel MOSFETs): the oldest and slowest type, are becoming obsolete. NMOS (n-channel MOSFETs): dominates the LSI fields (µP and memories). CMOS (Complementary MOSFETs): push-pull arrangement of n- and p-channel MOSFETs, is extensively used where low power consumption is needed. This gives rise to two main logic families; Transistor-Transistor Logic (TTL) and Complementary Metal Oxide Semiconductors (CMOS). Both these logic families may be used in the following types of integrated circuits (I.C.); Small-Scale Integration (SSI) 1 to 10 gates Medium-Scale Integration (MSI) 10 to 100 gates Large-Scale Integration (LSI) 100 to 1000 gates Very-Large-Scale Iintegration (VLSI) 1000 to 10,000 gates Super-Large-Scale Integration (SLSI) 10,000 to 100,000 gates per I.C. 5.2. Logic IC series: Commonly used logic IC families are: 1. Standard TTL (type 74XX/54XX) 2. CMOS (type 4XXX) 3. Low power Schottky TTL (type 74LS/54LS) 4. Schottky TTL (type 74S/54S) 5. ECL (type 10,000) In 1964, Texas Instruments introduced transistor-transistor logic (TTL), a widely used family of digital devices. TTL is fast, inexpensive, and easy to use. The digital IC7404 is an example of a standard TTL. Over the years, subfamilies of TTL have been developed that have superior characteristics. The most popular range of commercial TTL devices is the 74 series, which will operate over the temperature range of 00 C to 700 C. The supply voltage required for these gates is: Digital Lab Components - An Introduction [7] Maximum: +5.25V Typical: +5.00V Minimum: +4.75V And the military applications devices are the 54 series, which will operate over the temperature range -550 C to 1250 C. The supply voltage required for these gates is: Maximum: +5.25V Typical: +5.00V Minimum: +4.75V A pair of digits is used to code the device and these distinguish the logic function of the chip. For example: 7400 is a standard quad 2-input NAND gate. There are many subfamilies of this group which are distinguished by infix letters in the device coding: e.g. 74LS00 device code-LS are the infix letters. The subfamilies are compared by their switching speed and power consumption as shown in the table below. Table 2: Sub-families of the 74 series of TTL gates Symbol Type of device Switching speed No infix letter L LS Standard gate Low power Low power Schottky series Advanced Schottky Advanced LS Schottky High Speed Schottky 10 ns 33 ns 10 ns Power consumption 10 mW 1 mW 2 mW 1.5 ns 22 mW 4 ns 1 mW 6 ns 3 ns 22 mW 20 mW AS ALS H S Letters following the 74 denote the subfamily as mentioned in the following: 74LS04 indicates a TTL hex inverter in Low-power Schottky technology. 74AL04indicates Advanced Low-power Schottky TTL technology. If the letters following 74 contain AC, then the IC is in the CMOS family. The CMOS family also contains subfamilies: 74AC04 indicates a hex inverter of Advanced CMOS technology. 74HC04 indicates a hex inverter of high speed CMOS technology. CMOS Devices: The original CMOS family was numbered 4XXX. The most popular range is the 4000 series, which will operate over the temperature range of -400C to +850C. For [8] Experiments in Digital Electronics example: 4011 is a quad 2 input NAND gate. The supply voltage required for these gates are from +3V to +15V. The digital IC4069 is an example of a CMOS hex- inverter. Most 4XXX ICs have a different pin out than their 74XX counterparts. The power pin on the 4XXX series is labeled VDD instead of VCC; and the ground pin is labeled VSS.VDD can range from +3 to +15V. CMOS Version of TTL: The main advantage of TTL devices is their speed, whereas the advantage of CMOS is its low-power consumption. There are currently high speed versions of CMOS devices have equivalent functions and pin outs to TTL devices. These CMOS ICs are therefore a direct replacement for TTL chips and have comparable speed with lower power consumption. These devices are also coded with infix letters; e.g. 74HCXX = high speed CMOS version of TTL with CMOS compatible inputs and 74HCTXX = high speed CMOS version of TTL with TTL compatible inputs. 5.3. Logic Levels: With TTL, logic-1 is represented by +5V and logic-0 by 0V. This, however, is the ideal and, in practice, there is a whole range of voltages that can represent logic-1 and logic-0. There is also a range of voltage that is indeterminate, neither logic-1 nor logic-0. Logic levels are simply the range of voltages used to represent logic-1 and logic-0.CMOS may be operated at a supply voltage of between +3V and +15V. Therefore, the logic levels with CMOS are very different from TTL. The logic levels with CMOS depend upon the supply voltage used, whereas with TTL they are firmly fixed. Table 3: Voltage levels for TTL and CMOS Logic state Logic-1 Logic-0 Indeterminate TTL 2V to 5V 0V to 0.8V 0.8V to 2V CMOS 2/3 of the supply voltage 1/3 of the supply or less 1/3 to 2/3 of the supply voltage Voltages present at the inputs and output of the gate must be maintained at the levels shown in table 3 and not be allowed to fall into the intermediate range; otherwise the gate will not give the correct logic function. 5.4. Packages: Digital ICs come in four major packaged forms. These forms are shown in Fig.5. Dual-In-line Package (DIP): Most TTL and MOS devices in SSI and MSI and VLSI are packaged in 14, 16, 24 or 40 pin DIPs. Mini Dual-In-line Package (Mini DIP): Mini DIPs are usually 8 pin packages. Digital Lab Components - An Introduction [9] Flat Pack: Flat packages are commonly used in applications where light weight is an essential requirement. Many military and space applications use flat packs. The number of pins on a flat pack varies from device to device. TO-5, TO-8 Metal can: The number of pins on a TO-5 or TO-8 can vary from 2 to 12. All the above styles of packaging have different systems of numbering pins. To find out about how the pins of a particular package are numbered, the manufacturer’s data sheet on package type and pin numbers must be consulted. Fig.5: Typical packaging systems in digital integrated circuits 5.5. Pin arrangements: The IC pins are arranged in a definite pattern. One end of the top of the IC has a notch or indentation. Starting from the notch, the pin is numbered counter-clockwise. The IC as shown in Fig. 6 is a 14-pin DIP (dual-in-line package). Fig.6: DIP arrangement (14-pin) [10] Experiments in Digital Electronics 5.6. Identification: ICs are identified by a number code stamped on the top. The prefix is manufacturer’s code. The next two numbers denote the family of ICs such as TTL or CMOS. If letters follow, they indicate the subfamily of the IC. The next numbers indicate the function of the IC, and the last letters indicate the package style. For example, a. 74/54 Series Numbering: DM74LS83N DM P refix/ Manufacture’s c ode DM=Digital Monolithic AM= Adva nced Micro Devices Blank=Fairchild H= Har ris P or C=Intel M M= monolithic Memories M C=M otorola DM=National N=Signetics SN=Te xas b. 74 LS Fami ly (TTL – Commercial74 Series) (Military use54) Temperature Range: 74series = 0 to o 70 C 54 series = -5 5 oC to 125oC series) 83 Subfamily (LS=Low power Schott ky) Circuit Type: No Code=Standard L=Low Power S=Schottky Clamp ed H=High Sp eed/Power Product AL=Ad vanced Low power schottky AC=Advanced CMOS HC= High speed CMOS N Function Code (83- 4 bit binary adder) Package N= Plastic DIL T= flat Pack W = Cerami c Flat Pack J = Ceramic DIL Subfamily Power Max. Freq. 2 mW Prop. delay 9.5 ns LS L 1mW 33 ns 3 MHz S 19 mW 3 ns 125 MHz No code H 10 mW 22 mW 10 ns 6ns 35 MHz 50 MHz 45 MHz Example of CMOS Series Numbering: RCA4008 AE RCA P refix/ Manufacture ’s c ode RCA = CD M EM= General Instrume nts M C1 = M otorola M M = Na tional CM = Solitron T P =Te xas Instrume nts HBF = SGS N = Signetics SCL= Solid State Scientific Sw = Ste wert warme r 40 Family (CMOS – Commerci al) 08 Function Code (08- 4 bit full adder wit h fast carry) A Series A=Standard B = High voltage E Package D = Cerami c DIL F= Ceramic Frit-seal DIL E = plasti c DIL K = Cerami c Flat pack An IC can be identified from the information given on the IC itself. The numbering system, though it has been standardized, has some variations from manufacturer’ to manufacturer. Usually, an IC has the above marking on its surface as shown in Fig. 7. Digital Lab Components - An Introduction [11] Fig.7: Identification marks on the digital ICs. Do not confuse the IC number with the data code that is also often stamped on the IC. The number 7436 indicates that the IC was manufactured in 1974 during the 36th week. 6. Resistors: Resistors are one of the more common passive devices which are capable of resisting the flow of electrons. Generally, it falls into two main categories: 1. Linear resistors. Those which obeys Ohm’s law. 2. Non-linear resistors. Consists of three types in common use: (a) Photo resistors - light sensitive. (b) Thermistors-heat sensitive. (c) Voltage-dependent resistors. Linear resistors: The circuit symbols for linear resistors are shown in Fig.8, and the units in which resistance is measured are ohms. Multipliers of 103 lead to the common usage of: Kilohms � k� � 1000’s Megohms � M� � 1000 000’s [12] Experiments in Digital Electronics In many circuit diagrams and manufacturer’s literature the decimal point is indicated by the position of the multiplier letter. For example: 6.8 � = 6R8 3300 � = 3.3k � = 3K3 3 300 000 � = 3.3 M � =3M3 In addition, a letter system is used to indicate the percentage tolerance: F = ±1%; G = ±2%; J = 5%; K = ±10%; M = ±20%; Fig.8: Circuit symbol for linear resistor. Wattage: The most important fact after the resistance is the power rating or wattage of the resistor. For a required resistance, the wattage may be calculated using: W = VI = I2R = V2/R. The types of resistors used in electronics are rated from 1/8 W upward. Colour coding: Many small resistors have their value indicated by a colour-coded band system, which may be identified as shown in Fig. 9. The colour code is as shown in Table 4. Table 4: Resistor colour code. Colour Significant Multiplier Figures Black 0 1 Brown 1 10 Red 2 100 Orange 3 1k Yellow 4 10k Green 5 100k Blue 6 1M Violet 7 10M Grey 8 White 9 Gold 0.1 Silver 0.01 None ppm /°C (parts per million per degree Centigrade) (1 ppm = 0.0001%) Tolerance (%) ±1 ±2 ±0.5 ±0.25 ±0.1 ±0.05 ±5 ±10 ±20 Temperature Coefficient 100ppm 50 ppm 15 ppm 25 ppm - [13] Digital Lab Components - An Introduction Fig. 9: Resistance colour coding system. 7. Precautions for handling CMOS-ICs Care must be taken in the handling of CMOS ICs since they can be destroyed by excessive static build-up between pins. The following guidelines should be followed: 1. Store CMOS ICs in antistatic tubes or in black conductive foam. Never push CMOS ICs into Styrofoam. They can be wrapped in aluminum foil. 2. In low humidity environments where static build-up is a problem, avoid touching the pins of a CMOS IC when they are removed from storage unless precautions have been taken to bleed off the static charge. conductive wrist straps connected through a resistor to ground is one method used. 3. Apply DC voltage to the CMOS circuit before signals are applied. 4. Remove signal sources before the DC supply is switched off. 5. Switch off supply voltage before inserting or removing CMOS devices from a circuit. Experiments in Digital Electronics [14] 8. Testing Logic Chips 8.1. Logic Probes: These are used to detect logic levels in a circuit under test. With most probes, there is an indication of the high state, the low state, a pulsating state and a voltage that is between the logic levels; i.e. a bad or indeterminate logic level. The probe will also have to distinguish between TTL and CMOS devices operating at different supply voltages. This is achieved because the probe supply comes from the circuit under test, and in the case of CMOS, if the supply voltage is known, the indeterminate logic levels can be computed by the probe. There are many manufacturers of logic probes and you must study the probe manual to determine its correct operation and use. 8.2. Logic Pulser: 1. The logic pulser is used to inject a pulse into a logic circuit. The injected pulse has sufficient current to override the existing output at a gate. For example, if the TTL gate output is logic-0 (ground), the pulser will force the output up to logic-1 (+5V) momentarily, changing the logic state. To avoid damage to the chip, the duration of the pulse is restricted to about 1.5 microseconds. 2. A commercial pulser must be capable of sinking or sourcing a current of at least 100 mA. 3. When the output of a gate is high and has to be forced low, then the pulser must sink (lose) current. When the output of the gate is low and must be forced high, then the pulser must source (provide) current. 4. The pulser is normally powered by the circuit (logic chip) under test. 5. In between pulses, the pulser has high resistance of around 300K ohms. This will allow all logic families to function normally even though the pulser probe tips are in contact with the circuit under test. 6. The operation of the pulser can be either a single shot, one pulse only, or a continuous mode, which provides a train of pulses. 7. The logic pulser may be used in conjunction with the logic probe. The pulser is used to produce a change in the logic state at the input of the gate, and the probe is used to detect the change at the output. 8. A logic pulser and probe are being used to check the gate. 9. Troubleshooting Tips: If your circuit does not work properly, consider these points: 1. Vcc and ground: Use a Digital Multimeter as a voltmeter to check for +5V on Vcc and 0 V on ground directly on the pins of the IC. If it measures otherwise, trace the wiring back to find the fault. Digital Lab Components - An Introduction [15] 2. Inputs: Use a Digital Multimeter to check the each input is at the level you expected. Check directly on the pins of the IC itself. Correct any discrepancies. Since these inputs are supplied directly from the switches or power supply buses, a 1 should be close to +5V and a 0 close to ground. 3. Outputs: Use a Digital Multimeter to check the outputs directly on the pins of the IC (2.4 V to 5 V for a logic-1, 0 V to 0.4 V for a logic-0). If steps 1 and 2 check and step 3 do not, then either the IC is bad or something connected to the output is loading it down. A common beginning mistake is to tie the outputs, especially 4. Pinouts: Are you using the right pinout for your IC? Consult your data book. 5. Think and act: You can not correct a circuit by starting at it. Use your Digital Multimeter. Get involved. Discuss it with your lab partner. 6. Hookup wires are sometimes shoved too far into the protoboards so that the insulation prevents electrical connections. You should be able to track down such a situation with your digital multimeter. 7. If you don’t understand after really trying, ask! 10. Laboratory Safety Rules: Here are some general rules to keep in mind that will make your lab sessions safe for you and those working near you. Your instructor may have some additional, more specific rules that apply to your laboratory. 1. Be aware of the fire extinguishers available in and near your lab. Know where the extinguishers are and how to use them. 2. Be aware of the main power disconnect switches that can be used to kill the electricity to the outlets in the lab. If someone is in trouble (electricity speaking), hit the “kill” switch and then try to help. 3. Handling ICs: ICs are delicate devices and can easily be damaged by rough and careless handling. The following precautions may be observed while working with ICs. a. Use the minimum amount of heat to solder or desolder connections. b. Note the orientation of the IC before removing it. This should be done by drawing a sketch of the IC with surrounding parts and noting the position of the notch on the IC. c. Always turn-off the equipment before removing or replacing any IC. Experiments in Digital Electronics d. 4. [16] Always use the proper IC insertion and remover tool. Most of the digital circuits are operate on logic-1 (+5 volts). We all get careless working with 5 volt circuits because of the low voltage level. Care should be taken as follows: a. Jewelry can be a good conductor of current. Severe burns can result if your jewelry becomes a part of the current path. b. If your signal generator and DC power supply are not isolated from ground, the oscilloscope ground will only be connected to their common ground, then the circuit will be modified and heavy currents can flow. c. If electrolytic capacitors are installed backwards (polarity reversed), they can become hot and explode. Concentrate on your work. 5. Wear safety glasses when soldering or unsoldering components. Eyes are often are very close to the work being soldered. A solder splash in the eye is not only extremely painful; it can also endanger your vision. 6. Solder in a well ventilated area to avoid breathing in flux fumes. 7. Protect your eyes and the eyes of those around you by holding onto the end of a lead to be cut with diagonal cutters. 8. Avoid the temptation to play around in the lab. Playing tricks on your colleagues has no place in the lab. A little common sense goes a long way. 11. Use of laboratory manual: Every lab manual consists of instructions prepared for performing different experiments. For each experiment, the objectives are written in specific terms. The list of equipment/apparatus and components required are given. The students are required to choose suitably the number of ICs and the proper power supply for the ICs used. After selecting the ICs, the students are required to note down the manufacturer’s name. By doing this, they will become familiar with the names of firms dealing with particular instruments and equipment. The logic circuit diagram for each experiment is given. It is possible that the equipment/apparatus indicated in the manual can not be used due to their non availability in the laboratory or for any other reason. In that case, an alternative arrangement may be required for which the teacher should be consulted. In such case, modifications to the logic circuit diagram should be made and checked by the teacherin-charge. [17] Digital Lab Components - An Introduction Observations should always be made in tabular form. The output must be compared with what was expected. 12. Guidelines for the Teacher: 1. A time-table for laboratory work should be prepared. The students should be informed in advance about the experiments they will be required to perform on a particular date that so they can come prepared. 2. Students should have this manual available to them with them before the laboratory session starts. 3. For laboratory work, students can be divided into small groups. 4. Students should go through the instruction sheet thoroughly before performing the experiment so that they acquire sufficient background knowledge to perform the experiment. 13. Hazards: Lab work requires patience and hard work. Be cool. Avoid the trap of rushing through a lab to get home early and missing the points. You should pay close attention to details, but don’t miss the overall concepts involved. [18] 1. Digital Logic Gates EXPERIMENT-1.1 Object: To study and verify truth tables of basic gates, and universal gate using ICs. Equipment/Components required: 1. Equipment: Power Project board, Multi-channel CRO, and Digital Multimeter. 2. Components: ICs: One 7408 (Quadruple 2-input AND gates), One 7432 (Quadruple 2-input OR gates), One 7404 (Hex inverter), One 7400 (Quadruple 2input NAND gates), One 7402 (Quadruple 2-input NOR gates). Diode: One LED (20mW) Miscellaneous: One Resistor ( 330 � ) 0.25 watt, Single core wire, and wire Cutter and stripper. Brief theory: Gates are circuits that are used to combine digital logic levels (ones and zeros) in specific ways. The basic gates are the inverter, OR, AND, and universal NAND, and NOR gate. Basic Gates 1. Inverters: The inverter is a single–input gate whose output is the complement of the input. It inverts the signal at the input. Fig.1.1.1 (a) shows symbols for the inverter and (b) summarizes the operation in a truth table by listing all possible inputs and the corresponding output. A 1 7404 a(i) 2 Y A A 3 7404 a(ii) 4 Y A Input A 0 1 Output 1 0 (b) Fig.1.1.1: Inverter (a) symbol- (i) active high input and active low output, (ii) active low input and active high output (b) truth table Digital Logic Gates [19] The small circle on the output of symbol a (i) is called a bubble, indicates an active low output and the absence of a bubble on the output indicates that the input is active high. This type of symbol is known as active high input and active low output. An alternative symbol a (ii) has a bubble on input but not on output, known as active low input and active high output. Inverters are available in a 14-pin DIP package in both TTL and CMOS. In the TTL family, the 7404 is a hex inverter. Hex signifies that six inverters are contained in the same IC. Each is independent from the others and each can be used in a different part of the circuit. The supply voltage, V cc is +5V and is applied to pin 14 with pin 7 connected to ground. The pinouts of all 74XXX04ICs, regardless of family or subfamily, are the same. See Fig. 1.1.2. Fig. 1.1.2: Pinout diagram of 74XXX04 Series The original CMOS family was numbered 4XXX. For example, the 4069 is a hex inverter. Most 4XXX ICs have a different pinout from their 74XXX counterparts. The pinout of the 4069 happens to be the same as the 7404. The power pin on the 4XXX series is labeled VDD instead of VCC; and the ground pin is labeled VSS. VDD can range from +3 volts to +15 volts. Some of the available inverter ICs are listed in Table 1.1.1 Table 1.1.1: Inverter gate ICs Number 7404 74LS04 74ALS04 Family TTL TTL TTL 74AC04 CMOS 74HC04 CMOS 74HCT04 CMOS 4069 CMOS Subfamily Standard Low-Power Schottky Advanced LowPower Schottky Advanced CMOS High-Speed CMOS High- Speed CMOS, TTL Compatible Standard Description Hex Inverter Hex Inverter Hex Inverter Hex Inverter Hex Inverter Hex Inverter Hex Inverter [20] Experiments in Digital Electronics 2. OR gates (Inclusive OR): The OR gate is a circuit that produces a high '1' on its output when any of its inputs are high '1'. Fig.1.1.3 (a) shows the symbols for the two-input OR gate with inputs A and B and output Y, and (b) summarizes the operation of the OR gate. All possible input combinations are listed by counting in binary from 00 to 11. A B 1 32 2 A Y=A+B 3 1 04 2 2 B (i) 3 04 Y � AB � A � B 1 08 3 5 04 6 4 (ii) (a) Input B A 0 0 0 1 1 0 1 1 Output Y=A+B 0 1 1 1 (b) Fig.1.1.3: OR gate (a) symbol- (i) active high input and active high output,(ii) active low input and active low output (b) truth table A variety of forms of OR gates are available in TTL and CMOS. In the TTL family, the 7432 is a quad (meaning four gates) two-input TTL OR gate IC. The four are independent. Each can be in a different part of the circuit without feedback. Power is supplied to the IC through a VCC (+5V) and ground connection. The 4072 is a dual (meaning two gates) four input CMOS OR gate IC. The pinout for 7432 and 4072 is shown in Fig. 1.1.4. 7432 4072 Fig. 1.1.4: Pinout diagram of (a) 7432 (b) 4072. Some of the available OR gate ICs are listed in Table 1.1.1 Digital Logic Gates [21] Table 1.1.2: OR gate ICs Number 7432 74LS32 74HC32 4071 4072 Family TTL TTL CMOS CMOS CMOS Subfamily Standard Low-Power Schottky High-Speed CMOS Standard Standard Description Quad 2-input OR Quad 2-input OR Quad 2-input OR Quad 2-input OR Dual 4-input OR 3. AND gates: The AND gate is a circuit that produces a high '1' on its output when all of its inputs are high '1'. A two-input AND gate, with inputs A and B and output Y, is shown in Fig.1.1.5 (a) conventional, IEC and the IEEE symbols. The truth table, Fig 1.1.5 (b), summarizes the operation of the AND gate. All possible input combinations are listed by counting in binary from 00 to 11. A B 1 08 2 Y=A.B 3 A 04 2 1 2 B (i) 1 3 04 32 5 3 Y � A � B � A.B 6 04 4 (ii) B 0 0 1 1 Input (a) A 0 1 0 1 Output Y=A.B 0 0 0 1 (b) Fig.1.1.5: AND gate (a) symbol- (i) active high input and active high output,(ii) active low input and active low output (b) truth table A variety of forms of AND gates are available in TTL and CMOS. The 7408 IC is a quad (meaning four gates) two-input TTL AND gate IC. There are four independent two-input gates. The 7411 is a triple (meaning three gates) three-input TTL AND gate IC, and the 4082 is a dual (meaning two gates) four input CMOS AND gate IC. The pinout for the 7408 is shown in Fig. 1.1.6 Fig. 1.1.6: Pinout diagram of 7408. [22] Experiments in Digital Electronics Some of the available AND gate ICs are listed in Table 1.1.3 Table 1.1.3: AND gate ICs Number Family 7408 TTL 74ACT08 CMOS 74HCT11 CMOS 4081 4082 CMOS CMOS Subfamily Description Standard Quad 2-input AND Advanced CMOS, TTL Quad 2-input AND Compatible High-Speed CMOS, TTL Triple 3-input AND Compatible Standard Quad 2-input AND Standard Dual 4-input AND Universal gates 4. NAND gates: The NAND gate is a circuit that produces a low '0' at its output when all of its inputs are high '1'. NAND is the contraction of the words “NOT” and “AND”. Its symbol with two inputs A and B an output Y, is shown in Fig.1.1.7 (a). The truth table for a NAND gate is shown in Fig 1.1.7 (b). Input Output 1 2 B A Y = 04 A 1 Y � A.B 1 A 0 0 1 Y � A � B � A.B 3 32 00 2 2 3 0 1 1 B 3 4 04 B 1 0 1 1 1 0 (i) (ii) (a) (b) Fig.1.1.7: NAND gate (a) symbol- (i) active high input and active low output,(ii) active low input and active high output (b) truth table The pinout for the 7400 is shown in Fig. 1.1.8 Fig. 1.1.8: Pinout diagram of 7400. The NAND gate Ics is available in many forms in TTL and CMOS, as shown in table 1.1.4. Digital Logic Gates [23] Table 1.1.4: NAND gate ICs Number 7400 7430 74LS20 74ALST10 Family TTL TTL TTL TTL Subfamily Standard Standard Low-Power Schottky Advanced Low-Power Schottky Advanced Low-Power Schottky High-Speed CMOS Standard Standard Standard 74ALST133 TTL 74HTC11 4011 4012 4023 CMOS CMOS CMOS CMOS Description Quad 2-input NAND 8-input NAND Dual 4-input NAND Triple 3-input NAND 13-input NAND Quad 2-input NAND Quad 2-input NAND Dual 4-input NAND Triple 3-input NAND 5. NOR gates: The NOR gate is a circuit that produces a low '0' at its output when one or more of its inputs are high '1'. NOR is the contraction of the words “NOT” and “OR”. Its symbol is the OR symbol with an inverted, with two inputs A and B and an output Y, is shown in Fig.1.1.9 (a). The truth table for a NOR gate is shown in Fig 1.1.4 A B 2 02 3 Y � A �B 1 A 04 2 1 2 B (i) 1 3 04 4 (ii) (a) 08 3 Y � A.B � A � B Input B 0 0 1 1 Output Y= 1 0 0 0 A 0 1 0 1 (b) Fig.1.1.9: NOR gate (a) symbol- (i) active high input and active low output,(ii) active low input and active high output (b) truth table The pinout for the 7402is shown in Fig. 1.1.10 Fig. 1.1.10: Pinout diagram of 7402. The NOR gate ICs is available in many forms in TTL and CMOS, as shown in Table 1.1.5 [24] Experiments in Digital Electronics Table 1.1.5: NOR gate ICs Number 7402 7425 74LVQ02 74ALS27 Family TTL TTL TTL TTL 4001 4002 4025 CMOS CMOS CMOS Subfamily Standard Standard Low-Voltage Quiet Advanced Low-Power Schottky Standard Standard Standard Description Quad 2-input NOR Dual 4-input NOR Quad 2-input NOR Triple 3-input NAND Quad 2-input NOR Dual 4-input NOR Triple 3-input NOR (i) Circuit diagram: Figure 1.1.11 (a) shows a TTL and (b) a CMOS circuit diagram for a twoinput NOR gate (a) (b) Figure 1.1.1 1: 2 - inputs NOR gate circuit (a) TTL and (b) CMOS (ii) Breadboard layout: Figure 1.1.12 shows an experimental breadboard setup for the 74HC00 that is used to test the single NAND gate. Figure 1.1.12: Breadboard layouts for the 74HC00. Digital Logic Gates [25] Procedure: (i) Truth Table: a. Connect the required power supply to the proper place on the breadboard. b. Connect the single core wire to the pin number - 14 (VCC) of the IC and pin number 7, to the ground. c. Verify each gate of the chip by putting in all possible combinations of inputs and observing the output with the help of LED's. (ii) Wave Form: Obtain the input-output waveform observed on the oscilloscope. (iii) Propagation delay: Connect all the inverters in cascade in the 7404IC. After that, a clock pulse is applied to the input of the first inverter. With the help of an oscilloscope calculate the delay from input to output of the six inverters. Apply the input clock pulse to one of channels and output to the sixth inverter on the channel. Finally, divide the total delay by six and obtain an average propagation delay per inverter. Observation: (i) Truth table for gates: Inputs Decimal 0 1 2 3 (ii) S.No. 1 2 3 4 5 A B 0 0 1 1 0 1 0 1 Outputs AN D OR NOT ‘A’ NOT ‘B’ NAND NO R Waveform for gates: Gate AND OR Inverter NAND NOR Waveform (inputs and output) [26] Experiments in Digital Electronics (iii) Propagation delay for gates: S .N o . G a te 1 A ND 2 OR 3 In v e rt er 4 N AN D 5 N OR P ro p a g a tio n d e l a y a fte r 8 g a tes 1 .--------2 .--------3 .--------1 .--------2 .--------3 .--------1 .--------2 .--------3 . --------1 .--------2 .--------3 .--------1 .--------2 .--------3 .--------- M ea n P r o pa g a ti o n d el a y o f a g a te ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- Result: Verified all the object using truth table, waveform and found propagation delay of the each gate. Precautions: 1. Check all connections thoroughly. 2. Check that logic 1 (high) is the +5V rail and logic 0 (low) is the 0V rail. 3. Do not leave an input floating. 4. Try to keep the wire as short as possible to avoid a bunch of wires. 5. Pay extra attention while performing the experiments. If IC's are getting hot, then there is a probable of short circuit. So, immediately turn-off the power supply. EXPERIMENT-1.2 Object: To study and verify the truth tables of EX-OR and EX-NOR gates using ICs. Equipment/Components required: 1. Equipment: Power Project board, Multi-channel CRO, and Digital Multimeter. 2. Components: ICs: One 7486 (Quadruple 2-input EX-OR gates), one 74HCT266 (Quad 2-input Ex-NOR). Diode: One LED Miscellaneous: One Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Digital Logic Gates [27] Brief theory: 1. Exclusive-OR gates: An exclusive-OR (Ex-OR) gate is not one of the basic gates, but is constructed from a combination of the basic gates. The Ex-OR is a two-input gate that produces a high '1' on its output when its inputs are different and a low '0' if they are the same. The symbol and truth table for an exclusive-OR are shown in Fig. 1.2.1. B 0 0 1 1 Input (a) Output Y � A� B 0 1 1 0 A 0 1 0 1 (b) Fig.1.2.1: Ex-OR gate (a) symbol (b) truth table Designing an Ex-OR gate, first we write a Boolean expression for the truth table in Fig.1.2.1. The output Y � AB � AB � A � B Table 1.2.1. Shows the some Ex-OR gate are available in many forms in TTL and CMOS. The pinouts for a 7486 quad two-input Ex-OR are shown in Fig.1.2.2 Fig.1.2.2: Ex-OR gate pin outputs Number Family Table 1.2.1: Ex-OR Gates ICs Subfamily 7486 74ACT86 TTL CMOS Standard Advanced CMOS, TTL compatible Quad 2-input Ex-OR Quad 2-input Ex-OR 74ALST86 TTL Advanced Low-Power Schottky Quad 2-input Ex-OR 4030 4070 CMOS CMOS Standard Standard Quad 2-input NAND Dual 4-input NAND Description [28] Experiments in Digital Electronics 2. Exclusive-NOR gates: An exclusive-NOR (EX-NOR), sometimes called non-exclusive-OR. Ex-NOR gate is not one of the basic gates, but is constructed from a combination of the basic gates. The Ex-NOR is a two-input gate that produces a 1 on its output when its inputs are the same and a 0 if they are different. The symbol and truth table for an exclusiveNOR are shown in Fig. 1.2.3. (a) Input B A 0 0 0 1 1 0 1 1 Output Y � A� B 1 0 0 1 (b) Fig.1.2.3: Ex-NOR gate (a) symbol (b) truth table To design an Ex-NOR, first write a Boolean expression for the truth table in fig.1.2.3. Y � AB � AB � A � B . The pinouts for a 74266 quad two-input Ex-NOR are shown in Fig.1.2.4. Fig.1.2.4: Ex-NOR gate pin outputs Table 1.2.2: Ex-OR Gates ICs Number 74HCT266 Family CMOS Subfamily Hi Speed CMOS Description Quad 2-input Ex-NOR Procedure: (i) Truth Table: Use one gate from the list of IC and obtains the truth table for the gate. By connecting the inputs of the gate to switches and the output to an indicator lamp, the truth table can be obtained. After that, verify the result. Digital Logic Gates [29] (ii) Wave Form: Obtain the input-output waveform relationship of the gate with the help of a given list of ICs and the waveforms may be observed on the oscilloscope. Low order outputs of the binary counter are used to provide inputs to the gate. Observation: (i) Truth table for Ex-OR and Ex-NOR gate: S.No. 0 1 2 3 A 0 0 1 1 Inputs B X-OR Outputs X-NOR 0 1 0 1 (ii) Waveform for Ex-OR and Ex-NOR gate: S.No. 1. 2. Gate EX-OR EX-NOR Waveform (inputs and output) Result: Verified all the objects using the truth table, waveform and finding the propagation delay of each gate. Precautions: 3. Check all connections thoroughly. 4. Check that logic 1 is the +5V rail and logic 0 is the 0V rail. 5. Do not leave an input floating. EXPERIMENT-1.3 Object: To study and verify the use of data control to enable/disable (inhibit) of gates. Equipment/Components required: 1. Equipment: Power Project board, Multi-channel CRO, and Digital Multimeter. 2. Components: ICs: One 7408 (Quadruple 2-input AND gates), One 7432 (Quadruple 2-input OR gates), One 7400 (Quadruple 2-input NAND gates), One 7402 (Quadruple 2-input NOR gates), One 7486 (Quadruple 2-input EXOR gates). Diode: One LED Miscellaneous: One Resistor 330 � / 0.25 watt, Single core wire, Cutter and stripper [30] Experiments in Digital Electronics Brief theory: One of the common uses of gates is to control or gate the flow of data from the input to the output. In that mode of operation, one input is used as the control and the other presents the data to be passed to the output. If the data is allowed to pass through, the gate is said to be enabled. If the data is not allowed to pass through, the gate is said to be inhibited. 1. AND gate Enable/disable (inhibit): Fig.1.3.1 shows the truth table for AND gate as an Enable/disable. Input Control Data Y Inhibit 0 0 0 0 1 0 Enable 1 0 0 1 1 1 Output Comments Output locked at 0 Data p asses throug h unaltered (a) ENABLE DISABLE (b) Fig.1.3.1: (a) truth table for AND gate as an Enable/Inhibit.(b) symbol and operation If the signal on the control input of an AND gate is low '0' (top two lines of the truth table in Fig. 1.3.1), the output of the gate is low '0' regardless of the data present on the data input. The data does not pass through the gate, and the gate is said to be inhibited. The output is “locked up” in the low '0' state. If the signal on the control input is high '1' (bottom top two lines of the truth table in Fig. 1.3.1), then whatever is present on the data input appears on the output and the gate is said to be enabled. The data “passes through” the gate. 2. NAND gate Enable/Inhibit: Fig.1.3.2 shows the truth table for NAND gate as an Enable/Inhibit. Input Control D ata Y Inhibi t 0 0 1 0 1 1 Ena ble 1 0 1 1 1 0 (a) Output Comme nts Outp ut loc ked at 1 Da ta passes thr ough inverte d Digital Logic Gates [31] (b) Fig.1.3.2: (a) truth table for NAND gate as an Enable/Inhibit (b). symbol and operation If the signal on the control input of a NAND gate is low '0' (top two lines of the truth table in Fig. 1.3.2), the signal on the data input is ignored and the output is “locked up” in the 1 state. The gate is said to be inhibited even though the output is 1. If the signal on the control input is high '1' (bottom top two lines of the truth table in Fig. 1.3.2), the signal on the data input is passed through the gate but is inverted in the process. The gate is said to be enabled. The inverted data “passes through” the gate. 3. OR gate Enable/Inhibit: Fig.1.3.3 shows the truth table for OR gate as an Enable/Inhibit. Input Control Data Y Enable 0 0 0 0 1 1 Inhibit 1 0 1 1 1 1 Output Comments Data passes through Output locked at 1 (a) Fig.1.3.3: (a) truth table for OR gate as an Enable/Inhibit (b) symbol and operations If the signal on the control input of an OR gate is 0 (top two lines of the truth table in Fig. 1.3.3), the signal on the data input passes through to the output and the gate is enabled. If the signal on the control input is 1 (bottom top two lines of the truth table in Fig. 1.3.3), the signal on the data input is ignored and the output is “locked up” in the 1 state. The gate is said to be inhibited. [32] Experiments in Digital Electronics 4. NOR gate as Enable/Inhibit: Fig.1.3.4 shows the truth table for NOR gate as an Enable/Inhibit. Input Control Data Y Enable 0 0 1 0 1 0 Inhibit 1 1 0 1 0 0 (a) Output Comments Data passes through inverted Outp ut locked at 0 (b) Fig.1.3.4: (a) truth table for NOR gate as an Enable/Inhibit (b). symbol and operations If the signal on the control input of a NOR gate is low '0' (top two lines of the truth table in Fig. 1.3.4), whatever is present on the data input appears on the output inverted. The gate is enabled. If the signal on the control input is 1 (bottom top two lines of the truth table in Fig. 1.3.4), the output of the gate is 0 regardless of the data present on the data input. The gate is said to be inhibited. 5. Ex-OR gate as Enable/Inhibit: Fig.1.3.5 shows the truth table for Ex-OR gate as an Enable/Inhibit. A logic '0' 1 2 86 Y=A 3 (a) A logic '1' Input Control Data Dat a passes 0 0 0 1 4 5 86 Y�A 6 Dat a passes inverted 1 1 0 1 Y 0 1 1 0 Output Comments Data passes through (buffer) Data passes through inverted (NOT gate) (b) Fig.1.3.5: (a) symbol and (b) truth table for Ex-OR gate as an Enable/Inhibit. If the signal on the control input of EX-OR gate is 0 (top two lines of the truth table in Fig. 1.3.5), whatever is present on the data input appears on the output inverted. The gate is enabled. Digital Logic Gates [33] If the signal on the control input is high '1' (bottom top two lines of the truth table in Fig. 1.3.5), the output of the gate is an inverted input. The gate is enabled. Procedure: To verify whether the gates are enabled or inhibited. (1) Insert the ICs into the power project board. (2) Connect the power supply to each IC. (3) Verify the output by giving the control and data inputs as shown in the above figures. (4) Connect the output to the LED monitor on the trainer or hookup it to a LED with the proper current limiting resistor. Observation: 1. Truth table for AND gate Enable/Inhibit: Inhibit Enable 2. Enable Y Output Comments Input Control 0 0 1 1 Data 0 1 0 1 Y Output Comments Truth table for OR gate Enable/Inhibit: Enable Inhibit 4. Data 0 1 0 1 Truth table for NAND gate Enable/Inhibit: Inhibit 3. Input Control 0 0 1 1 Input Control 0 0 1 1 Data 0 1 0 1 Y Output Comments Truth table for NOR gate Enable/Inhibit: Enable Inhibit Input Control 0 0 1 1 Data 0 1 0 1 Y Output Comments [34] Experiments in Digital Electronics 5. Truth table for Ex-OR gate Enable/Inhibit: Enable Inhibit Input Control 0 0 1 1 Data 0 1 0 1 Output Comments Y Result: Verified the enable/inhibit gates. Precautions: 1. Check all gates in the ICs before using them as enable/inhibit. 2. Check the power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-1.4 Object: To study and verify the expanding the inputs of gates. Equipment/Components required: 1. Equipment: Power Project board, Multi-channel CRO, and digital Multimeter. 2. Components: ICs: One 7408 (Quadruple 2-input AND gates), One 7432 (Quadruple 2-input OR gates), Two 7400 (Quadruple 2-input NAND gates), Two 7402 (Quadruple 2-input NOR gates). Diode: One LED Miscellaneous: One Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: 1. Expanding an AND gate: We can expand an AND gate with another AND gate. a. A three-input AND gate can be created from two, two-input AND gates as shown in Fig.1.4.1.The output is the same as if we had fed A, B, and C into three inputs AND, Y=(A.B).C.=A.(B.C) A B C 1 2 08 A.B 3 4 5 08 6 Y=A.B.C Fig. 1.4.1: Expanding a three- input AND gate using two-input AND. Digital Logic Gates [35] b. A four-input AND gate can be created from three two-input AND gates as shown in Fig.1.4.2. The output is the same as if we had fed A, B, C, and D into a fourinput AND, Y= (A.B). (C.D). Fig.1.4.2: Expanding a four- input AND gate using two-input AND. 2. Expanding a NAND gate: a. The output from a three-input NAND gate would be Y � A.B.C, can be created from three two-input NAND gates as shown in Fig.1.4.3. The output is the same as if we had fed A, B, and C into a three-input NAND as: Y � A.B.C � ( A.B).C � A.( B.C ) NAND � NAND Combination Fig.1.4.3: Expanding a three- input NAND gate using two-input NAND. b. A four-input NAND gate can be created from five two-input NAND gates as shown in Fig.1.4.4. The output is the same as if we had fed A, B, C, and D into a four-input NAND as: Y � A.B.C.D � ( A.B).(CD) NAND - NAND Combination Similarly, we can expand an NAND with another NAND. A B 1 2 4 00 3 5 00 6 12 13 C D 00 Y � ABCD 11 9 10 00 8 00 Fig.1.4.4: Expanding an four- input NAND gate using two-input NAND Experiments in Digital Electronics 3. [36] Expanding an OR gate: a. A three-input OR gate can be created from two two-input OR gates as shown in Fig.1.4.5. The output is the same as if we had fed A, B, and C into a three-input AND, Y= (A+B) + C = A + (B+C). Fig.1.4.5: Expanding a three- input OR gate using two-input OR. b. A four-input OR gate can be created from three two-input OR gates as shown in Fig.1.4.6. The output is the same as if we had fed A, B, C, and D into a fourinput OR, Y= (A.B). (C.D), similarly we can expand an OR with another OR. Fig.1.4.6: Expanding an four- input OR gate using two-input OR 4. Expanding an NOR gate: a. A three-input NOR gate can be created from three two-input NOR gates as shown in Fig.1.4.7. The output of three (A, B, and C) input NOR gate is: Y � A � B � C � ( A. �) � C � A � B � C ) NOR � NOR Combination Fig.1.4.7: Expanding a three- input NOR gate using two-input NOR. Digital Logic Gates [37] b. A four-input NOR gate can be created from five two-input NOR gates as shown in Fig.1.4.8. The output of four input (A, B, C, and D) NOR gate is Y � A � B � C � D � ( A � B) � (C � D) {NOR - NOR Combination} Similarly we can expand an NOR with another NOR. Fig.1.4.8: Expanding an four- input NOR gate using two-input NOR Procedure: 1. Insert the ICs in the proper place on the power project board. 2. Connect the power supply to the ICs. 3. Construct the above mentioned expanding gate logic circuits. 4. Connect the output to the LED monitor on the trainer or hookup it to a LED with the proper current limiting resistor. 5. Switch on the power project board. 6. Verify the output by giving the inputs in sequence. Observation: 1. Truth table for Expanding an AND gate: S.No. 0 1 2 3 4 5 6 7 8 14 15 D Inputs C B Output A 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 1 1 0 1 1 1 1 Output [38] Experiments in Digital Electronics 2. Truth table for Expanding a NAND gate: S.No. 0 1 2 3 4 5 6 7 8 14 15 3. D Inputs C B Output A Y � ( A.B).C or � A.( B.C ) 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 1 1 0 1 1 1 1 Output Y � A.B.C .D � ( A.B).(CD ) Truth table for Expanding an OR gate: S.No. 0 1 2 3 4 5 6 7 8 14 15 D 0 Inputs C 0 B 0 A Output 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 1 1 0 1 1 1 1 Output Y = (A+B) + (C+D) Digital Logic Gates [39] 4. Truth table for Expanding an NOR gate: S .N o. Inp uts D C B O ut pu t A Y � (A � B) � C � A. � B � C ) 0 1 2 3 4 5 6 7 8 14 15 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 1 1 0 1 1 1 1 O ut pu t or Y � A�B�C �D � ( A � B) � (C � D ) Result: Verified the expending gates using a truth table. Precautions: 4. Check all gates in the ICs before expanding. 5. Check the power supplies of the power project board. 6. Do not switch on the power supply when inserting the IC into breadboard. 7. Do not leave an input floating. [40] 2. Universal Gates EXPERIMENT-2.1 Object: To study and verify the use of the NAND gate as a Universal gate. Equipment/Components required: 1. Equipment: Power Project board, Multi-channel CRO, and Digital Multimeter. 2. Components: ICs: Two 7400 (Quadruple 2-input NAND gates). Diode: One LED Miscellaneous: One Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: The NAND gate is a combination of NOT and AND gate (i.e., AND gate followed by an inverter). Therefore, the output is NOT the AND of the inputs. Thus, it has two or more input signals but only one output signal. All input signals must be high to get a low output. The NAND gate is also called a universal gate because it can be used to implement any Boolean function. The logic operation of NOT (inverter/complement), AND, OR, Ex-OR, and Ex-NOR gates can be obtained with NAND gates only. The NAND gate is easier to realize and consumes less power than the other gates. 1. NAND as NOT ( Inverter/Complement) operation: The complement operation is obtained from a one input NAND gate that behaves exactly like an inverter. Fig.2.1.1 shows a two-input NAND gate as an Inverter. Suppose we apply the same signal to both inputs of a two-input NAND. The inputs to the NAND gate are tied together, so that the gate works as inverter (NOT) gate. Then either both inputs are low '0' or both inputs are high ‘1’. If the input is low '0' the output will be high ‘1’. If the input is high ‘1’ the output will be low '0'. The output is always the complement of the input. Universal Gates [41] Input 1 2 7400 3 Output Fig.2.1.1: NAND as an Inverter. 2. NAND as an AND operation: Two NAND gates are required for the operation of the AND gate. Firstly, perform the operation of the NAND gate and, after that, inverts the logical value of the signal. Fig.2.1.2 shows a two-input NAND gate used as a two-input AND gate. The output of the two-input AND gate is (Y � A.B � AB , NAND � NAND combinatio n} , the combination of two NAND gates gives AND operation. The two inputs of first NAND gate are A and B. Its output is (Y ) � A.B . The two inputs to the second NAND gate are tied together (NAND as NOT) and the output of first A.B is fed to this common terminal. The second NAND gate works as inverter and its output (Y � AB � AB ), thus giving two-input AND operation. Fig.2.1.2: NAND as an AND. 3. NAND as an OR operation: With the help of a NAND gate with additional inverters on each input, the OR operation can be achieved. Fig.2.1.3 shows a two-input NAND gate used as a two-input OR gate operation. The output of two-input OR gate is ( Y � A � B � A � B � A . B ). It indicates that, the combination of three NAND gates gives two-input OR gate. When two input NAND gate are tied together, the NAND gates work as inverters, giving outputs A and B. The output of third NAND gate is A . B. As per De-Morgan’s theorem, this is equal to A � B thus giving a two-input OR function. [42] Experiments in Digital Electronics 1 00 3 5 00 6 2 4 00 Fig.2.1.3: NAND as an OR. 4. NAND as a NOR operation: Fig.2.1.4 shows a two-input NAND gate as a two-input NOR gate. The output of the two-input NOR gate is ( Y � A � B � A . B ). It indicates that the combination of four two-input NAND gates gives a two-input NOR gate operation. In Fig.2.1.4, the two inputs of each of the first two NAND gates are tied together and fed by A and B. The outputs are A and B. They are fed to as inputs to third NAND gate. The output is A+B, fed to as an input to fourth NAND gate. The final output is A � B thus giving NOR operation. Fig.2.1.4: Shows a two-input NAND gates as a two-input NOR gate 5. NAND as an EX-OR operation: The output of the EX-OR gate is ( Y � AB � A B ). There are two ways, from which we can implement the EX-OR gate. Fig.2.1.5 shows a logic diagram of an EXOR gate using two-input NAND gates. Table 2.1.1 shows the comparison between two logic diagrams. One way {Logic diagram (a)}:Y � AB � A B Y � AB � A B Y � AB. A B Second way {Logic diagram (b)}:� . 𝐴 + 𝐴𝐴̅ + 𝐵𝐵 � 𝑌 = 𝐴̅. 𝐵 + 𝐵 � ) + 𝐵(𝐴̅ + 𝐵 �) 𝑌 = 𝐴(𝐴̅ + 𝐵 ����������������������� ����� ����� 𝑌 = 𝐴(𝐴. 𝐵 ) + 𝐵(𝐴. 𝐵) �������������������� �������� �������� 𝑌 = ���������� 𝐴(𝐴. 𝐵). ���������� 𝐵(𝐴. 𝐵) Universal Gates [43] VCC=+5V 14 A 12 13 00 9 11 10 5 Y 1 2 2 00 A B 3 1 2 00 3 00 5 6 00 12 3 13 10 B IC 7400 (a) 6 00 00 Y A 11 B 9 4 1 B 4 A 8 00 8 00 7 GND (b) Fig.2.1.5: Ex-OR gate (a) first logic diagram and (b) second logic diagram using two-input NAND gates. Table 2.1.1 Comparison between two logic diagrams. Descriptions;(2-input NAND gate) Total numbers of gate used Total Numbers of inputs Total Number of IC(s) used Logic diagram (a) 5 8 2 Logic diagram (b) 4 5 1 After comparing the above two logic diagrams, logic diagram (b) requires minimum hardware to implement the EX-OR gate. 1. NAND as an EX-NOR operation: The output of the EX-NOR gate is ( Y � AB � A B � AB � A B ). It is the invert of the EX-OR gate. We can implement the EX-NOR gate using minimum number of NAND gates as shown in Fig.2.1.7. 1 2 00 3 4 5 00 9 10 00 6 12 8 13 00 11 1 2 00 3 Y Fig.2.1.6: Ex-NOR gate using minimum number of NAND gate. Procedure: (1) Insert the IC 7400 on the IC base of the logic trainer board/breadboard. Connect +5V supply to pin 14 and ground pin 7. (2) Construct the different logic gate operations as shown above. (3) Connect the inputs of the gate to the switches provided on the trainer or hook up them to the +5V supply (logic 1) or ground (logic 0) as required. [44] Experiments in Digital Electronics (4) Connect the output to the LED monitor on the trainer or hookup them to a LED with proper current limiting resistor. (5) Switch on the trainer/power project board and observe LED output for various combinations of A and B inputs. Observations: Truth table for gates using NAND-NAND combinations: S .No. 1 2 3 4 A 0 0 1 1 Inp uts B AND OR Output NOT A NOR X-OR X -NOR 0 1 0 1 Result: Verified the outputs of the above mentioned gates using NAND gates only. Precautions: 1. Check all gates in the NAND gates ICs, LED, power supplies in the power project board/trainer, and hook up single core wire before using it. 2. Do not leave an input floating. EXPERIMENT-2.2 Object: To study and verify the use of the NOR gate as a Universal gate. Equipment/Components required: 1. Equipment: Power Project board, Multi-channel CRO, and Digital Multimeter. 2. Components: ICs: Two 7402 (Quadruple 2-input NOR gates). Diode: One LED Miscellaneous: One Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: The NOR gate is obtained by the combination of NOT and OR gates. The operation of NOR is the dual of the NAND operation. Therefore, the output is NOT the OR of the inputs. Thus, it has two or more input signals but only one output signal. All input signals must be low to get a high output. The NOR gate is also called the universal gate because it can be used to implement any Boolean function. We can implement NOT (complement), AND, OR, NAND, EX-OR, and EX-NOR gates with NOR gates only. The NOR gate is easier to realize and consumes less power than the other gates. Universal Gates [45] 1. NOR as an Inverter operation: A single input NOR gate behaves like an inverter and it shows a complement operation. If we apply the same signals to a two-input NOR gate, then either both inputs are‘0’ or both inputs are ‘1’. In either case, the output is always the complement of the input. Fig.2.2.1 shows a two-input NOR gate as an Inverter. Input 2 3 1 02 Output Fig.2.2.1: NOR as an Inverter. 2. NOR as an OR operation: An OR operation requires two NOR gate. Fig.2.2.2 shows a two-input NOR gate as a two-input OR operation. The output of the two-input OR gate is ( Y � A � B � A � B ). Therefore, the combination of two two-inputs NOR gates gives OR operation. The two inputs of the first NOR gate are A and B. Its output is (Y ) � A � B . The two inputs to the second NOR gates are tied together and the output of the first A � B is fed to this common terminal. The second NOR gate works as an inverter and its output is A+B, thus giving two-input OR operation. 2 3 02 1 5 6 02 4 Y Fig.2.2.2: NOR as an OR. 3. NOR as an AND operation: The AND operation is achieved through a NOR gate with additional inverters on each input.Fig.2.2.3 shows a two-input NOR gates as a two-input AND operation. The output of the two-input AND gate is ( Y � AB � AB � A . � B ). It implies that, the combination of three NOR gates gives AND operation. In Fig.2.2.3, the two-inputs of each of the first two two-input NOR gates are tied together and fed by A and B as shown. The outputs are A and B. They are fed as inputs to the third two-input NOR gate. The final output is AB thus giving two-input AND operation. Experiments in Digital Electronics [46] Fig.2.2.3: NOR as an AND. 4. NOR as a NAND operation: Fig.2.2.4 shows a two-input NOR gate as a two-input NAND operation. The output of two-input NAND gate is ( Y � AB � A � B ). It implies that the combination of four NOR gates NAND operation. Fig.2.2.4 shows a NOR gate as a NAND. In Fig.2.2.4, the two-inputs of each of the first two NOR gates are tied together and fed by A and B. The outputs are A and B . They are fed as inputs to the third NOR gate. The output is AB, fed as an input to fourth NOR gate. The final output is AB , thus giving NAND operation. Fig. 2.2.4: NOR as an NAND 5. NOR as an EX-OR operation: Fig.2.2.5 shows a two-input NOR gate as EX-OR operation. The output of EX-OR gate is Y � AB � A B . We can implement the EX-OR gate with minimum of two input NOR gate as shown in fig. 2.2.5. Y � A � ( A � B) � B � ( A � B) Universal Gates [47] 2 3 02 1 5 6 02 9 8 02 4 10 11 12 13 02 2 3 1 Y 02 Fig.2.2.5: Ex-OR gate using minimum numbers of NOR gates. 6. NOR as an EX-NOR operation: Fig.2.2.6 shows a two-input NOR gate as EX-NOR operation. The output of EX-NOR gate is Y � AB � AB � AB � AB . It is the invert of the EX-OR gate. We can implement the Ex-NOR gate using minimum number of NOR gates as: Y � A � ( A � B ) � B � ( A � B) � A � ( A � B ) � B � ( A � B ) 5 2 3 02 1 6 8 9 02 02 4 10 11 12 02 13 Y Fig.2.2.6: Ex-NOR gate using minimum number of NOR gate. Procedure: (1) Insert the IC 7402 into the IC base of the logic trainer board/breadboard. Connect +5V supply to pin 14 and ground pin 7. (2) Construct the different logic gates operation as shown above. (3) Connect the inputs of the gate to the switches provided on the trainer or hook them up to the +5V supply (logic 1) or ground (logic 0) as required. (4) Connect the output to the LED monitor on the trainer or hookup it to a LED with the proper current limiting resistor. [48] Experiments in Digital Electronics (5) Switch on the trainer/power project board and observe LED output for various combinations of A and B inputs. Observations: Truth table for gates using NOR-NOR combinations: S.No. 1 2 3 4 A 0 0 1 1 Inputs B AND OR Output NOT A NAND X-OR X-NOR 0 1 0 1 Result: Verified the output of the above mentioned gates using NOR gates only. Precautions: 1. Check all gates in the NOR gates ICs, LED, power supplies in the power project board/trainer, and hook up single core wire before making use of it. 2. Do not leave an input floating. [49] 3. Simplification of Boolean Functions EXPERIMENT-3.1 Object: To study and verify De-Morgan’s and duality theorem. Equipment/Components required: 1. Equipment: Power Project board, Multi-channel CRO, and Digital Multimeter. 2. Components: ICs: One 7402 (Quadruple 2-input NOR gates), One 7432 (Quadruple 2-input OR gates), One 7404 (Hex inverter). Diode: One LED. Miscellaneous: One Resistor (330 Ω) 0.25watt, Single core wire, Cutter and stripper. Brief theory: De-Morgan’s theorem is one of the most important theorems in Boolean algebra. Since it formulates the relationship between NOT (AND) and NOT (OR) functions that allows one type of function to be implemented using a different type of gate. This is also known as the ‘Law of dualisation’. 1. De-Morgan’s first theorem: It states that compliment of a sum of variables is equal to the product of their individual compliment of variable. Boolean expression for the above is B � A � B. A . This equation means that a NOR function can be implemented by inverting the two inputs to an AND function. Fig. 3.1.1 shows the logic diagram and truth table for two-input De-Morgan’s first theorem. This theorem supports the fact that a NOR gate is the same as inverting the inputs into an AND gate (bubbled AND). A B 2 02 3 Y � A�B 1 A 04 2 1 2 B (i) 1 3 04 4 (ii) (a) 08 3 Y � A.B � A � B B 0 0 1 1 A 0 1 0 1 B.A 0 0 0 1 1 1 1 0 (b) Fig.3.1.1: (a) Logic diagram (b) truth table 1 1 0 0 1 0 1 0 1 1 1 0 [50] Experiments in Digital Electronics 2. De-Morgan’s second theorem: It states that the complement of a product of variables is equal to the the sum of their individual variable complements. The Boolean expression for the above is BA � B � A . This equation means that a NAND function can be implemented by inverting the two inputs into an OR function. Fig. 3.1.2 shows the logic diagram and truth table for two-input De-Morgan’s second theorem. A B A 1 1 04 2 1 Y � A.B 00 2 2 3 B 3 04 (i) Y � A � B � A.B 32 3 4 (ii) (a) B 0 0 1 1 A 0 1 0 1 B.A 0 0 0 1 1 1 1 0 (b) 1 1 0 0 1 0 1 0 + 1 1 1 0 Fig.3.1.2: (a) Logic diagram (b) truth table 1. Duality theorem: It states that if you have a true Boolean equation or expression then the dual of this equation or expression is true. The dual of a Boolean expression can be replaced by symbols with their counterparts. This means that 1 is replaced by 0 and 0 is replaced by 1. With the help of the duality theorem, SOP (sum of product) is converted to POS (product of sum) and vice-versa. For example, A+1 = 1, by duality A.0 = 0 Procedure: (1) Insert the ICs into the breadboard. Connect the power supply to the ICs on the proper pin. (2) Construct the abovementioned circuits. (3) Connect the inputs of the gate to the switches provided on the trainer or hook them up to the +5V supply (logic 1) or ground (logic 0) to give the proper sequence of binary or you may use 2-bit binary counter with a debouncing switch as a clock. (4) Connect the output to the LED monitor on the trainer or hookup it to a LED with proper current limiting resistor. (5) Turn on the trainer/power project board. (6) Check the output of each circuit by giving the proper sequence of binary. (7) Prepare the truth table. Observation: Truth Table for De-Morgan & Duality theorem: S.No. 0 1 2 3 Inputs A B 0 0 1 1 0 1 0 1 De-Morgan’s first theorem A� B A. B De-Morgan’s second theorem A.B A. � B Duality theorem A+1=1 A.1 = 0 Simplification of Boolean Functions [51] Result: Verified the De-Morgan’s and duality theorems. Precautions: 1. Check all gates inside the IC before using them in the circuit. 2. Check the power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-3.2 Object: To study and verify the Boolean laws. Equipment/Components required: 1. Equipment: Power Project board, Multi-channel CRO, and Digital Multimeter. 2. Components: ICs: One 7408 (Quadruple 2-input AND gates), One 7432 (Quadruple 2-input OR gates), One 7404 (Hex inverter). ), and one 7421 (Dual 4input AND gates). Diode: One LED Miscellaneous: One Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: Named after its inventor, George Boole (1954), Boolean algebra defines constants, variables, and functions to describe binary systems . It describes a number of theorems that can be used to manipulate logic expressions. Boolean operators are the codes for the basic logic gates. Boolean constants consist of 0 and 1. Boolean variables are quantities that can take different values at different times. They may represent input, output or intermediate signals and are given names consisting of alphabetic characters such as A, B, C, X or Y. Boolean variables may only take the values 0 or 1. The following are the commonly used Boolean laws. a. Commutative law: It states that the elements of a function can be arranged in any sequence provided the connective is the same. Commutative law can also be stated as: the order in which terms are ANDed or ORed together is unimportant.Therefore, the OR operation is commutative. (i) A+ B= B +A [52] Experiments in Digital Electronics ORing-the two inputs to OR gate have been interchanged. The output is the same. 1 4 32 2 = 3 5 32 6 Fig.3.2.1: Logic diagram : Commutative law for OR logic. The AND operation is commutative. (ii) A.B = B.A ANDing- the two inputs to AND gate has been interchanged. The output is the same. 1 2 08 3 = 4 5 08 6 Fig.3.2.2: Logic diagram : Commutative law for AND logic. Truth table for commutative law is given in table 3.2.1 Table 3.2.1: Truth table for commutative law S.No. Inputs 0 1 2 3 A 0 0 1 1 b. B 0 1 0 1 Commutative (ORing) A+B B+A 0 0 1 1 1 1 1 1 Commutative (ANDing) A.B B.A 0 0 0 0 0 0 1 1 Distributive law: The distributive laws allow the factoring or multiplying of expressions. Two distributive laws are considered. (i) A + (B . C) = (A + B) . ( A + C ) Figure 3.2.3 illustrates the distributive law. The AND gate gives an output B.C. These signals, when fed to OR gate along with input A, gives the output A + (B. C).In the circuit on right hand side, the two OR gates give the output (A + B) and ( A + C ) respectively. The AND gate gives the output (A + B). (A + C). Simplification of Boolean Functions [53] 1 A Y=A+BC 32 2 3 A B 1 2 32 3 1 08 2 4 1 B 08 2 C 3 C 5 32 Y=(A+B).(A+C) 3 6 Fig.3.2.3: Logic diagram : Distributive law (OR over AND). Truth table for distributive law (i) is given in table 3.2.2. Table 3.2.2: truth table for distributive law S.No. Distributive law (i) A+(B.C) A+B A+C 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Inputs A 0 0 0 0 1 1 1 1 0 1 2 3 4 5 6 7 (ii) B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 B.C 0 0 0 1 0 0 0 1 (A+B).(A+C) 0 0 0 1 1 1 1 1 A. (B + C) = A .B + A. C Fig. 3.2.4 illustrates the distributive law. The OR gate gives an output B + C. This is fed as input to the AND gate along with input A. On the right hand side, the two AND gates give the output (A. B) and (A. C) respectively. The OR gate gives the output (A. B) + (A. C). 1 2 1 2 32 3 08 4 5 08 3 = 9 10 08 6 4 5 32 8 Fig.3.2.4: Distributive law (AND over OR). 6 [54] Experiments in Digital Electronics Truth table for distributive law (ii) is given in table 3.2.3. Table 3.2.3: truth table for distributive law S.No. 0 1 2 3 4 5 6 7 Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 B+C 0 1 1 1 0 1 1 1 Distributive law (ii) A.C A.(B+C) A.B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 1 (A.B)+(A.C) 0 0 0 0 0 1 1 1 c. Associative law: This law merely states that in any Boolean function containing elements (A, B, C etc) separated by the same connective, it does not matter if some of the elements are considered as a group. (i) A + B + C = A + (B + C) = (A + B) + C Fig.3.2.5 shows the associative law for ORing. The inputs to OR gates have been grouped in two different ways, but the output is the same, i.e. y = A+B+C. 9 1 8 2 32 3 10 32 = 12 4 32 5 13 32 11 6 Fig.3.2.4: truth table for Associative law Truth table for associative law (i) is given in table 3.2.4 Table: 3.2.4 S.No. Inputs Associative law (i) A B C B+C A+(B+C) A+B (A+B)+C 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 2 0 1 0 1 1 1 1 3 0 1 1 1 1 1 1 4 1 0 0 0 1 1 1 5 1 0 1 1 1 1 1 6 1 1 1 1 1 1 1 7 1 1 1 1 1 1 1 Simplification of Boolean Functions [55] (ii) A.B.C = A.(B.C) = (A.B).C Fig.3.2.6 shows the associative law for ANDing. The inputs to AND gates have been grouped in two different ways without affecting the output. In each case, the output is y = A.B.C. Y=A.(B.C) 12 A 08 13 A B 1 2 4 08 3 C 08 5 6 B Y=(A.B).C C 11 9 10 08 8 B.C Fig.3.2.6: Associative law for AND logic. Truth table for associative law (ii) is given in table 3.2.2 Table 3.2.5: Truth table for associative law S.No. Inputs A 0 0 0 0 1 1 1 1 0 1 2 3 4 5 6 7 d. B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 B.C 0 0 0 1 0 0 0 1 Associative law (ii) A.(B.C) A.B 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 (A.B)C 0 0 0 0 0 0 0 1 Absorption law: This law is extremely important for the elimination of redundant functions in a system. (i) A (A + B) = A Fig.3.2.7 shows the law of absorption. The output is logic 0 when A is 0 and logic 1 when A is 1, irrespective of the state of B. 1 A 2 Y=A.(B+A) 08 3 1 B 2 32 3 (A+B) Fig.3.2.7: Absorption law for OR-AND logic. [56] Experiments in Digital Electronics Truth table for absorption law (i) is given in table 3.2.6 Table 3.2.6: Truth table for absorption law (i) S.No. Inputs 0 1 2 3 4 5 6 7 A 0 0 0 0 1 1 1 1 (ii) A + AB = A B 0 0 1 1 0 0 1 1 Output A+B 0 0 1 1 1 1 1 1 A(A+B) 0 0 0 0 1 1 1 1 Fig.3.2.8 shows the another law of absorption. The output is logic 0 when A is 0 and logic 1 when A is 1, irrespective of the state of B. A 1 1 B 2 3 08 32 2 3 Y=A+A.B= A Fig.3.2.8: Absorption law for AND-OR logic. Truth table for absorption law (ii) is given in table 3.2.2 Table 3.2.7: truth table for absorption law (ii) S.No. 0 1 2 3 4 5 6 7 Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 AB 0 0 0 0 0 0 1 1 output A+(AB) 0 0 0 0 1 1 1 1 Simplification of Boolean Functions [57] e. Idempotent law: This law states that if a variable is ANDed or ORed with itself any number of times, the result is always original variable. (i) A = A.A.A.A...... Fig. 3.2.9 shows the law of idempotent for ANDing. The output is variable itself, ‘A’ whatsoever, the value of A. 1 2 4 5 A A A A 7421 6 Y=A Fig.3.2.9: Idempotent law for AND logic. Truth table for idempotent law (i) is given in table 3.2.8 Table: 3.2.8: : truth table for idempotent law for AND gate Inputs A 0 1 (ii) A 0 1 Output A 0 1 A.A.A 0 1 A = A + A + A + A + .... .... Fig.3.2.10 shows the another law of idempotent for ORing. The output is variable itself ‘A’ whatsoever, the value of A. 1 A 2 A A 3 32 4 5 32 A 9 6 10 32 Y=A 8 A A Fig: 3.2.10 Idempotent law for OR logic. Truth table for idempotent law (ii) is given in table 3.2.9 Table: 3.2.9: truth table for idempotent law for OR gate A 0 1 Inputs A 0 1 A 0 1 Output A+A+A 0 1 [58] Experiments in Digital Electronics f. Complementation law: This law states that if a function consists of a variable and its inverse, then the function is a constant. (i) A.A � 0 Since an AND gate requires both inputs to be logic 1 for a logic 1 output, it is always logic 0, since A and A can never be logic 1 simultaneously.. This is shown in Fig.3.2.11 Fig.3.2.11: Complementation law for AND logic. Truth table for complementation law (i) is given in table 3.2.10 Table 3.2.10: truth table for complementation law A 0 1 (ii) Inputs Output 1 0 0 0 A � A �1 Since an OR gate requires only one input to be logic 1 for logic 1 output, either must be 1 at any time, so the result of A � A is always logic 1. This is shown in Fig.3.2.12. Fig.3.2.12: Complementation law for OR logic. Truth table for complementation law (ii) is given in table 3.2.11 Table 3.2.11: truth table for complementation law A 0 1 Inputs Output 1 0 1 1 Simplification of Boolean Functions [59] Procedure: (1) Insert the ICs into the breadboard. Connect the power supply to the ICs on the proper pin. (2) Construct the abovementioned circuits. (3) Connect the inputs of the gate to the switches provided on the trainer or hook them up to the +5V supply (logic 1) or ground (logic 0) to giving proper sequence of binary. (4) Connect the output to the LED monitor on the trainer or hookup it to a LED with the proper current limiting resistor. (5) Turn on the trainer/power project board. (6) Check the output of each circuit. (7) Prepare the truth table for each. Observation Table: a. Commutative law: Truth table for commutative law. Inputs Decimal 0 1 2 3 b. A 0 0 1 1 Commutative (ORing) A+B B+A B 0 1 0 1 Commutative (ANDing) A.B B.A Distributive law: Truth table for distributive law (i). Decimal 0 1 2 3 4 5 6 7 Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 B.C Distributive law (i) A+B.C A+B A+C (A+B).(A+C) [60] Experiments in Digital Electronics Truth table for distributive law (ii). Decimal A 0 0 0 0 1 1 1 1 0 1 2 3 4 5 6 7 c. Inputs B 0 0 1 1 0 0 1 1 Distributive law (ii) C B+C A.(B+C) A.B A.C (A.B)+(A.C) 0 1 0 1 0 1 0 1 Associative law: Truth table for associative law (i) Decimal Inputs A 0 0 0 0 1 1 1 1 0 1 2 3 4 5 6 7 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 1 1 B+C Associative A+(B+C) A+B (A+B)+C Truth table for associative law (ii) Decimal 0 1 2 3 4 5 6 7 Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 B.C A.(B.C) Associative A.B (A.B)C Simplification of Boolean Functions [61] d. Absorption law: Truth table truth table for absorption law Decimal A 0 1 2 3 4 5 6 7 e. B C Output A+B AB A(A+B) A+(AB) Idempotent law: Truth table for idempotent law Inputs A 0 1 f. Inputs A 0 1 A 0 1 A.A.A=A 0 1 Output A+A+A=A 0 1 Complementation law: Truth table for complementation law A 0 1 Inputs 1 0 0 0 =0 Output 1 1 Result: Verified the Boolean laws. Precautions: 1. Check all gates in the ICs before use. 2. Check power supplies of the power project board and single-core wires. 3. Do not leave an input floating. EXPERIMENT-3.3 Object: Design and verify a circuit with universal gates that implements the Boolean functions:Y1 � AB � CD � SOP form, and Y2 � ( A � B ).(C � D ) � POS form �Dual of Y1 � Equipment/Components required: 1. Equipment: Power Project board and Digital Multimeter. [62] Experiments in Digital Electronics 2. Components: ICs: One 7408 (Quadruple 2-input AND gates), One 7432 (Quadruple 2-input OR gates), Two 7400 (Quadruple 2-input NAND gates),Two 7402 (Quadruple 2-input NOR gates). Diode: One LED Miscellaneous: One Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: Digital circuits are frequently constructed with NAND or NOR gates rather than with AND and OR gates. Universal gates are easier to fabricate with electronic components and are the basic gates used in all IC digital logic families. Two-level implementation of the above given Boolean function are: (i) SOP function: If the Boolean function is in the form of a sum of product (SOP), then consider the given logic function in the sum of product form; Y1 � AB � CD .This function can be implemented with (a) AND and OR gates, (b) NAND-NAND, and (c) NOR-NOR as shown in Fig.3.3.1. In (b) AND and OR gates are replaced by NAND gates with an OR-invert graphic symbol (bubbled OR). Similarly in (c) AND and OR gates are replaced by NOR gates. Therefore, the given SOP equation is implemented by universal gates only, but a minimum number of gates/IC is required in NAND-NAND implementation. A B C D 1 2 A 3 08 1 2 4 5 B Y=AB+CD 32 = 3 C 08 6 D 1 2 00 3 4 9 10 Y=AB+CD 00 5 00 6 8 IC 7408 used : 01, IC 7432 used : 01 IC 7400 used : 01 (a) (b) 2 A 3 02 1 8 9 5 B 6 02 02 10 4 11 12 5 C 6 02 D 9 08 13 02 4 2 3 8 Y=AB+CD 02 02 1 IC 7402 used : 02 Fig.3.3.1: Two level implementation of SOP form. Simplification of Boolean Functions [63] (ii) POS function: If the Boolean function in product sum of (POS) form. Consider the given logic function in POS form; Y2 � ( A � B).(C � D) .This function can be implemented with (a) OR and AND gates, (b) NAND-NAND, and (c) NOR-NOR, as shown in Fig.3.3.2. In (b) the AND gates are replaced by NAND gates and the OR gates by NAND gates with an OR-invert graphic symbol (bubbled OR), similarly in (c) the OR gates and the AND gates by NOR gates and the OR gates. Remember that a bubble denotes complementation and two bubbles along the same line represent double complementation, so both can be removed. Therefore, the given POS equation is implemented by universal gates only, but minimum number of gates/IC is required for NOR-NOR implementation. 1 A B C D 1 2 32 2 32 00 3 1 2 1 4 5 A 3 Y=(A+B).(C+D) 08 3 2 4 B 00 3 00 6 9 5 6 IC7432 used : 01, IC7408 used : 01, ORgate used : 02, ANDgate used : 01 C (a) 2 A 1 02 3 8 B Y=(A+B).(C+D) D 02 9 10 5 C 02 6 4 D 10 9 00 10 4 5 12 00 13 8 6 00 11 IC 7400 used : 02, NAND gate used : 07 (b) IC 7402 used : 01, NOR gate used : 03 (c) Fig.3.3.2: Two level implementation of POS form. Procedure: (1) Insert the ICs in the proper place on breadboard. Connect the power supply to the ICs on the proper pin. (2) Construct the abovementioned circuits. (3) Connect the inputs of the gate to the switches provided on the trainer or hook them up to the +5V supply (logic 1) or ground (logic 0) to giving proper sequence of binary. (4) Connect the output to the LED monitor on the trainer or hookup it to a LED with proper value of current limiting resistor. (5) Turn on the trainer/power project board. [64] Experiments in Digital Electronics (6) Check the output of each circuit. (7) Prepare the truth table for each. Observation Table: Truth table for the given SOP/ POS form. S.No. A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 In pu ts B C D 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 AN DOR Outputs (S OP fo rm ) NAN D-N ANDNOR -NO R OR AND O utputs ( PO S form ) N OR- NOR NANDNA ND Result: Verified the output of Boolean functions using different implementations (SOP and POS form). Precautions: (1) Check all gates in the ICs before using them. (2) Check power supplies of the power project board. (3) Do not leave an input floating. [65] 4. Combinational Logic Circuits-Arithmetic Circuits EXPERIMENT-4.1 Object: Design and verify the operation of a half-adder circuit using a minimum numbers of gates. Equipment/Components required: 1. 2. Equipment: Power project board and Digital Multimeter. Components: ICs: One 7408 (Quadruple 2-input AND gates), One 7432 (Quadruple 2-input OR gates), One 7404 (Hex inverter), Two 7400 (Quadruple 2input NAND gates),Two 7402 (Quadruple 2-input NOR gates), One 7486 ( Quadruple 2-input EX-OR gates) and One 7411 (Triple 3-input AND gates). Diode: Two LED Miscellaneous: Two Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: A half adder is a circuit that has two inputs, A and B, and two outputs, sum and carry. It is a combinational circuit that performs the addition of two bits according to the rules for binary addition. The input variables designate the augends and addend bit; the output variables produce the sum and carry them. Applications of half-adders are very limited because they can not accept a carry from a previous addition. The block diagram and truth table for a half-adder are shown in Fig.4.1.1. Inputs S.No. A Sum B Carry 1 2 3 4 A B (Augends) (Addend) 0 0 0 1 1 0 1 1 Outputs C S (Carry) (Sum) 0 0 0 1 0 1 1 0 (a) (b) Fig.4.1.1: half adder (a) block diagram and (b) truth table [66] Experiments in Digital Electronics From the truth table, it is clear that the sum (S) output is identical to the EX-OR gate output and the carry (C) output is identical to the AND gate output. Hence, the expressions of sum and carry are: S � AB � AB C = AB The products of sum expressions are: S � � A � B � .� A � B � C = A + B {k - map simplification} The more complicated the expression, the more complex is the gate network. It is, therefore, best to simplify an expression as much as possible to get the simplest gate network. There are two standard or canonical forms used to express any combination of logic network: the sum-of-products (SOP) form and the product-ofsum (POS) form. In this experiment, the SOP form was taken to implement the logic diagram for the half-adder circuit. There are different ways to implement the logic diagram for the half-adder circuit. Some of them are: (i) Using Ex-OR gate and AND gate; 1 2 86 3 (Sum) 1 2 08 3 (Carry) Fig. 4.1.2: Logic diagram of a half adder using Ex-OR and AND. (ii) Using AND,OR and NOT gate; A B 1 2 08 3 1 2 3 32 S (Sum) 4 5 08 6 9 10 08 8 C (Carry) Fig. 4.1.3: Logic diagram of a half adder using basic gates. Combinational Logic Circuits-Arithmetic Circuits [67] (iii) Using NAND-NAND gates; S � AB � AB � AB � AB � A A � B B � A( AB) � B( AB) � A( AB) � B( AB) � A( AB).B( AB) C � AB 1 2 4 6 5 00 3 00 12 11 (Sum) 00 13 9 10 00 8 1 3 (Carry) 2 00 Fig. 4.1.4: Logic diagram of a half adder using only NAND gates. (iv) Using NOR-NOR gates. S � AB � AB � AB � AB � A A � BB � ( A � B).(A � B) � ( A � B) � ( A � B) C � AB � A � B 2 3 02 1 1 2 02 3 SUM 5 02 A 4 6 11 12 02 13 CARRY 8 02 B 9 10 Fig. 4.1.5: Logic diagram of a half adder using only NOR gates. Observing the above logic circuits, a minimum number of gates are required to implement the half-adder circuit, when using only universal gates, Procedure: (1) Insert the ICs into the breadboard. Connect the power supply to the proper pin of the chip. (2) Construct the abovementioned logic circuits. (3) Connect the inputs of the gate to the switches provided on the trainer or hook them up to the +5V supply (logic 1) or ground (logic 0) to giving proper sequence of binary. [68] Experiments in Digital Electronics (4) Connect the LEDs to the sum and carry outputs, or hookup them to a LED with a current limiting resistor. (5) Turn on the trainer/power project board. (6) Check the output of each circuit by giving the proper sequence of binary. (7) Prepare the truth table. Observation Table: Truth table for half adder Inputs Outputs S.No. A B C S (Augends) (Addend) (Carry) (Sum) 1 0 0 2 0 1 3 1 0 4 1 1 Result: Verified the above half adder circuits. Precautions: 1. Check all gates in the ICs before making them used in the logic circuits. 2. Be sure about the pin out diagram of the IC. 3. Check power supplies of the power project board. 4. Do not leave an input floating. EXPERIMENT-4.2 Object: Design and verify the operation of a full-adder circuit using a minimum number of gates. Equipment/Components required: 1. Equipment: Power Project board and Digital Multimeter. 2. Components: ICs: One 7408 (Quadruple 2-input AND gates), One 7432 (Quadruple 2-input OR gates), One 7404 (Hex inverter), Two 7400 (Quadruple 2input NAND gates),Three 7402 (Quadruple 2-input NOR gates), One 7486 ( Quadruple 2-input EX-OR gates) and 7411. Diode: Two LED Miscellaneous: Two Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: Whereas the half adder added two inputs, A and B, the full adder adds three inputs together, A, B, and a carry from a previous addition, and outputs a sum and carry. A full adder is a combinational circuit that performs the arithmetic sum of three Combinational Logic Circuits-Arithmetic Circuits [69] bits. It consists of three inputs and two outputs. Three inputs mean two significant bits and a previous carry and two outputs are sum and carry. The truth table follows the rules for binary addition. The block diagram and truth table for a full adder are shown in Fig.4.2.1. Decimal 0 1 2 3 4 5 6 7 Sum A B C in Carry Out Inputs Cin B A (input carry) (Addend) (Augends) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Outputs Cout S (Sum) (outputc arry) 0 0 0 1 0 1 1 1 (a) (b) Fig.4.2.1: full adder (a) block diagram and (b) truth table 0 1 1 0 1 0 0 1 Using k-map simplification techniques for SOP form, the simplified expression for sum and carry outputs are; S � Cin BA � C in B A � Cin B A � Cin BA � Cin � B � A C � Cin B � Cin A � BA The logic diagram of the full adder is implemented in the following way: (i) Using EX-OR gates and Basic gates. S � Cin � B � A C � Cin .B. A � Cin .B. A. � Cin .B. A � Cin . A.B � BA � Cin � A � B� 1 2 86 34 5 86 6 1 08 3 1 2 2 4 08 6 5 32 3 Fig. 4.2.2: Logic diagram of a full adder using EX-OR, AND and OR. (ii) Using basic gates. S � Cin BA � C in B A � Cin B A � Cin BA C � Cin B � Cin A � BA [70] Experiments in Digital Electronics Cin B A 5 3 6 4 1 2 1 2 13 11 12 1 32 3 4 5 11 11 1 2 08 9 5 6 3 8 32 13 1 32 2 6 08 08 SUM(S) 8 4 12 9 10 32 10 12 4 5 3 8 32 1 2 13 6 11 9 10 11 2 3 8 Fig. 4.2.3: Logic diagram of a full adder using basic gates (iii) Using two inputs NAND-NAND combinations; S � Cin � B � A � X � A � X XA . A XA {where X � Cin � B } ......(5.2.7) Cout � Cin B � Cin A � BA � (Cin B � Cin A ) � BA � (Cin B � Cin A) .BA � (Cin B.Cin A) .BA ......(5.2.8) {using K � map} Cout � C in BA � Cin B A � Cin B A � Cin BA � A( Cin � B ) � Cin B {using Boolean laws ) ......(5.2.9) � A( Cin � B ) � Cin B � A( Cin � B).Cin B � AX .Cin B Cin B 4 00 5 1 2 00 12 00 3 5 11 1 13 9 10 00 4 00 6 6 2 8 00 00 3 11 13 9 00 8 10 A 12 1 3 2 00 Fig. 4.2.4: Logic diagram of a full adder using only NAND gates. (iv) Using only two-input NOR-NOR gates. S � Cin � B � A � X � A � ( X � A) � (A � X) {where X � Cin � B } .....(5.2.1) Cout � C in BA � Cin BA � Cin B A � Cin BA � A( Cin � B) � Cin B {using Boolean laws) � AX � Cin B � ( A � X ) � (C in � B) .....(5.2.8) Combinational Logic Circuits-Arithmetic Circuits [71] 5 6 Cin B 2 02 3 8 02 02 13 11 02 12 1 9 A 4 5 1 6 42 1 02 3 02 2 02 11 02 13 3 12 8 10 5 4 6 02 11 02 12 13 8 02 10 9 02 10 9 Fig. 4.2.5: Logic diagram of a full adder using only NOR gates. Procedure: (1) Insert the ICs into the breadboard. Connect the power supply to the proper pin of the chip. (2) Construct the abovementioned logic circuits. (3) Connect the inputs of the gate to the switches provided on the trainer or hook them up to the +5V supply (logic 1) or ground (logic 0) to giving proper sequence of binary. (4) Connect the LEDs to the sum and carry outputs, or connect them to a LED with a current limiting resistor. (5) Turn on the trainer/power project board. (6) Check the output of each circuit by giving the proper sequence of binary. (7) Prepare the truth table. Observation Table (Truth table for full adder): S.No. 0 1 2 3 4 5 6 7 Cin (input carry) Inputs B (Addend) A (Augends) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Result: Verified the full adder circuits. Outputs Cout (Carry) S (Sum) [72] Experiments in Digital Electronics Precautions: 1. Check all gates used in the logic circuits. 2. Check power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-4.3 Object: To study the 4-bit full adder IC7483 and verifiy its operation. Equipment/Components required: 1. Equipment: Power Project board and Digital Multimeter. 2. Components: ICs: One 7483 Diode: Four LEDs Miscellaneous: Four Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: Fig.4.3.1 shows the 4-bit full adder IC 7483, which is classified as a Medium Scale Integration, TTL circuit with four full-adders. Table 4.3.1 lists some of the available 4-bit full adder ICs. Table 4.3.1: Medium Scale Integration, 4-bit Adder Circuits ICs Device No. 7483 74C83 4008 Family TTL CMOS CMOS Description 4-bit binary adder with fast carry, output: TP 4-bit binary adder with fast carry 4-bit full adder with fast carry Fig.4.3.1 (a) shows the pin assignment of IC 7483 and (b) the function table specifies the circuit operation. The IC 7483 is a 4- bit binary parallel adder having eleven inputs (8-pins for two 4-bit addition,2-pins for power supply, and 1-pin for carry input) and five outputs (4-pins for sum and 1-pin for carry out) dual in package. Here the two 4-bit input binary numbers are A (A1 through A4) and B (B1 through B4). The four bit sum is obtained from S (S1 through S4). C0 , C4 are the input carry and the carry output. Combinational Logic Circuits-Arithmetic Circuits [73] Inputs Outputs Data A Data B Addition C0 A4 A3 A2 A1 B4 B3 B2 B1 S3 S2 S1 1 0 0 0 0 0 0 0 0 C4 S4 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 1 1 0 1 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 (a) (b) Fig.4.3.1: IC 7483 (a) pinout diagram, (b) the functional table The IC 7483 can add 4-bits (nibbles). To add bytes, we need to use two 7483s as cascading (the carry out of the lower IC7483, is used as the carry in to the upper IC7483). This allows the two 7483s to add 8-bit numbers. It can be constructed with the help of four full adders which are connected in cascaded, with the output carry from each full adder connected to the input carry of the next full adder in the chain. Writing a truth table for nine inputs creates a table of 512 lines (29). The truth table shown has been reduced to 16 lines. The note below the truth table explains that the table is used in two steps.A1, B1, A2, B2, and C0 determine the outputs S1, S2 and C4 that are internal to the IC.C2 is then used with A3, B3, A4, and B4 to determine S1, and C4. output When C0 = 1 When C0 = 0 Input when C 2= 0 B2 A2 B1 A1 C2 B4 A4 B3 A3 C4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 S2 S4 0 0 0 1 1 1 1 0 1 1 1 0 0 0 0 1 S1 S3 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 when C2 = 1 C2 C4 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 S2 S1 S4 S3 0 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 [74] Experiments in Digital Electronics Note: input conditions at A1, B1, A2, B2 and C0 are used to determine outputs S1 and S2 and the value of the internal carry C2. The values at C2, A3, B3, A4 and B4 are then used to determine outputs S3, S4, and C4. Procedure: (1) Insert IC 7483 on the logic trainer board. Connect the power supply to the proper pin of the chip and carry input to logic ‘0’. (2) Connect the LEDs to the sum and carry outputs with current limiting resistor. (3) Connect inputs of the gate to the switch provided on the trainer/board or hook them up to the +5V supply (logic 1) or ground (logic 0) as required. (4) Vary these inputs from 0000 to 1111 and observe LED outputs at sums and carry out. (5) Prepare the truth table. Observation Table: Inputs Decimal C0 A4 A3 A2 A1 outputs B4 B3 B2 B1 C4 S4 S3 Result: Verified the 4-bit parallel adder using an IC. Precautions: 1. Check all the full adder's outputs before giving inputs. 2. Check power supplies of the power project board. 3. Do not leave an input floating. S2 S1 Combinational Logic Circuits-Arithmetic Circuits [75] EXPERIMENT-4.4 Object: Design and verify the operation of BCD adder using IC 7483 and basic gates. Equipment/Components required: 1. Equipment: Power Project board and Digital Multimeter. 2. Components: ICs: Two 7483 (4 bit parallel adder) ,One 7408 (Quadruple 2-input AND gates), One 7432 (Quadruple 2-input OR gates). Diode: One LED Miscellaneous: One Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: BCD (Binary-Coded-Decimal) uses four bits to represent a decimal number, as shown in Fig.4.4.1. Although valid BCD numbers must stop at nine, there are six more counts before all four columns are full. These six steps are not valid BCD numbers. In BCD addition, care must be taken to compensate for these six invalid states. If overflow occurs during an addition, or if one of the invalid states occurs as result of an addition, then six must be added to the result to flip through the unwanted states. It is a decimal adder. Computers or calculators that perform arithmetic operations directly in the decimal number system represent decimal numbers in Binary Coded Decimal form (BCD). An adder for such a computer must employ arithmetic circuits that accept coded decimal numbers and present results in the same code. A decimal adder requires a minimum of nine inputs and five outputs, since four bits are required to code each decimal digit and the circuit must have an input and output carry. Consider the arithmetic addition of two decimal digits to BCD, together with an input carried from a previous stage. Since each input digit does not exceed 9, the output sum can’t be greater than 9+9+1=19, the 1 in the sum being an input carry. Suppose we apply the two BCD digits to a 4-bit binary adder. The adder will form the sum in binary and produce a result that ranges from 0 through 19.These are binary numbers that are listed in table 4.4.1 and are labeled by symbols Cin, S3, S2, S1, and S0. The Cin is the input carry, and the subscripts under the letter S represent the weights 8, 4, 2, and 1 that can be assigned to the four bits in the BCD code. [76] Experiments in Digital Electronics Table 4.4.1 : Truth table for BCD adder S.No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Cin 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 Binary Sum S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 S8 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 BCD Su m S4 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 S2 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 S1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 The columns under the binary sum list the binary value that appears in the outputs of the 4-bit binary adder. The output sum of two decimal digits must be represented in BCD and should appear in the form listed in the column under BCD sum. The problem is to find a rule by which the binary sum is converted to the corrected BCD digit representation of the number in the BCD sum. In examining the contents of the table, it is apparent that when the binary sum is equal to or less than 1001, the corresponding BCD number is identical and therefore no conversion is needed. When the binary sum is greater than 1001, we obtain a nonvalid BCD representation. The addition of binary 6 (0110) to the binary sum converts it to the correct BCD representation and also produces an output carry as required. Logic Circuit: It is obvious that a correction is needed when the binary sum has an output carry (Cout) =1.The other six combinations from 1010 through 1111 that need a correction have a 1 in position S8, we specify further that either S 4 or S2 must have a 1.The condition for a correction and an output carry can be expressed by the Boolean function Z = S1S3 + S2S3 + Cout .When Z = 1, it is necessary to add 0110 to the binary sum and provide an output carry for the next stage. Combinational Logic Circuits-Arithmetic Circuits [77] B3 B2 B1 B0 A3 A2 A1 A0 7483-1 6 4 5 1 08 3 3 2 32 4 2 6 08 5 1 7483-2 Fig.4.4.1: Logic diagram of BCD adder using IC 7483 and basic gates Procedure: (1) Insert ICs on the logic trainer board. Connect the power supply to the proper pin of the chip and carry input to logic ‘0’. (2) Connect the power supply to the proper pin of the chip. (3) Connect the LEDs to the sum and carry outputs with a current limiting resistor. (4) Connect the inputs of the gate to the switch provided on the trainer/ board or hook them up to the +5V supply (logic 1) or ground (logic 0) as required. (5) Vary these inputs from 0000 to 1111 and observe LED outputs at sums and carry out. (6) Prepare the truth table. [78] Experiments in Digital Electronics Observation Table: S.No. Inputs Cin A3 A2 A1 A0 B3 B2 B1 B0 Cout S3 Outputs S2 S1 S0 Result: Verified the BCD adder circuit. Precautions: 1. Check all full adders inside the 7483 IC before giving them to inputs. 2. Check power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-4.5 Object: Design and verify the operation of half-subtraction circuits with a minimum number of gates. Equipment/Components required: 1. Equipment: Power Project board and Digital Multimeter. 2. Components: ICs: One 7408 (Quadruple 2-input AND gates), One 7432 (Quadruple 2-input OR gates), One 7404 (Hex inverter), Two 7400 (Quadruple 2input NAND gates), Two 7402 (Quadruple 2-input NOR gates), One 7486 (Quadruple 2-input EX-OR gates). Diode: One LED Miscellaneous: One Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: Half subtraction a combinational circuits that subtracts two binary bits and produces two outputs, difference (D) and borrow (B). It subtracts the LSB of the Combinational Logic Circuits-Arithmetic Circuits [79] subtrahend from the LSB of the minuend. The truth table follows the rules for binary subtraction. The block diagram and truth table for a half subtraction are shown in Fig.4.5.1. S.No. 1 2 3 4 Inputs Outputs A B D B (Minuend) (Subtrahend) (Difference) (Bo rrow) 0 0 1 1 0 1 0 1 0 1 1 0 0 1 0 0 (a) (b) Fig.4.5.1: half subtractor (a) block diagram and (b) truth table The sum of products expressions for difference and borrow outputs are: D � AB � AB B � AB The logic diagram of the half subtraction is implemented with following ways: a. X-OR gate and AND, and NOT gate; 1 2 A B 1 86 2 1 2 3 Diff 3 Borrow Fig. 4.5.2: Logic diagram of a half subtractor using Ex-OR, AND, and NOT. b. AND, OR and NOT gate; Fig. 4.5.3: Logic diagram of a half subtractor using basic gates. [80] Experiments in Digital Electronics c. NAND-NAND gates; D � AB � AB � AB � AB � AA � BB � A(AB) � B(AB) � A(AB) � B(AB) � A(AB).B(AB) � B � AB � AB � BB � B A � B � � � � � � B AB � B. AB 4 1 3 00 2 5 00 9 10 00 6 12 8 11 00 D 13 1 3 00 B 2 Fig. 4.5.4: Logic diagram of a half subtractor using only NAND gates. d. NOR-NOR gates. D � B � � A � B � � A � �A � B � B � A B � AA � A � A � B � � A � � A � B � 5 B 6 4 11 2 3 02 02 1 12 8 A 2 02 13 02 3 1 02 9 10 Fig. 4.5.5: Logic diagram of a half subtractor using NOR gate. Procedure: (1) (2) (3) Insert the ICs into the breadboard. Connect the power supply to the proper pin of the chip. Construct the abovementioned logic circuits. Connect the inputs of the gate to the switches provided on the trainer or hook them up to the +5V supply (logic 1) or ground (logic 0) to giving proper sequence of binary or you may use 2-bit binary up counter with de bounce switch as a clock. Combinational Logic Circuits-Arithmetic Circuits [81] (4) Connect the LEDs to the sum and carry outputs, or hookup them to a LED with current limiting resistor. (5) Turn on the trainer/power project board. (6) Check the output of each circuit by giving the proper sequence of binary. (7) Prepare the truth table. Observation: Truth Table for half-subtractor S.No. 1 2 3 4 A (Minuend) 0 0 1 1 Inputs B (Subtrahend) 0 1 0 1 Outputs D B (Difference) (Borrow) Result: Verified the half-subtractor circuits. Precautions: 1. Check all gates in the ICs before using them. 2. Check power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-4.6 Object: Design, construct and verify full subtraction circuits with a minimum number of gates. Equipment/Components required: 1. Equipment: Power Project board and Digital Multimeter. 2. Components: ICs: Two 7408 (Quadruple 2-input AND gates), Two 7432 (Quadruple 2-input OR gates), One 7404 (Hex inverter), Three 7400 (Quadruple 2input NAND gates), Two 7402 (Quadruple 2-input NOR gates), One 7486 (Quadruple 2-input EX-OR gates). Diode: One LED Miscellaneous: One Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: Full subtraction is a combinational circuit that performs a subtraction of two bits, taking into account borrowing form the lower significant stage. This circuit has three inputs named minuend (A), subtrahend (B), and previous borrow (bin) and two outputs, called difference (D) and a borrow (B). The truth table follows the rules for [82] Experiments in Digital Electronics (a) bi (input borrow) B 0 0 1 1 0 0 1 1 B (Borrow) D B Full Subtractor 0 0 0 0 1 1 1 1 D (difference) A B bin 0 1 2 3 4 5 6 7 (subtrahend) S.No. A (minuend) binary subtraction. The block diagram and truth table for a full subtraction are shown in Fig.4.6.1. Inputs Outputs 0 1 1 0 1 0 0 1 0 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 (b) Fig.4.6.1: full subtractor (a) block diagram and (b) truth table Using k-map simplification techniques, the simplified expression for difference and borrow outputs are; . .bin � ABbin � ABbin � A � B � bin D � A.B.bin � AB B � Abin � AB � Bbin {Using K � map} a. B � bin ( A � B) � AB {Using Boolean laws} The logic diagram of the full subtractor is implemented in the following way: Using EX-OR gates and NAND gate. D � A.B.bin � AB . .bin � ABbin � ABbin � A � B � bin B � bin ( A � B) � AB {Using Boolean laws} B � bin ( A � B ) � AB � bin ( A � B ). AB A B 1 2 86 3 4 86 Difference 6 5 bin 1 2 00 3 4 5 00 6 1 2 9 10 00 8 00 3 Borrow 12 13 00 11 Fig. 4.6.2: Logic diagram of a full subtractor using Ex-OR and NAND gate. Combinational Logic Circuits-Arithmetic Circuits [83] b. Using basic gates. . in � A.B.bin � A.B.bin � A.B.bin � A � B � bin D � A.Bb B � Abin � AB � Bbin {Using K � map} bin B A 04 04 08 08 32 08 08 Difference 32 08 08 32 08 08 Fig. 4.6.3: Logic diagram of a full subtractor using basic gates. c. A B Using two half subtraction and OR gate. Half Subtractor 1 Half Subtractor 2 Difference 1 2 32 3 Borrow bin Fig. 4.6.4: Logic diagram of a full subtractor using two half subtract and OR gate [84] Experiments in Digital Electronics d. Using two inputs NAND-NAND combinations; 4 A 00 2 11 5 3 00 13 2 6 00 5 1 00 12 9 B 4 6 00 1 12 3 00 13 9 8 11 Difference 8 00 10 10 00 bin 1 2 3 00 Borrow IC 7400 used : 3, NAND gate used : 9 Fig. 4.6.5: Logic diagram of a full subtractor using NAND gate e. Using only two-input NOR-NOR gates. D � AB � AB � AB � B B � AB � A A � B( A � B) � A ( A � B ) D � B( A � B) � A ( A � B) � B � ( A � B) � A � ( A � B) D � B � ( A � B) � A � ( A � B) B � AB � A A � A ( A � B ) � A � ( A � B ) 5 A bin 6 02 2 4 11 2 02 3 1 12 B 2 02 13 3 02 1 8 02 02 6 02 Abin 4 9 11 12 02 13 1 5 02 4 Difference 6 8 5 10 02 10 9 8 9 3 02 10 11 02 13 Borrow 12 IC 7402 used : 3, NOR gate used : 12 Fig. 4.6.6: Logic diagram of a full subtractor using NOR gate Procedure: (1) Insert the ICs into the breadboard. Connect the power supply to the proper pin of the chip. (2) Construct the abovementioned logic circuits. (3) Connect the inputs of the gate to the switches provided on the trainer or hook them up to the +5V supply (logic 1) or ground (logic 0) to give the proper sequence of binary. Combinational Logic Circuits-Arithmetic Circuits [85] (4) Connect the LEDs to the sum and carry outputs. Or hookup them to a LED with a current limiting resistor. (5) Turn on the trainer/power project board. (6) Check the output of each circuit by giving the proper sequence of binary. (7) Prepare the truth table. Observation Table (Truth table for full subtractor): Decimal A (minuend) 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 Inputs B bin (subtrahend) (input borrow) 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Outputs D (difference) B (Borrow) Result: Verified the full subtractor logic circuits. Precautions: 1. Check all gates inside the ICs before using them in other logic circuits. 2. Check the power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-4.7 Object: Design, construct, and verify the operations of 1’s complement adder/subtractor circuit. Equipment/Components required: 1. Equipment: Power Project board and Digital Multimeter. 2. Components: ICs: One 7483 (4-bit binary adder with fast carry), One 7408 (Quadruple 2-input AND gate), 7404 (Hex-inverter) Two7486. ( Quadruple 2-input EX-OR gates). Diode: Five LEDs. Experiments in Digital Electronics [86] Miscellaneous: Five Resistors � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: 1’s complement addition/subtraction circuit: The subtraction of two binary numbers may be achieved by taking the 1’s complement of the subtrahend and then adding it to the minuend. To form the 1’s complement of a number, take the 1’s complement of binary number, simply change each bit. The 1’s complement of 1 is 0 and vice-versa. Design a circuit that will use a IC 7483 to add the 4-bit numbers B3, B2, B1, and B0 to the four bit binary numbers A3, A2, A1, A0 and subtract B3, B2, B1, and B0 from A3, A2, A1, A0. Use the 1’s complement methods for subtraction. To use the IC7483 4-bit full adder as a 1’s complement adder/subtractor, the following must be considered. 1. Fig. 4.7.1 shows a controlled inverter. Leave the numbers B3, B2, B1, and B0 unaltered for an addition problem, but take the 1’s complement for a subtraction problem. An EX-OR invert data (1’s complement) when the control input is high. EX-OR gates will be used to invert B3, B2, B1, and B0 for subtraction. A control signal is needed that will be 1 for subtraction and 0 for addition. A3, A2, A1, A0 will be fed directly into the IC 7483 Fig. 4.7.1: 4 -bit controlled inverter Combinational Logic Circuits-Arithmetic Circuits [87] 2. If the problem is subtraction, and if there is overflow (Cout), perform an EAC (end-around carry). To detect when subtraction and overflow occur, AND the control line with Cout . The output of the AND gate number 1 is 1 when an EAC results. But in this case, the output of AND gate number 1 can be fed directly into Cin. 3. If the problem is subtraction and if there is no carry (Cout), indicate the answer is negative and take the 1’s complement of the result to obtain the true magnitude of the answer. If Cout is invalid then an AND gate can be used to detect when a subtraction process is to be performed and when Cout is 0. The control input and Cout, are fed into AND gate number 2.A high output indicates a subtraction problem is being performed, and the answer is negative. This signal could be used to light an LED to indicate the answer is negative. Fig.4.7.2 shows the function table for 1’s complement adder/subtractor. When the control-1 (first controlled inverter) input is ‘0’ we can use the diagram as an adder, or if it is ‘1’, it can use as subtraction. The 1’s complement method for subtraction i.e. if there is a carry (called overflow), known as EAC (end around carry), add it to the LSB of sum (or fed directly into Cin) or if there no carry, indicate the negative answer with 1’s complement of the result. Table 4.7.1 summarizes the techniques to draw the design to implement of 1’s complement addition/subtraction circuit with the help of controlled inverter. Table 4.7.1: Function table for 1's complement addition/subtraction circuits Op eration add subtract C ontrol-1 C1 7483 C ou t C in C ontr ol-2 S ign bit C2 0 = +ve 1 = -ve R em ar k Ov erflo w(n eed o ne m ore b it) 0 0 1 0 1 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 (a ) No carry, ans wer is -ve with 1’s co mp le men t of s um. Wh en carr y, an swer is +v e, add carry to LSB of su m. Simplified expression for Cin and C2 of above table: C in � C1 .C out C 2 � C1 . C out [88] Experiments in Digital Electronics Control � 1�C1 � B3 0=Addition 1=Subtraction B2 B1 B0 1 2 4 5 9 10 12 13 14 VCC 7486-1 A3 A2 A1 A 0 1 1 1 3 Cin �14� 2 3 8 10 Cout �13� 8 6 3 16 4 7 11 4 2 5 2 6 12 GND 2 S3 Control � 2 �C2 � 3 1 4 9 12 2 S2 6 9 S1 S0 5 10 13 14 VCC 4 7486-2 330 � +5V LED on : Negative answer to subtraction GND 5 VCC 7483 15 1 7 11 7 GND 11 8 6 3 S3 S2 S1 S0 True Magnitude sum outputs Fig.4.7.2: 1’s complement adder/subtractor Logic circuit Procedure: (1) Insert the ICs into the breadboard. Connect the power supply to the proper pin of the chip. (2) Construct the abovementioned logic circuits. (3) Connect the inputs of the gate to the switches provided on the trainer or hook them up to the +5V supply (logic 1) or ground (logic 0) to give the proper sequence of binary. (4) Connect the LEDs to the sum and carry outputs, or hookup them to a LED with current limiting resistor. (5) Turn on the trainer/power project board. (6) Check the output of each circuit by giving the proper sequence of binary. (7) Prepare the truth table. Combinational Logic Circuits-Arithmetic Circuits [89] Observation: 1. 1’s complement method S.No. outputs Inputs Control-1 A3 A2 A1 A0 B3 B2 B 1 B 0 Sign bit S3 S2 S1 S0 Result: Verified the operations of 1’s compliment adder/subtractor circuit. Precautions: 1. Check all gates in the ICs before using them. 2. Check the power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-4.8 Object: Design, construct and verify the operations of 2’s complement adder/ subtraction circuits. Equipment/Components required: 1. Equipment: Power project board and Digital Multimeter. Experiments in Digital Electronics 2. [90] Components: ICs: Two 7483 (4-bit binary adder with fast carry), One 7408 (Quadruple 2-input AND gate), 7404 (Hex-inverter), Two7486.( Quadruple 2-input EX-OR gates). Diode: Five LEDs. Miscellaneous: Five Resistors � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: 2’s complement addition/subtraction circuit: The subtraction of the two binary numbers can be done by the following steps: (a) take the 2’s complement of the subtrahend. (b) add it to the minute. To find the 2’s complement of a number, first take its 1’s complement and then add 1 to it. Design a circuit that will use an IC 7483 to add the 4-bit numbers B3, B2, B1, and B0 to the four bit binary numbers A3, A2, A1, A0 and subtract B3, B2, B1, and B0 from A3, A2, A1, A0. Use the 2’s complement method for subtraction. To use the IC7483 4-bit full adder as a 2’s complement adder/subtractor, the following steps must be considered a. Leave the numbers B3, B2, B1, and B0 unaltered for an addition problem, but take the 2’s complement for a subtraction problem. The 2’s complement can be formed by taking the 1’s complement and adding 1. The 1’s complement can be formed by using Ex-OR gates as we did in the 1’s complement subtractor. 1 can be added to form the 2’s complement by writing the control signal directly to Cin1. b. If the problem is subtraction and if there is no overflow (Cout),indicate the answer is negative and take the 2’s complement of the result to obtain the true magnitude of the answer. As in the 1’s complement subtractuion circuit, the inverted output of Cout ANDed with the first control signal C1. A high AND gate indicates that a subtraction problem is being Combinational Logic Circuits-Arithmetic Circuits [91] performed and the answer is negative. This signal will be inverted to drive an LED in the active low mode. The 1’s complement can be formed by EX-ORing the results with the output of the AND gate. To add 1 to form the 2’s complement, another IC 7483 must be used. The output of the AND can be fed directly into Cin2 of 7483-2 to complete the 2’s complement process. The true magnitude outputs appear at S3,S2,S1, and S0 of 7483-2. c. If the problem is subtraction and if there is overflow (Cout1), do not take the 2’s complement of the result from 7483-1. The answer is already in true magnitude form and should not be altered by the following circuitary. Fig.4.8.1 shows the (a) function table and (b) logic diagram for 2’s complement adder/subtractor. When the control-1(first controlled inverter) input is ‘0’ we can use the diagram as an adder, or if it is ‘1’ it can use as a subtraction. Table 4.8.1 summarizes the techniques used to draw design implementation of 2’s complement adder/subtraction circuit with the help of the above mentioned points. Table 4.8.1: Function table for 2’s complement adder/subtraction circuit Control-1 Operation C1 7483 C out Control-2 7483 C in �1 C2 Cin � 2 Sign bit 0 = +ve 1 = -ve add 0 0 0 0 0 0 0 1 0 0 0 0 subtract 1 0 1 1 1 1 1 1 1 0 0 0 Simplified expression for above table: Cin �1 � C1.C out � C1Cout � C1 C2 � C1. C out � Cin � 2 Remark - Overflow(need one more bit No carry, answer will be -ve with 2’s complement. When carry, answer will be +ve, ignore carry [92] Experiments in Digital Electronics Control � 1 C1 B3 0=Addition 1=Subtraction B2 B0 B1 1 2 4 5 9 10 12 13 14 VCC 7486-1 A3 A2 A1 A 0 11 8 6 3 3 8 10 16 4 7 11 1 14 Cin1 2 1 1 2 08 3 7 5 VCC 7483-1 13 Cout 1 12 GND 15 2 S3 Control � 2 C2 2 1 4 9 12 GND S2 6 9 S1 S0 5 10 13 14 VCC 7486-2 7 GND 11 8 6 3 16 4 7 11 S3 S 2 S1 S0 GND 1 3 8 10 Cin2 14 Cout2 13 3 4 7483-2 LED on : Negative answer to subtraction 330 � True Magnitude outputs +5V Fig.4.8.1: Shows the logic diagram for 2’s complement adder/subtractor. Procedure: (1) Insert the ICs into the breadboard. Connect the power supply to the proper pin of the chip. (2) Construct the abovementioned logic circuits. (3) Connect the inputs of the gate to the switches provided on the trainer or hook them up to the +5V supply (logic 1) or ground (logic 0) to give the proper sequence of binary. Combinational Logic Circuits-Arithmetic Circuits [93] (4) Connect the LEDs to the sum and carry outputs, or connect them to a LED with a current limiting resistor. (5) Turn on the trainer/power project board. (6) Check the output of each circuit by giving the proper sequence of binary. (7) Prepare the truth table. Observation: 2’s complement method: S.No. Inputs Control-1 A3 A2 A1 outputs A0 B3 B 2 B1 B0 Sign bit S 3 S2 S1 Result: Verified the operations of the 2’s compliment adder/subtractor circuit. Precautions: 1. Check all gates in the ICs before using them. 2. Check power supplies of the power project board. 3. Do not leave an input floating. S0 [94] Experiments in Digital Electronics 5. Combinational Logic Circuits: Code Converters EXPERIMENT-5.1 Object: To study and verify the Binary-to-BCD code converter circuit and vice versa. Equipment/Components required: 1. Equipment: Power Project board and Digital Multimeter. 2. Components: ICs: Three 7408 (Quadruple 2-input AND gates), Two 7432 (Quadruple 2-input OR gates), One 7404 (Hex inverter), and one 74184 (BCD-tobinary converter). Diode: Five LEDs Miscellaneous: Five Resistors � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: Since a binary number of different codes are used in different processes. It is, sometimes, necessary to convert the data from one code to another. Such a device is known as a code converter. Binary codes: Computers work with binary numbers. In most present-day electronic digital systems, we can use signals as two discrete values, 0 & 1 and it is said to be binary. A binary digit, called a bit, has two values: 0 and 1. In this, each coefficient is multiplied by 2n, where n is the position of the bit. Binary codes are a group of bits which consist of discrete elements of information. In the binary number, the binary number has a string of zeros and ones. Since it has only two digits, the base is 2. An n-bit binary code is a group of n bits that assumes up to 2n distinct combinations of 1’s and 0’s, with each combination representing one element of the set that is being coded. A set of four elements can be coded with two-bits, with each element assigned one of the following bit combinations: 00, 01, 10, and 11. A three bit code is used for a set of eight elements and a four-bit code set is used for a set of sixteen elements. In the binary system, positive and negative numbers may be represented as (i) signed magnitude, and (ii) 1’s complement and 2’s complement. In order to represent the 16 decimal digits, 0 through 15, in binary code, it is necessary to use at least 4-bit binary numbers (0 = 0000 and 15 = 1111). Since there [95] Combinational Logic Circuits: Code Converters are sixteen combinations of four binary digits, it is possible to form a very large number of distinct codes. a. BCD code: A weighted 4-bit binary code is one in which each number carries a certain weight. A string of 4-bits is known as a nibble. Binary-Coded Decimal (BCD) means that each decimal digit is represented by a nibble (binary code of 4-digits). Many BCD codes have been proposed, e.g., 8421, 2421, and 5211. Out of these, the 8421 code is the most predominant BCD code. The destination 8421 indicates the weights of the 4-bits (8, 4, 2, and 1 respectively, starting from the left most bit). In BCD, only 10 of the 16 combinations are used. The six combinations that are not used: 1010, 1011, 1100, 1101, 1110, and 1111 are invalid codes in the BCD code. The BCD code is not self-complementing. The Binary-Coded Decimal (BCD), which is very important for visual display communication between a computer and a human being. But BCD is very difficult to deal with arithmetically. Algorithms, or procedures, have been developed for the conversion of BCD to binary by computer programme (software), so that the computer will be able to perform all arithmetic operations in binary. Yet another way to convert BCD to binary, the hardware approach, is with MSI integrated circuits. Additional circuitry is involved, but it is much faster to convert using hardware rather than software. The BCD code is used in pocket calculators, electronic counters, digital voltmeters, digital clocks, etc. Early versions of computers also used the BCD code. However, the BCD code was discarded for computers because it is slow and more complicated than binary. Often, it is important to convert a coded number into another form that is more usable by a computer or digital system. The main advantage of the BCD code is the relative ease of converting to and from decimal. Only the four bit code groups for the decimal digits 0 through 9 need to be remembered. This ease of conversion is especially important from a hardware standpoint, because in a digital system, it is the logic circuits that perform conversions to and from decimal. 1. Binary-to-BCD conversion: Any binary number can be converted into BCD by the following steps: 1. To form a BCD number from a binary, simply convert each decimal digit to its four-bit binary code. A binary code takes the complete decimal number and represents it in binary. 2. In a 4-bit binary the maximum binary is 1111. But in BCD, decimal 0 through 9 are valid numbers (single digit decimal) - binary code and BCD code are equivalent, and 10 through 15 are invalid numbers (two digit decimal) can be represented into BCD by converting each digit into 4-bit binary. [96] Experiments in Digital Electronics Table 5.1.1: Binary to BCD code - converter D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B in ary code C B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 B4 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 B C D code B2 B1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 B3 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 To draw the logic diagram for the binary to BCD code converter, each of the output functions are simplified by using k-maps. B4 � DC � DB � D (C � B ) B3 � DC B B2 � DC � CB B1 � D A � DC B B0 � A The logic diagram for the code converter is shown in the Fig.5.1.1. A B 04 3 4 D (Binary) C 04 1 2 1 2 32 1 2 08 3 B4 08 4 3 5 08 6 B3 9 10 08 8 4 5 12 13 08 1 2 08 5 08 6 (BCD) B2 11 3 9 4 32 10 6 9 10 08 32 8 B1 8 B0 Fig.5.1.1: Logic diagram of binary to BCD code converter Combinational Logic Circuits: Code Converters [97] 2. BCD-to-Binary conversion: Any BCD number can be converted into binary. Simply convert each 4-bit BCD number to decimal and then to binary. The truth table of the 5 bit BCD-to-binary converter is given in table 5.1.2. Table 5.1.2: BCD to Binary code - converter BCD Code (Inputs) Binary Code (Output) B4 B3 B2 B1 B0 A B C D E 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 To draw the logic diagram for code converter, each of the output functions are simplified by using k-maps. The logic diagram for the BCD-to-binary converter is shown in the Fig.5.1.2. A � B4 B3 � B4 B2 B0 B � B 4 B3 � B4 B 3 B 2 � B4 B 3 B1 C � B 4 B2 � B2 B1 � B4 B 2 B1 D � B 4 B1 � B4 B 1 E � B0 The IC 74184 is used for the BCD-to-binary converter, Fig. 5.1.2.(b) gives the block diagram of 74184. When BCD inputes are applied at terminals (A through E), and binary output appears at terminals (Y1 through Y8) when the circuit is enabled (G = 0). [98] Experiments in Digital Electronics B4 B3 B2 B1 B0 1 2 08 1 4 5 08 08 08 9 10 08 1 2 4 5 08 4 5 8 12 08 32 6 B1 6 08 08 13 B 11 9 8 12 32 8 12 13 32 11 C 11 3 32 08 A 32 13 3 08 08 3 8 5 3 6 4 5 32 11 08 1 2 08 10 9 10 9 4 1 2 2 6 10 12 13 3 D 6 E (a) (b) Fig.5.1.2: (a) logic diagram for the BCD to binary converter (b) Block diagram of the 74184 Procedure: (1) Mount the ICs on the breadboard and make the connections shown above the logic circuit. (2) Connect the power supply to the proper pin of the chip. (3) Connect the inputs of the gate to the switches provided on the trainer or hook them up to the +5V supply (logic 1) or ground (logic 0) to give the proper sequence of binary. (4) Connect the LEDs to the outputs, or hookup them up to a LED with a current limiting resistor. (5) Turn on the trainer/power project board. (6) Check the output of each circuit by giving the proper sequence of binary. (7) Prepare the truth table. Combinational Logic Circuits: Code Converters [99] Observation Table: 1. Truth table for binary- to- BCD code converter. S.No. D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2. Binary code C B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 B4 B3 BCD code B2 B1 B0 Truth table for BCD-to- binary converter. B4 B3 BCD code (Inputs) B2 B1 B0 E Binary code(Outputs) D C B A [100] Experiments in Digital Electronics Result: Verified the operations of binary-to-BCD code converter and vice-versa. Precautions: 1. Check all gates in ICs before making them used in the circuits. 2. Check the power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-5.2 Object: To study and verify the Binary-to-Gray code converter and vice versa. Equipment/Components required: 1. Equipment: Power Project board and Digital Multimeter. 2. Components: ICs: Two 7486 (Quadruple 2-input EX-OR gates). Diode: Four LEDs Miscellaneous: One Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: a. The gray code: It is an unweighted code. The bit positions do not have any specific weights assigned to them. However, the most important characteristics of this code is that only a single bit change occurs when going from one code number to next. In binary systems all the 4 bits change when we go from 0111 to 1000. The single bit change property is important in some applications, e.g., shaft position encoders. In these applications the chances of error increase if more than one bit change occurs. The gray code belongs to a class of codes called the minimum change code. Successive coded characters never differ by more than one-bit. Because of this, the gray code is not suitable for arithmetic operations, but finds application in input/ output devices, some types of ADC, and the designation of rows and columns in a Karnaugh map. In the gray code, there is only one bit change in going from one number to the next. Only one bit in the numerical representation changes between the successive numbers. This shows the advantage of the gray code over the binary number sequence. Hence, gray code is also referred to as ‘reflected code’. Any binary number can be converted into an equivalent gray code by following these steps: 1. The MSB of the gray code is the same as the MSB of the binary number; 2. The second bit next to the MSB of the gray code equals the EX-OR of the MSB and the second bit of the number; it will be 0 if there is the same binary bit or it will be 1 for different bits; 3. The third bit for gray code equals the Ex-OR of the second and third bits of the binary number, and similarly, all the next lower order bits follow the same mechanism. The following table shows the truth table for binary to gray code conversion. Combinational Logic Circuits: Code Converters [101] Table 5.2.1: Binary to gray code converter A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Binary code (inputs) B C 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gray c ode (outputs) G2 G1 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0 G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 To draw the logic diagram for code converter, each of the output functions are simplified by using k-maps. G3 = A G2 = A � B G1 = B � C G0 = C � D The logic diagram of binary to gray code converter is shown in the Fig.5.2.1. Binary code (Input) A B C D G3 1 2 86 3 G2 4 5 86 6 G1 9 10 86 8 G0 Fig.5.2.1: Logic diagram for the binary to gray code converter [102] Experiments in Digital Electronics The gray to binary code converter contain four inputs and four outputs: D, C, B, and A. Any gray code can be converted into equivalent binary number by following these steps: 1. The MSB of the binary number code is the same as the MSB of the gray code; 2. The second bit next to the MSB of the binary number equals the Ex-OR of the MSB and the second bit of the gray code; it will be 0 if there is same binary bit or it will be 1 for different bits; 3. The third bit for a binary number equals the Ex-OR of the second bit of the binary number and the third bit of the gray code, and similarly, all the next lower order bits follow the same mechanism. The following table shows the truth table for gray to binary code conversion. Table 5.2.2: Gray-to-Binary Converter G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Gray code (inputs) G2 G1 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Binary (outputs) C B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 To draw the logic diagram for code converter, each of the output functions are simplified by using k-maps. D � C � G0 C � B � G1 B � G3 � G2 A � G3 The logic diagram for the code converter is shown in the Fig.5.2.2. Combinational Logic Circuits: Code Converters [103] Graycode (input) G3 G2 G1 G0 A 1 2 86 4 5 86 3 B Binary (output) 6 C 9 10 86 8 D Fig.5.2.2: Logic diagram for the gray to binary. Procedure: (1) Insert the ICs into the trainer/breadboard. Connect the power supply to the proper pin of the chip. (2) Construct the abovementioned logic circuits. (3) Connect the inputs of the gate to the switches provided on the trainer or hook them up to the +5V supply (logic 1) or ground (logic 0) to give the proper sequence of binary. (4) Connect the LEDs to the outputs, or hookup them up to a LED with the proper values and voltage current limiting resistor. (5) Turn on the trainer/power project board. (6) Check the output of each circuit by giving the proper sequence of binary. (7) Prepare the truth table. Observation Table: 1. Truth table for binary–to- gray converter. S. N o . 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B in a r y c o d e ( i n p u t s) C B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G3 G r a y co d e (o u tpu ts ) G2 G1 G0 [104] Experiments in Digital Electronics 2. Truth table for gray–to-binary converter. S.N o. G3 Gray code (inputs) G2 G1 G0 D BC D code (outputs) C B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Result: Verified the operations of the Binary-to-gray code converter and vice-versa. Precautions: 1. Check all gates in the ICs before using them. 2. Check power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-5.3 Object: To study and verify the BCD-to-EX-3 code converter. Equipment/Components required: 1. Equipment: Power Project board and Digital Multimeter. 2. Components: ICs: Two 7408 (Quadruple 2-input AND gates), One 7432 (Quadruple 2-input OR gates), One 7404 (Hex inverter). Diode: Four LEDs. Miscellaneous: Four Resistors � 330 � � 0.25watt, Single core wire, Cutter and stripper Combinational Logic Circuits: Code Converters [105] Brief theory: a. BCD code: {See page number 95} b. The Excess-3 code: A decimal code that has been used on some old computers is the EX-3 code. This is an unweighted code, i.e., no weights can be assigned to any of the four digit positions. This code assignment is obtained from the corresponding value of the 4 bit binary code after adding 3 to the given decimal digit and then converting the result to four bit binary. Out of the possible 16 code combinations, only 10 are used in the EX-3 code. The remaining 6, i.e., 0000, 0001, 0010, 1101, 1110 and 1111 are invalid in this code. Ex-3 code is also known as the self-complementary code. The Selfcomplementary property of this code helps considerably in performing subtraction operations in digital systems. The truth table for BCD to Ex-3 code is shown in the following tableTable 5.3.1 : BCD to EX-3 code converter Decimal 0 1 2 3 4 5 6 7 8 9 A 0 0 0 0 0 0 0 0 1 1 BCD code (inputs) B C 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 D 0 1 0 1 0 1 0 1 0 1 E3 0 0 0 0 0 1 1 1 1 1 EX-3 code (outputs) E2 E1 E0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 To draw the logic diagram for code converter, each of the output functions are simplified by using k-maps. E3 = D+ B �C + D � E2 = B � C + D � + B C D E1 = C e D E0 = D The logic diagram for the code converter is shown in the Fig.5.3.1. [106] Experiments in Digital Electronics BCD code (Input) D C B A 5 3 1 6 4 2 1 2 32 3 1 08 3 4 5 2 4 5 08 9 10 32 6 9 10 8 12 08 13 1 2 08 4 5 08 6 E3 8 12 13 08 32 11 32 11 E2 Ex-3 code (Output) 3 1 6 32 3 E1 2 E0 Fig.5.3.1: logic diagram for the BCD to EX-3 code converter Procedure: (1) Insert the ICs into the trainer/breadboard. Connect the power supply to the proper pin of the chip. (2) Construct the abovementioned logic circuits. (3) Connect the inputs of the gate to the switches provided on the trainer or hook them up to the +5V supply (logic 1) or ground (logic 0) to give the proper sequence of binary. (4) Connect the LEDs to the outputs, or hook them up to a LED with a current limiting resistor. (5) Turn on the trainer/power project board. (6) Check the output of each circuit by giving the proper sequence of binary. (7) Prepare the truth table. Combinational Logic Circuits: Code Converters [107] Observation: Truth table for BCD to EX-3 converter S.No. D BCD code (inputs) C B A E3 EX-3 code (outputs) E2 E1 E0 0 1 2 3 4 5 6 7 8 9 Result: Verified the operations of the BCD-to-EX3 code. Precautions: 1. Check all gates in the ICs before using them. 2. Check power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-5.4 Object: To study the use of comparator and verify its operation. Equipment/Components required: 1. Equipment: Power project board and Digital Multimeter. 2. Components: ICs: One 7485 (4-bit comparator),one 7486, Two 7408, One 7432 and One 7404. Diode: Three LEDs Miscellaneous: Three Resistors � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: A magnitude comparator is a combinational circuit that compare the relative magnitude of two binary numbers, A and B. The result of this comparison is specified by three binary variables that indicate whether A>B, A=B, or A<B. Often in the evaluation of digital information, it is important to compare two binary strings (binary words) to determine if they are exactly equal. This comparison process is performed by a digital comparator. The basic digital comparator evaluates two binary strings bit by bit and outputs a high '1' if they are exactly equal. An Ex-NOR gate is the easiest way to compare the equality of bits. [108] Experiments in Digital Electronics In order to compare binary numbers containing more than just 2 bits, we need additional Ex-NORs, and the output of all of them must be high '1'. To design a comparator to evaluate two n-bit numbers, we need ‘n’ Ex-NORs. The logic used to determine the comparator of two four bits, if A>B starting from MSB, can be expressed in the set of statements as follows: 1. If A3 =1 and B3 =0, then A>B. Or 2. If A3 =B3 and, if A2 =1 and B2 = 0, then A>B. Or 3. If A3 =B3, A2 =B2, and A1 = 1, B1 =0, then A>B. Or 4. If A3 =B3, A2 =B2, and A1 = B1, A0 = 1, B0 =0, then A>B. From above statements, the logic expression for A>B can be written as for active high output. A � B � A3 B3 � (A3 �B3)A2 B2 � (A3 �B3)(A2 �B2)A1B1 � (A3 �B3)(A2 �B2)(A1 �B1)A0 B0 Similarly for B > A and B=A: B � A � A3B3 � (A3 �B3)A2B2 � (A3 �B3)(A2 �B2)A1B1 � (A3 �B3)(A2 �B2)(A1 �B1)A0B0 A � B � A3 � B3 ) � ( A2 � B2 )1 � ( A1 � B1 ) � ( A0 � B0 ) The logic diagram for 2-bit comparator with active low output is shown in the Fig.5.4.1. BCD code (Input) B1 B0 A1 A0 7 5 3 1 8 6 4 2 1 2 08 4 5 08 1 2 86 4 86 3 6 9 10 08 1 2 32 4 5 32 3 A>B 8 3 6 A=B 6 5 1 2 08 4 5 08 3 12 13 6 08 11 9 10 32 8 A<B Fig.5.4.1: logic diagram for the 2-bit comparator for active low output. [109] Combinational Logic Circuits: Code Converters Integrated Circuit Comparator: Integrated-Circuit magnitude comparators are available in both the TTL and CMOS families. A magnitude comparator not only determines, if A equals B, but also if A greater than or less than B. The IC 7485 is a MSI series, 16-pin DIL package, TTL 4-bit magnitude comparator. The pin configuration and function table for the IC 7485 are given in Fig.5.4.2 (a). It can be expanded to any number of bits. The cascading inputs are used for expansion to a system capable of comparison. To set up a circuit capable to compare two 8-bit words, two 7485s are required. The comparator outputs of the lower-order (least significant) comparator are connected to the expansion inputs of high-order comparator. That way, the comparators act together, comparing two entire 8-bit words and outputting the result from the high order comparator outputs. The comparator is used to compare more than 4-bit binary words by cascading IC7485. The IC7485 is used to compare two 4-bit binary numbers. To compare 8-bit numbers, we need to use two 7485 ICs. The logic diagram of an 8-bit comparator is shown in Fig. 5.4.2 (b). Table 5.4.2 shows the function table for cascading IC7485. (a) (b) Fig. 5.4.2: IC 7485: (a) pin diagram (b) 8-bit comparator [110] Experiments in Digital Electronics Table 5.4.1: The function table for IC 7485 Comparing inputs Cascading inputs Comparator output A 2B2 A1B1 A0B0 A>B A<B A=B A>B A<B A=B x x x x x x 1 0 0 x x x x x x 0 1 0 A2 >B2 x x x x x 1 0 0 A2 <B2 x x x x x 0 1 0 A2 = B2 A1 > B1 x x x x 1 0 0 A2 = B2 A1 < B1 x x x x 0 1 0 A2 = B2 A1 = B1 A 0 > B0 x x x 1 0 0 A2 = B2 A1 = B1 A 0 < B0 x x x 0 1 0 A2 = B2 A1 = B1 A0 =B0 1 0 0 1 0 0 A2 = B2 A1 = B1 A0 =B0 0 1 0 0 1 0 A2 = B2 A1 = B1 A0 =B0 0 0 1 0 0 1 1 = high 0 = low x = don’t care Lower order cascading inputs connection: A>B, and A<B = logic ‘0’; A = B, equal to logic ’1’ A 3B3 A 3>B3 A 3<B3 A 3=B3 A 3=B3 A 3=B3 A 3=B3 A 3=B3 A 3=B3 A 3=B3 A 3=B3 A 3=B3 Procedure: (1) Insert IC 7485 on the logic trainer board. (2) Connect cascading inputs A>B, A<B together to the logic ‘0’ or logic’1’but, cascading input A = B must be to logic’1’. (3) For higher order comparison, output of the lower comparator is connected to the cascading inputs of higher order comparator. (4) Give inputs A and B through binary switches and observe LEDs at the output. (5) Make a truth table for different outputs. Observation Table: S.No. Comparator inputs A3 A2 A1 A0 Comparator inputs B3 B2 B1 B0 Outputs A>B A<B 1 2 3 4 5 6 7 8 9 10 11 Result: Verified the operations of the magnitude comparator. A=B Combinational Logic Circuits: Code Converters [111] Precautions: 1. Check the gate to be used in the logic circuit in ICs before connecting. 2. Check the power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-5.5 Object: Design, construct, and test a circuit that generates and checks an even/oddparity bit from message bits. Use XOR gates. Equipment/Components required: 1. Equipment: Power Project board and Digital Multimeter. 2. Components: ICs: One 7486 (Quadruple 2-input EX-OR gates), 74S280. (9-bit odd/ even parity-generator). Diode: Two LED Miscellaneous: Two Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: 1. Parity bit: When data bits are transferred from one circuit to another, an extra bit is sometimes added to ensure that the data is transferred correctly. The extra bit is called a parity bit. The system can work on an even parity or odd parity system. If the system is even parity, then the parity bit is chosen so that the total number of 1s in the word, including the parity bit, is even. One method for error detection is to use 7 bits for data and the 8th (most significant) bit for parity. The parity bit can be 1 or 0.To make an odd parity, the parity bit is set to 1 or 0. If the word has an odd number of 1s, the parity bit is set to 0. If the word has an even number of 1’s, the parity bit is set to 1 so as to make the total number of 1’s odd. The following table shows an example of a parity bit. Parity Data 1100111 1101011 1000010 0000011 Total number of 1s 5 5 2 2 Even 1 1 0 0 odd 0 0 1 1 At the receiving point, the parity is checked to see if it is odd. If it is even, an error has been committed and the data is required to be transmitted again. [112] Experiments in Digital Electronics 2. Even parity generator: A circuit that can determine whether the parity bit should be 1 or 0 is called a parity generator. Ex-OR gates can be used to construct a parity generator. Fig.5.5.1 shows Ex-OR gates being used as an even-parity generator. Each Ex-OR gate checks for unlike inputs. Unlike inputs into the last Ex-OR means that an odd number of 1’s have been encountered. The 1 output would be used as a parity bit, making the total number of 1s even. 3. Even/odd-parity generator: By adding an extra Ex-OR gate, the circuit can be made more versatile. A 1 on the control input inverts the output and changes the circuit into an odd-parity generator. A parity generator circuit generates the parity bit in the transmitter. For this purpose, EX-OR function is very useful in system where there is a requirement for error detection and correction codes. Consider a 3-bit message being transmitted tighter with an even/ odd parity bit. Table 5.5.1 shows the truth table for the even/odd-parity generator. Table 5.5.1: Even/Odd-Parity-Generator Three-Bit Message Y 0 0 1 1 0 0 1 1 X 0 0 0 0 1 1 1 1 Parity Bit P(even) P(odd) 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 Z 0 1 0 1 0 1 0 1 For the three-variable exclusive-OR function, the parity bit can be expressed as; P � X �Y � Z The logic diagram for the even parity generator is shown in Fig.5.5.1 X Y 1 2 86 4 3 5 86 Parity bit 6 Z Fig.5.5.1: 3-bit even parity generator Combinational Logic Circuits: Code Converters [113] 4. Parity checker: The parity checker circuit is used to check the parity in the receiver. Suppose a computer has sent a group of data bits along with an even-parity bit to a printer. The printer checks to see that the total number of 1’s received is even. A circuit that can determine whether the total number of 1s is even or odd is called a parity checker. Fig 5.5.2 shows a four-bit even parity checker. The table 5.5.2, shows the truth table for even/odd parity checkers. Here, the three bits in the message are combined with the parity bit and, after that; these bits are applied to the parity checker circuit to check for possible errors in the transmission. As the information was transmitted with even parity, the fourth bit must have an odd/ even number of 1’s. Table 5.5.2: Even-Parity-Checker Four-Bits received X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Y 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Z 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Parity Error Check C(e ven) C(odd) 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 P 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 From the above table parity checker can be expressed as; C � X �Y � Z � P The figure given below shows the logic diagram for the parity checker; X Y Z P 1 2 86 3 9 10 4 5 86 86 8 6 Fig. 5.5.2 : 4-bit even parity checker [114] Experiments in Digital Electronics 5. 9-bit parity generator/checker: The 74S280 is a medium-scale integrated circuit that functions as a 9-bit parity generator/checker. The pinout and truth table are shown in Fig 5.5.3. If the number of inputs (A through I) that are high is even, then the � ODD � EVEN output goes high and the output goes low (First line of truth table). To use the IC as an even-parity generator, use the � ODD output to generate the parity bit. Outputs Number of Inputs (A-I) that are HIGH 0, 2, 4, 6, 8 1, 3 ,5, 7, 9 � EVEN � ODD 1 0 0 1 (a) (b) Fig 5.5.3 74S280 9-bit generator/checker (a) truth table, and (b) pinout diagram. Procedure: (1) Insert ICs on the logic trainer board. Connect the power supply to the proper pin of the chip. (2) Construct each circuit on the breadboard. (3) Connect the LEDs to the output with the proper value of the current limiting resistor. Combinational Logic Circuits: Code Converters [115] (4) Connect the inputs of the gate to the switch provided on the trainer/ board or hook them up to the +5V supply (logic 1) or ground (logic 0). (5) Vary these inputs and observe LED outputs. (6) Prepare truth table. Observation: 1. Truth table for Even/Odd-Parity-Generator X 0 0 0 0 1 1 1 1 2. Three-Bit Message Y 0 0 1 1 0 0 1 1 Parity Bit P(even) P(odd) Z 0 1 0 1 0 1 0 1 Truth table for Even/Odd-Parity-Checker F o ur-B its received X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Y 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Z 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 P 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 P arity Erro r C heck C(even ) C( o dd ) Result: Verified the parity generator/checker output. Precautions: 1. Check each gate on a 7486 IC by determining its truth table. 2. Check power supplies of the power project board. 3. Do not leave an input floating. [116] Experiments in Digital Electronics 6. Combinational Logic Circuits-Data Processing Circuits EXPERIMENT-6.1 Object: Design a combinational circuit with four inputs (A, B, C, and D) and one output (Y). The output is to be equal to 1 when A=1 provided that B=0, or when B=1 provided that either C or D is also equal to 1.Otherwise, the output is to be equal to zero. Equipment/Components required: 1. Equipment: Power Project board and digital Multimeter. 2. Components: ICs: One 7408 (Quadruple 2-input AND gates), One 7432 (Quadruple 2-input OR gates), One 7404 (Hex inverter), Two 7400 (Quadruple 2input NAND gates), and Three 7402 (Quadruple 2-input NOR gates). Diode: One LED. Miscellaneous: One Resistor 330 � - 0.25watt, Single core wires, wire cutter and stripper. Brief theory: A combinational circuit consists of input variables, logic gates, and output variables. It consists of logic gates whose outputs at any time are determined by only the present combination of inputs. Table 6.1.1: Truth table for given combinational circuit Inputs Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Y 0 1 0 0 0 1 1 1 0 1 1 1 0 1 1 1 Combinational Logic Circuits-Data Processing Circuits [117] As we know, that combinational circuits are used to performs an operation that can be specified logically by a set of Boolean functions. In this experiment; we designed and implemented a combinational circuit with four inputs and one output. The output is equal to 1, when input A=1, provided that input B = 0, or when B = 1, provided that either C or D is also equal to logic-1. Otherwise, the output will be equal to zero. Now Obtain the truth table for the above mentioned logic as shown in Table 6.1.1. Then simplify output using k-map. The simplified sum-of-product expression for output is equal to: Y = B A + CB + D B The logic diagram implementation of this expression using basic gates is shown in Fig. 6.1.1 (a). It can also be implemented using universal gates as shown in Fig.6.1.2 or 6.1.3 (a) Using two input basic gate: Y � ( B A � CB) � DB D C B A 1 2 3 08 1 4 5 08 9 10 08 6 4 32 3 2 5 32 8 Fig. 6.1.1: Using 2-input basic gate. (b) Using two-input NAND-NAND gates. � � � � � � Y � BA � CB � DB � BA � CB .DB � BA.CB .DB 6 Y [118] Experiments in Digital Electronics D C B A 1 2 00 3 4 6 00 5 4 00 8 6 00 5 12 9 10 00 11 1 2 13 3 00 9 10 00 8 Fig. 6.1.2: Using 2-input NAND-NAND gate (c) Using two-input NOR-NOR gates. Y � ( B A � CB ) � DB � ( B A.CB) � ( D � B) � ( B � A).(C � B) � ( D � B) � ( B � A) � (C � B) � ( D � B) � {( B � A) � (C � B)} � ( D � B) D C 02 02 B A 02 02 2 3 02 5 6 02 1 8 9 4 02 10 11 02 13 2 3 12 02 1 9 02 10 Y 8 5 6 02 4 Fig. 6.1.3: Using two-input NOR-NOR gates. Procedure: (1) Insert ICs on the logic trainer board. Connect the power supply to the proper pin of the chip. (2) Construct the above logic circuit on the breadboard. (3) Connect the LEDs to the output with a current limiting resistor. (4) Connect the inputs of the gate to the switch provided on the trainer/ board or hook them up to the +5V supply (logic 1) or ground (logic 0) as required. (5) Vary these inputs from 0000 to 1111 and observe LED outputs. (6) Prepare the truth table. Combinational Logic Circuits-Data Processing Circuits [119] Observation Table: Decimal Inp uts D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 O utput Y Result: Verified the output of the abovementioned combinational circuit. Precautions: 1. Check each gate in ICs before designing a logic circuit. 2. Check the power supply of the power project board. 3. Do not leave an input floating. EXPERIMENT-6.2 Object: To study and verify the workings of the multiplexer and its operation as a logic function generator. Equipment/Components required: 1. Equipment: Power Project board and digital Multimeter. 2. Components: ICs: One 7432, One 7404, One 7486, One 74150 (16X1 MUX), One 74151 (8X1 MUX), One 74153 (4X1 MUX), and One 74157 (2X1 MUX). Diode: One LED Miscellaneous: One Resistor � 330 � � 0.25watt, Single core wire, wire cutter and stripper. [120] Experiments in Digital Electronics Brief theory: A multiplexer (MUX) is a combination circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2ndata input lines and n- selection lines, whose bit combinations determine which data input is selected. A MUX is also called a data selector, since it selects one of many inputs and steers the binary information to the output line. The enable input (EN) in a MUX, must be active for normal operation. Therefore, MUX is a very convenient logic circuit used in combinational logic circuits. Digital multiplexers are available in ICs. Some of these are given in Table 6.2.1. Table 6.2.1: TTL and CMOS MUXs IC number 74150 74151A 74152 74153 74157 74158 Description 16 -data inputs MUX with 4 data select inputs lines. Output is complemented. 8 -data inputs MUX with 3 data select inputs lines. Data output and its complement are available at the output. 8- data inputs MUX with 3 data select input lines. Output is inverted input. Dual separate 4-data inputs MUXs with 2- data select inputs lines. Output is the same as input. Quad separate 2-data inputs MUXs with 1-data select input lines on a single chip. They share a common data select and a common enable. Output same as input. Quad separate 2-data inputs MUXs with 1-data select input lines on a single chip. Output is complemented. One data select line. Boolean function implementation: As the name indicates, MUX is many into one, which means that this circuit is associated with many inputs and a single output. Here, the minterms of a function are generated by the circuit associated with the selection inputs. MUX has n- selection inputs and 2n- data inputs, one for each minterm. For implementing a Boolean function of n- variables with a MUX that has (n-1)-selection inputs. The first (n-1) variables of the function are connected to the Combinational Logic Circuits-Data Processing Circuits [121] selection inputs and the remaining single variable are used for the data inputs. If the single variable is denoted by ‘C’, each data input of the MUX will be c, c ,1, or 0 .The procedure for using it to generate a given minterm logic expression is as under: 1. The select lines are used as data input lines. 2. Input lines corresponding to given minterms are connected to logic 1 level. 3. The remaining input lines are connected to logic-0 level (i.e., ground). Let us consider the Boolean function of three variables: Y ( A, B, C ) � A B C � ABC � ABC � ABC � � m (1,2,6,7) This function can be implemented with: 1. A 16-to-1line (16X1) MUX: The IC 74150 is a 16-to-1line (16X1) MUX that has active high 16-data inputs and 4-selection input lines and one active low output. But the above function has only three selection inputs lines. One selection line can be eliminated by either giving logic-0 or logic-1. In this chip, we are eliminating selection input D, which is MSB. If D = logic 0, the first eight data inputs are enabled, or if it is logic-1, last eight data inputs are enabled. Finally, the 16X1 MUX IC can work as 8X1 MUX. Fig.6.2.1 shows the pin diagram, logic diagram, function table, and block diagram for the above function using IC-74150. (a) [122] Experiments in Digital Electronics D X 0 Control Inputs C B A X X X 0 0 0 Enable E 1 0 Output Y 1 D0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 D1 D2 D3 0 0 1 1 0 0 0 1 0 0 D4 D5 0 1 1 0 0 D6 0 1 1 1 0 D7 1 0 0 0 0 D8 1 0 0 1 0 D9 1 0 1 0 0 D10 1 1 1 0 1 1 1 0 0 1 0 1 0 0 0 D11 D12 D13 1 1 1 1 1 1 0 1 0 0 D14 D15 (b) logic diagram (c) function table D0 D1 D2 D3 D4 D5 D6 D7 D8 Y=∑m(1,2,6,7) D9 D10 D11 D12 D13 D14 D15 (5V ) + VCC Enable (d) Fig.6.2.1: IC 74150 (a) Pin diagram (b) Logic diagram (c) Function table Block diagram of given Boolean function. (d) Combinational Logic Circuits-Data Processing Circuits [123] 2. A 8X1 MUX: IC 74151A is an 8-to-1 line (8X1 MUX) that has active high 8-data inputs and 3-selection input lines and two outputs, one active low and other active high output. As per the above function, it connects the data input lines (1, 2, 6, and 7) to logic-1 and the remaining data input lines (0, 3, 4, and 5) to logic-0. Connect A, B, C to select lines. Connect LED at the output terminal. Fig.6.2.2 shows the pin diagram, logic diagram, function table, and block diagram for the above function using IC-74151. (a) (b) (c) Enable E 0 1 1 1 1 1 1 1 1 Control Inputs C B A X X X 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Output Y 0 D0 D1 D2 D3 D4 D5 D6 D7 [124] Experiments in Digital Electronics D0 D1 D2 D3 (d) D4 D5 D6 D7 5 Y 6 Y Y� Outputs m 1,2,6,7 5V � VCC Enable / Strobe Fig.6.2.2 : IC 74151 (a) Pin diagram (b) Logic diagram (c) Function table (d) Block diagram of given Boolean function. 3. A 4X1 MUX: IC 74153 is a dual 4-to-1 line (4X1 MUX) that has active high 4-data inputs and 2-selection input lines and one active high output. For implementing any Boolean function of n-variables with a MUX with (n-1) selection inputs and (2n-1) data inputs, the following steps are used: (i) Firstly, the Boolean function is listed in a truth table. (ii) The first (n-1) variables in the table are applied to the selection inputs of the MUX. (iii) For each combination of selection variables, evaluate the output as a function of the last variable. But the above function has three selection inputs; any one selection input can be shifted to data inputs of the 4X1 MUX as shown in Table 6.2.2. Here the C and B are applied to the selection lines in that order; B is connected to the LSB input and C to the MSB input. The values for the data input lines are determined from Table 6.2.2. Fig.6.2.3 shows the pin diagram, logic diagram, function table and block diagram for the above function using IC-74153. Combinational Logic Circuits-Data Processing Circuits [125] Table 6.2.2 : three control lines function using two control lines. Data input D0 D1 D2 D3 Inputs 0utput C 0 0 B 0 0 A 0 1 Y 0 1 A 0 0 1 1 0 1 1 0 A 1 1 0 0 0 1 0 0 0 1 1 1 1 0 1 1 1 1 Comments When CB = 00 (D0 ), D0 = A, because Y = 0 when A = 0 and Y = 1 when A = 1.This requires that variable ‘A’ be applied to data input D0. When CB = 01 (D1), D1= A , because Y = 1 when A = 0 and Y = 0 when A = 1.This requires that variable A be applied to data input D1. When CB = 10 (D2), D2 = 0, because Y = 0 when A = 0 and Y = 0 when A = 1.This requires that logic ‘0’ be applied to data input D2 . When CB = 11 (D3), D3 = 1, because Y = 1 when A = 0 and Y = 1 when A = 1.This requires that logic ‘1’ be applied to data input D3 . (a) (b) (c) [126] Experiments in Digital Electronics D0 A (LSB) D1 D2 Logic -o D3 Logic -I 7 +VCC (5V ) Outputs (Enable)EN (d) (MSB) Fig.6.2.3: IC 74153 (a) Pin diagram (b) Logic diagram (c) Function table (d) Block diagram of given Boolean function. 4. Dual 4X1 MUX and a two-input OR gate. The IC 74153 is dual 4-to-1 line (4X1 MUX) that has active high 4-data inputs and 2-selection input lines, one active high output, and an active high enable (strobe) input. An 8X1 MUX can be implemented with two 4X1 MUXs with enabled inputs and a 2-input OR gate. Using enable input as one of the select input of MUXs, generally takes enable as MSB i.e., C selection input. The C (MSB) input determines which multiplexer is enabled. The enable input of upper MUX is connected to C and the lower MUX to C. If C = 0, the enable input in upper MUX is logic-1, or lower MUX is logic-0, which enables the upper MUX and disable the lower MUX. The select inputs A, B, and C (when C = 0) determine which of the data inputs D0 to D7 will be steered to the output. When C=1, the bottom multiplexer is enabled and select inputs A, B, and C determine which of the data inputs D0 to D7 is selected to the output.. Fig.6.2.4 shows the block diagram of the given Boolean-function using IC-74153 and one two-input OR gate. D0 1 D1 D2 D3 7 Output Y1 Enable 1 C 2 (LSB) (MSB) Y� 32 3 m 1,2,6,7 D4 D5 D6 9 Output D7 � VCC 5V Enable Y2 2 Fig.6.2.4: Block diagram of given function using IC-74153 and two input OR gate Combinational Logic Circuits-Data Processing Circuits [127] 5. Dual 4X1 MUX and 2X1 MUX: The IC 74157 is a quadruple 2-to-1 line (2X1 MUX) with active high 2-data inputs and 1-selection input lines, one active high output, and an active low-enable (strobe) input. A 4X1 MUX can handle a maximum of 4 inputs. When the number of inputs is more than 4, a MUX tree can be used. Fig 6.2.5 shows an arrangement for an 8X1 MUX using two 4X1 MUX (LSB) and one 2X1 MUX (MSB). Two 4X1 MUXs (upper M1 and lower M2) select one output from their 4 data inputs and one 2X1 MUX (M3) selects two data inputs depending on the selected input lines. When the select input of M3 is 0, the output of M1 will be the final output. If the control input of M3 is 1, the output of M2 will be the final output. Fig.6.2.5 shows the block diagram for the above function using IC-74153 and 74157. (a) (b) [128] Experiments in Digital Electronics Enable Control Input E 1 0 A C X 0 0 1 (c) D0 D1 Outputs 74157 74158 Y Y 0 1 D0 Y1 Y D 01 Y2 D1 Y12 D M1 D2 D3 7 (logic- 0 Enable Y1 M3 (d) (LSB) 4 D4 D5 + VCC M2 Enable D6 D7 (logic- 0 Enable Output 9 Y2 (logic- 0 +VCC (5V ) Fig.6.2.5 : IC 74157 (a) Pin diagram (b) Logic diagram (c) Function table (d) Block diagram of above function using IC-74153 and IC-74157. 6. A 2X1 MUX: The IC 74157 is a quadruple 2-to-1 line (2X1 MUX) with active high 2-data inputs and 1-selection input lines, one active high output, and an active low-enable (strobe) input. But the above function has three control inputs; any two control inputs can be shifted to data input as shown in the Table 6.2.3. Here, one variable A is applied to the selection lines and is connected to the MSB input. From Table 6.2.3 the values for the data input lines are calculated. Fig.6.2.6 shows the block diagram for the above function using IC-74157 and a 2-input EX-OR gate. Combinational Logic Circuits-Data Processing Circuits [129] 4 � VCC 5V Output Y� m 1,2,6,7 Fig.6.2.6: Block diagram for the above function using IC-74157 and 2-input EX-OR gate. Table 6.2.3: Three control lines function using two control lines. MUX Data Input D0 D1 7. Control Inputs (2X1MUX) Variable sifted in MUX data inputs 0utput Comments A B C Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 1 1 When A = 0 (D0), output D0 � B � C When A = 1 (D1), Output D1 � BC � BC � B A Quad 2X1 MUX, a 4X1 MUX: The IC 74157 is a quadruple 2-to-1 line (2X1 MUX) has active high 2-data inputs and 1-selection input lines, one active high output, and an active low-enable (strobe) input, and IC 74153 is a dual 4-to-1 line (4X1 MUX) with active high 4-data inputs and 2-selection input lines, one active high output, and an active high-enable (strobe) input. A single 2X1 MUX can handle a maximum of 2-data inputs. When the number of inputs is more than two, a MUX tree can be used. Fig 6.2.7 shows an arrangement for an 8X1 MUX using four 2X1 MUX and one 4X1 MUX. Four 2X1 MUXs select one output from their 2-data inputs and one 4X1 MUX selects four data inputs, depending on the selected input lines. When selecting input lines A, B, C = 000, the output of MUX-(D0) will be the final output. If select inputs lines A, B, C = 111, the output of MUX-(D7) will be the final output. Fig.6.2.7 shows the block diagram for the given function using IC's-74157 and 7453. [130] Experiments in Digital Electronics 74157 D0 4 D1 D2 D0 7 D3 D1 D2 D3 D4 9 D5 11 Y (Output) Enable +VCC D6 12 D7 Enable 0 +VCC A Fig.6.2.7: Block diagram for the above function using IC's-74157 and 74153 Procedure: (1) Insert an IC on the power project board. Connect the power supply to the proper pins. (2) Construct a different logic diagram. (3) Give binary inputs through binary switches. (4) Observe the LED output and verify the function operation. (5) Prepare a truth table for the same. Combinational Logic Circuits-Data Processing Circuits [131] Observation: Truth table for MUXs: Inputs Outputs A B C 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 16X1 8X1 4X1 2X1 Dual 4X1, 2-input OR Dual 4X1, o ne 2X1 Quad 2X1, one 4X1 Result: Verified the output of the giving function using different MUX. Precautions: 1. Check each minterm of ICs by giving control input and data input. 2. Check the power supply of the power project board. 3. Do not leave an input floating. EXPERIMENT-6.3 Object: To study and verify the operation of the demultiplexer as a logic function generator. Equipment/Components required: 1. Equipment: Power Project board, Multi-channel CRO, and digital Multimeter. 2. Components: ICs: One 74138 (One 1X8 DMUX with 3-data select lines, inverted output), One 74139 (Dual 1X4 DMUX with 2-data select line, complemented output), and One 74154 (One 1X16 DMUX with 4-data select lines, active high output), Two IC 7410, and Two IC 7420. Diode: One LED Miscellaneous: One Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: A demultiplexer (DMUX) is a circuit that receives information from a single line and directs it to one of 2n possible output lines. The selection of specific output is Experiments in Digital Electronics [132] controlled by the bit combination of n-selection lines. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2n-output lines and n-selection lines, whose bit combinations determine which input is selected. Therefore, the DMUX is a very convenient logic circuit used in multi output combinational logic circuits. A DMUX is also called a data distributor, since it distributes one of many outputs and steers the binary information to the output line. The enable input (EN) in a DMUX, must be active for normal operation. DMUX are also available in ICs. Some of the common available packages are given in Table 6.3.1. Table 6.3.1: DMUX ICs IC number 74138 74139 74154 74155 74159 Descriptions One 1X8 DMUX with 3-data select lines. Output is inverted input. Dual 1X4 DMUX with 2-data select lines. Output is complemented. One 1X16 DMUX with 4-data select lines. Output is same as input. Dual 1X4 DMUX with 2-data select lines. Two outputs – one is complemented and other is same as input. One 1X16 DMUX with 4-data select lines. Output is same as input open collector. Combinational logic implementation: The minterms of a function are generated in a DMUX by the circuit associated with the selection inputs. The individual minterms can be selected by the data outputs. This provides a method of implementing a Boolean function of ‘n’ variables with a DMUX that has n-selection inputs and 2n- data outputs, one for each minterm. Let us consider the following minterm expression of three variables: Y1 ( A, B, C ) � � m (0,2,3,6) Y2 ( A, B, C ) � � m (1,5,6,7) Y3 ( A, B, C ) � � m (3,4,5) These functions can be implemented with: 1. A 1-line-to-16 line (1X16) DMUX and NAND gate: IC 74154 is a 1-line-to-16 line (1X16) DMUX with active low outputs (as indicated by small circles at outputs). Therefore, a NAND gate is required. The above expressions have only three variables (eight outputs). Out of sixteen, any eight outputs can be used depending upon the selection of inputs. If we take the first three as control inputs and the last one as MSB, Giving MSB = logic 0, means the first eight DMUX outputs will be low, used in the above 1X8 functions and leaving others. The above multi output function is implemented with IC74154 and NAND gates as shown in Fig.6.3.1. Combinational Logic Circuits-Data Processing Circuits [133] (a) (b) Inputs Enable Data D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 x 1 0 x 1 1 x x = Don’t care C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x x x B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x x x A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x x x 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (c) 5 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 6 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 Outputs 7 8 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 12 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 13 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 [134] Experiments in Digital Electronics logic c '0' 18 Y0 19 Y1 EN 1×16 Y2 24 +5V VCC DMUX Y3 12 GND Y4 Din Y5 Y6 Y7 (d) Logic '0' 1 1 2 3 4 5 6 7420 9 7420 7 8 7410 Y1 � �m 0,2,3,6 6 Y2 � �m 1,5,6,7 8 Y3 � �m 3,4,5 6 D C B A (LSB) Fig.6.3.1 : IC74154 (a) Pin diagram (b) Logic diagram (c) Function table (d) Block diagram of given function using IC-74154 and 3 NAND gates. 2. A 1X8 DMUX and NAND gate : The IC74138 is a 1-line-to-8 line (1X 8) DMUX, having active low outputs. Connect the multi output function in the three NAND gates. The above multi output function is implemented with IC74138 and NAND gates as shown in Fig.6.3.2. (a) Combinational Logic Circuits-Data Processing Circuits [135] (b) (c) Inputs Enable Inputs G2B G2A G1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 x x 0 x 1 x 1 x x x = Don’t care Data (6) Outputs C 0 0 0 0 1 1 1 1 x x x Select B 0 0 1 1 0 0 1 1 x x x (15) A 0 1 0 1 0 1 0 1 x x x 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 2 1 1 0 1 1 1 1 1 1 1 1 3 1 1 1 0 1 1 1 1 1 1 1 1 7420 (14) 4 1 1 1 1 0 1 1 1 1 1 1 5 1 1 1 1 1 0 1 1 1 1 1 6 1 1 1 1 1 1 0 1 1 1 1 7 1 1 1 1 1 1 1 0 1 1 1 Y1 � �m 0,2,3,6 6 (13) 1×8 DMUX (12) (11) (d) logic c '0' 18 19 74138 (10) EN (4) (9) EN (5) (7) C B 9 7420 7410 Y2 � �m 1,5,6,7 8 Y3 � �m 3,4,5 6 A (LSB) Fig.6.3.2: IC74138(a) Pin diagram (b) Logic diagram (c) Function table Block diagram of given function. (d) [136] Experiments in Digital Electronics 3. Dual 1X4 DMUX and NAND gate: The IC74139 is a 1-line-to-4 line (1X4 DMUX, having active high selection, enabled input and active low outputs, The above expressions have only three variable (eight outputs), but above chip has only four outputs. The remaining four can be expanded by using one more 1X4 DMUX, taking enable as a control input as shown in Table 6.3.2. Therefore, the dual 1X4 DMUX can be converted to 1X8 DMUX as shown in Fig. 6.3.3. Table 6.3.2: Function table for 1X8 DMUX using two 1X4 DMUX Enable inputControl input of 1X4 DMUX Comments C 0 0 0 0 1 1 1 1 (a) (b) B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 Make upper DMUX enable for first four enable input (C = 0) and disable for last four (C = 1). Make lower DMUX enable for last four enable input (C = 1) and disable for first four (C = 0). Combinational Logic Circuits-Data Processing Circuits [137] Inputs Strobe/Enable G 0 0 0 0 1 x = Don’t care (c) 74139-1 1×4 DMUX EN (1) 74139-2 1×4 DMUX (d) EN (15) C B Outputs Select B A 0 0 0 1 1 0 1 1 x x 4 0 0 1 1 1 1 1 1 0 1 1 1 2 1 1 0 1 1 1 2 4 5 6 7 5 7420 3 1 1 1 0 1 Y1 = Sm (0,2,3, 6 ) 6 Y2 = Sm (1,5,6,7 ) 9 12 10 12 13 11 10 9 7420 3 4 5 7410 8 Y3 = Sm (3, 4,5 ) 6 A (LSB) Fig.6.3.3: IC74139 (a) Pin diagram (b) Logic diagram (c) Function table (d) Block diagram of given function. Procedure: (1) Insert IC on the power project board. Connect the circuit as shown in the above. (2) Give binary inputs A, B, C through binary switches or hook them up to the logic-1 and logic-0. (3) Verify the each function operation by observing the LEDs output. (4) Prepare the truth table. Observation Table: 1. DMUX Inputs Output (Y) using DMUXs and gate C B A 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1X16 1X8 Dual 1X4 [138] Experiments in Digital Electronics Result: Verified the output of the givin function using different DEMUX. Precautions: 1. Check each minterm of ICs by giving control input and data input. 2. Check the power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-6.4 Object: To study and verify the operation of decoders-drivers. Equipment/Components required: 1. Equipment: Power Project board and digital Multimeter. 2. Components: ICs: One 74138 (One 1X8 DMUX with 3-data select lines, inverted output), One 74139 (Dual 1X4 DMUX with 2-data select line, complemented output), and One 74154 (One 1X16 DMUX with 4-data select lines, active high output), One 7420 (Dual 4-input NAND gates and One 7410 (Triple 3-input NAND gates). Diode: One LED Miscellaneous: One Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: Decoder: A decoder is similar to a demultiplexer, with one exception-there is no data input. The only inputs are the selection bits. A circuit is called 4-of-16 decoder depending upon the selection inputs. The selection of a specific output is controlled by the bit combination of selection lines. A 1X4 DMUX with an enable (EN) input can be used as 2X4 decoder by giving an enable (EN) input-to enable the DMUX. Therefore, decoder is a very convenient logic circuit used in combinational logic circuit. Some commonly used decoders-drivers are: binary-to-octal decoder (3X8,) binaryto- decimal decoder (4X16), BCD-to-decimal decoders (4X10), and BCD-to- Seven– Segment Decoder. Decoders-drivers are also available in ICs. Some of the common available decoder ICs is given in Table 6.4.1 Combinational Logic Circuits-Data Processing Circuits [139] Table 6.4.1: decoder/driver ICs IC number Descriptions 7441 BCD-to-decimal decoder-nixie driver 7442 BCD-to-decimal decoder 7443 Excess 3 to decimal decoder 7445 BCD-to-decimal decoder-driver. 7446 BCD-to-seven segment decoder- drivers (30 V output), drives a common-anode indicator. 7447 BCD-to--seven segment decoder- drivers (15 V output) 7448 BCD-to--seven segment decoder- drivers drives a commoncathode indicator. 74141 BCD-to-decimal decoder- driver 74145 BCD-to-decimal decoder- driver Combinational logic implementation: In a decoder, the minterms of a function are generated by the circuit which are associated with the selection inputs. The individual minterms can be selected by the data outputs which provides a method of implementing a Boolean function of ‘n’ variables with a decoder having n-selection inputs and 2n -data outputs, one for each minterm. Let us consider the following minterm expression of three variables: Y1 ( A, B, C ) � � m (0,2,3,6) Y2 ( A, B, C ) � � m (1,5,6,7) Y3 ( A, B, C ) � � m (3,4,5) These functions can be implemented with: 1. A 4-line-to-16 line (4X16) Decoder and NAND gate: IC 74154 is a binary to decimal decoder (4X16) decoder, having active low outputs. Therefore, a NAND gate is required to implement the above three variable outputs. The above expressions is only three selection lines, out of sixteen only eight output lines can be used depending upon the selection inputs lines. If we use first three as selection inputs (A, B, and C) and D as MSB. Giving D = logic 0, the first eight outputs will be low. The above 3X8 decoder multi output function can be implemented with 4X16 decoder and NAND gates as Similar to Fig. 6.3.1. 2. A 3X8 Decoder and NAND gate : IC74138 is a binary to octal decoder (3X8) decoder, having active low outputs. Connect the outputs of 3X8 decoder in the multi outputs function in the NAND gate as Similar to Fig. 6.3.2. [140] Experiments in Digital Electronics 3. Dual 2X4 Decoder and NAND gate: IC74139 is a (2X4) decoder, having active high control, enabled input and active low outputs. The above expressions have only three variables (eight outputs), but the above chip has only four outputs. The remaining four can be expanded by using one more 2X4 decoder, taking enable as a control input as shown in Table 6.4.2. Therefore, the dual 2X4 decoder can be converted to a 3X8 decoder as Similar to Fig. 6.3.3. Table 6.4.2: Function table for 3X8 decoder using two 2X4 decoder Enable Control input of Comments input 1X4 decoder C B A 0 0 0 Make upper decoder enable for first four enable Input (C = 0) and disable for last four (C = 1). 0 0 1 0 1 0 0 1 1 1 0 0 Make lower decoder enable for last four enable Input (C = 1) and disable for first four (C = 0). 1 0 1 1 1 0 1 1 1 Procedure: (1) Insert an IC on the power project board. Connect the circuit as shown in the above figures. (2) Give binary inputs A, B, C, and D through binary switches. (3) Observe the outputs. (4) Prepare the truth table. Observation: Truth table for decoder-driver C 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 I n pu ts B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 4X 16 D e co d er -dr iv er o u tpu ts 3X 8 D ua l 2 X 4 Combinational Logic Circuits-Data Processing Circuits [141] Result: Verified the output of given functions using different decoders. Precautions: 1. Check all the IC's and gates used in the circuits before making them use. 2. Check the power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-6.5 Object: To study and verify the operation of display devices and their decoders-drivers. Equipment/Components required: 1. Equipment: Power Project board, Multi-channel CRO, and digital Multimeter. 2. Components: ICs: One 7446/7447 (BCD-to-seven segment decoder- drivers: drives a common anode type seven segment display), and One 7448/7449 (BCDto-seven segment decoder- drivers: drives a common cathode type seven segment display), Display: One common anode: seven segments display, and one common cathode: seven segments display. Miscellaneous: Seven resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: Display devices: The LED is the most commonly used display device. This is very efficient because electrical energy is converted directly into light. Its brief theory has been discussed in the first unit point 3. 1. Seven Segment Displays: A group of seven LEDs is formed into a seven segment display. Each LED is called a segment because it forms a part of the character being displayed. Individual segments can be lit to represent the decimal numbers 0 to 9 plus a few letters of the alphabet. Usually, the decimal digit is available in BCD. A BCD-to-seven-segment decoder/driver accepts a decimal digit in BCD and generates the corresponding sevensegment code. The layout of the seven segment display is given in Fig.3. There are two ways to connect the seven segments; they are the common anode and the common cathode, as shown in Fig, 6.5.1. 2. Common Anode LED displays: The diode used to form the segments may have all their anodes connected [142] Experiments in Digital Electronics together. With the common anode display, all the anodes are connected to the positive supply rail. Each individual diode cathode is then switched to ground to illuminate the diode. Fig.6.5.1(a) shows the seven segment display of the common cathode 3. Common cathode LED displays: The diode used to form the segments may have all their cathodes connected together. With the common cathode display, all the cathodes are connected to the ground. Each individual diode anode is then switched to a positive supply to illuminate the diode. Fig.6.5.1(a) shows the seven segment display of common cathode. Some of the common available packages are given in table 6.5.1. Table 6.5.1: decoder-driver ICs IC number 7446 7447 7448 Descriptions BCD-to-seven segment decoder- drivers (30 V output), drives a common-anode indicator. BCD-to-seven segment decoder- drivers (15 V output) BCD-to-seven segment decoder- drivers drives a common-cathode indicator. 4. Seven-Segment decoder-driver: 4.1 The Common-Anode Seven Segment Display Decoder drive: There are two types of decoder-driver, corresponding to the common-anode and common cathode indicators. Each decoder-driver has 4 input pins (the BCD input) and seven output pins (a through g segments).The IC 7446A, 47A, and LS47 are BCD-to-seven segment display, active-low outputs designed for driving commonanode LEDs or incandescent indicators directly. Fig.6.5.1 shows a 7446 driving a common-anode indicator. Logic circuits inside the 7446 convert the BCD input to the required output. You have to connect external resistors to limit the current in each segment to a safe value between 1 and 50 mA, depending on how bright you want the display to be. (a) Combinational Logic Circuits-Data Processing Circuits [143] (b) Pin No. 1 2 3 (c) 4 Pin Name B C Display test / Lamp test Blank Input 5 6 7 8 9 10 11 12 13 14 15 16 Store D A GND e d c b a g f +Vcc Description BCD input of the IC BCD input of the IC To test the display LED To turn-off the LEDs of the display Store or strobe a BCD code BCD input of the IC BCD input of the IC Ground 7 segment output 1 7 segment output 2 7 segment output 3 7 segment output 4 7 segment output 5 7 segment output 6 7 segment output 7 IC Supply Voltage (d) Fig.6.5.1: (a) Common Anode LED's (b) 7446/7447 pin-diagram (c) Pin description (d) Circuit diagram Experiments in Digital Electronics [144] 4.2 The Common-Cathode Seven- Segment Display Decoder drive: The IC 7448, LS48 and LS49 are BCD-to-seven segment displays with active high outputs for, driving lamp buffers or common-cathode LEDs. All the circuits except the LS49 have full ripple-blanking input/output controls and a lamp test input. The LS49 features a direct blanking input. The display pattern for BCD input count above nine are unique symbols to authenticate input conditions. All of the circuits except the LS49 incorporate automatic leading/or trailing-edge, zero-blacking control (RBI and RBO). The lamp test (LT) of these devices may be performed at any time when the BI/RBO node is at a high logic level. All types (including LS 49) contain an overriding blanking input (BI) which can be used to control the lamp intensity (by pulsing), or to inhibit the outputs. Fig.6.5.2 shows a 7448 driving a common-cathode indicator. Logic circuits inside the 7448 convert the BCD input to the required output. Unlike the 7446, which requires external current-limiting resistors, the 7448 has its own current–limiting resistors on the chip. Table 6.5.2 shows a logic function table for IC 7446A, 7447A and Table 6.5.3 shows a logic function table for IC 7448. (a) (b) Fig.6.5.2: 7448/49 decoder-driving a common-cathode indicator : (a) Pin diagram (b) Circuit diagram Combinational Logic Circuits-Data Processing Circuits [145] Table 6.5.2: function table for IC 7446A,7447A. D ec ima l or fu n c ti o n 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BI R BI LT In p u ts LT RBI D C B A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X 1 0 1 X X X X X X X X X X X X X X X X 0 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X 0 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X 0 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X 0 X 7 4 4 6 A ,7 4 BI / RB O N o te (1 ) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 4 7A O u tp u ts N o te a b c d e F g 0 1 0 0 1 0 1 0 0 0 1 1 1 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 1 1 0 0 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 1 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 ( 2) ( 3) ( 4) ( 5) * 0 = ground, 1 = VCC and X = don't care Table 6.5.3: function table for IC 7448. Decimal or function 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BI RBI LT Inputs LT R BI D C B A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X 1 0 1 X X X X X X X X X X X X X X X X 0 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X 0 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X 0 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X 0 X 7 448 BI / RBO Note (1 ) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 Outputs a b c d e F g 1 0 1 1 0 1 0 1 1 1 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 0 0 0 1 1 1 0 1 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 N ote ( 2) ( 3) ( 4) ( 5) Note (1): BI/RBO is a wire-AND logic serving as blanking input (BI) and /or ripple blanking output (RBO). [146] Experiments in Digital Electronics Note (2): The blanking input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired. The ripple-blanking input (RBI) must be open or high if blanking of a decimal zero is not desired. Note (3): When a low logic level is applied directly to the blanking input (BI), all segment outputs are high (46, 47), regardless of the level of any other input. Note (4): When ripple-blanking input (RBI) and inputs A, B, C, and D are at a low level with the lamp test input high, all segment outputs go high and the rippleblanking output (RBO) goes to a low level (response condition). Note (5): When the blanking- output (BI/RBO) is open or held high and a low is applied to the lamp-test input, all segment outputs are low. Input BI/RBO is a wire-AND logic serving as a blanking input (BI) and /or ripple blanking output (RBO). Procedure: (1) Insert an IC on the power project board. Connect the circuit as shown in the above figures. (2) Give binary inputs A, B, C, and D through binary switches or hook them up to the +5V supply (logic 1) or ground (logic 0). (3) Observe the outputs. (4) Prepare the truth table. Observation Table: Inp ut s A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D ecod er -d ri ver ou tp uts Com mon anode C om mon ca thode Result: Verified the operations of display devices and their decoder-drivers. Combinational Logic Circuits-Data Processing Circuits [147] Precautions: 1. Check all the IC's and gate used in the circuits before making them use. 2. Check power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-6.6 Object: To study encoder logic circuits and verifies their operation. Equipment/Components required: 1. Equipment: Power Project board, Digital IC tester, and digital Multimeter. 2. Components: ICs: Three 7432 (Four, two input OR gate), 74147 (Decimal to BCD priority encoder, active low input and output), 74148 (Priority encoder). Diode: Four LEDs Miscellaneous: Four Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: 1. Encoder: An encoder converts an active input signal into a coded output signal. It has 2n (or fewer) input lines and no output lines. The output lines generate the binary code corresponding to the input value. Table 6.6.1 is the truth table of the octal to binary encoder. It has eight inputs and three outputs that generate the corresponding binary number. Another common type of encoder is the decimal-to-BCD encoder. Fig. 6.6.1 shows the logic diagram for the octal to binary encoder. Table 6.6.1: truth table of octal to binary encoder D0 1 0 0 0 0 0 0 0 D1 0 1 0 0 0 0 0 0 D2 0 0 1 0 0 0 0 0 Inputs D3 D4 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 D5 0 0 0 0 0 1 0 0 D6 0 0 0 0 0 0 1 0 D7 0 0 0 0 0 0 0 1 Outputs A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 [148] Experiments in Digital Electronics Design: These conditions can be expressed by the following output Boolean functions; A � D1 � D3 � D5 � D7 B � D2 � D3 � D6 � D7 C � D4 � D5 � D6 � D7 The encoder can be implemented with three nine two-input gates as shown in the Fig6.6.1. Octal (Input) D7 D6 D5 D4 D3 D2 D1 D0 1 2 32 12 13 32 9 10 32 3 4 5 32 11 1 2 32 12 32 8 13 6 9 10 3 32 4 5 32 11 1 2 32 8 6 3 A B Binary (Output) C Fig.6.6.1: octal-to-binary encoder 2. Priority Encoder: The encoder, which is defined in the above table, has the limitation that only one input can be active at any given time. If two inputs are active simultaneously, the output produces an undefined combination. For example, if D3 and D6 are ‘1’ simultaneously, the output of the encoder will be 111 because all three outputs are equal to ‘1’. This does not represent either binary ‘3’ or binary ‘6’. To resolve this ambiguity, encoder circuits must establish an input priority to ensure that only one input is encoded. If we established a higher priority for inputs with higher subscript Combinational Logic Circuits-Data Processing Circuits [149] numbers, and if both D3 and D6 are high '1' at the same time, the output will be 110 because D6 has a higher priority than D3. Another ambiguity in the octal to binary encoder is that an output with all 0’s is generated when all the inputs are 0; this output is the same as when D0 is equal to 1. The discrepancy can be resolved by providing one more output to indicate that at least one input is equal to '1'. Table 6.6.2 is the truth table for decimal to BCD highest priority encoder. Table 6.6.2: Truth table of a decimal to BCD highest priority encoder D0 D1 D2 D3 0 1 X X X X X X X X X 0 0 1 X X X X X X X X 0 0 0 1 0 X X X X X X 0 0 0 0 1 X X X X X X Inputs D4 D5 0 0 0 0 0 1 X X X X X 0 0 0 0 0 0 1 X X X X D6 D7 D8 D9 A B 0 0 0 0 0 0 0 1 X X X 0 0 0 0 0 0 0 0 1 X X 0 0 0 0 0 0 0 0 0 1 X 0 0 0 0 0 0 0 0 0 0 1 X 0 0 0 0 0 0 0 0 1 1 X 0 0 0 0 1 1 1 1 0 0 Outputs C D X 0 0 1 1 0 0 1 1 0 0 X 0 1 0 1 0 1 0 1 0 1 V(valid Bit) 0 1 1 1 1 1 1 1 1 1 1 Using k map simplification, the simplified Boolean expressions for the highest priority encoder are: A � D8 � D9 B � D4 D 8 D 9 � D5 D 8 D 9 � D6 D 8 D 9 � D7 D 8 D 9 � D 8 D 9 ( D4 � D5 � D6 � D7 ) C � D2 D 4 D 5 D 8 D 9 � D3 D 4 D 5 D 8 D 9 � D6 D 8 D 9 � D7 D 8 D 9 D � D1 D 2 D 4 D 6 D 8 � D3 D 4 D 6 D 8 � D5 D 6 D 8 � D7 D 8 � D9 V � D0 � D1 � D2 � D3 � D5 � D6 � D7 � D8 � D9 Encoders are also available as ICs. The available packages are given in Table 6.6.3. Table 6.6.3: Encoder ICs IC number 74147 74148 Description Decimal to BCD priority encoder ( active low input and output) Priority encoder [150] Experiments in Digital Electronics (a) (b) 1 1 x x x x x x x x 0 2 1 x x x x x x x 0 1 Decimal Inputs BCD Outputs BCD (active low inputs) (active low outputs) (negative logic) 3 1 x x x x x x 0 1 1 4 1 x x x x x 0 1 1 1 5 1 x x x x 0 1 1 1 1 6 1 x x x 0 1 1 1 1 1 7 1 x x 0 1 1 1 1 1 1 8 1 x 0 1 1 1 1 1 1 1 9 1 0 1 1 1 1 1 1 1 1 D 1 0 0 1 1 1 1 1 1 1 C 1 1 1 0 0 0 0 1 1 1 B 1 1 1 0 0 1 1 0 0 1 A 1 0 1 0 1 0 1 0 1 0 0 9 8 7 6 5 4 3 2 1 +VCC (5V ) Current limiting resister LED’s 14 6 (c) 7 9 BCD outputs Fig. 6.6.2: IC 74LS147 (a) Pin diagram (b) Function table (c) Block diagram of decimal to BCD encoder. Combinational Logic Circuits-Data Processing Circuits [151] The function table for Deciml to BCD encoder and octal to binary encoder are shown in table 6.6.4. Table 6.6.4: (a) Decimal to BCD encoder (b) Octal to binary encoder E1 1 0 X X X X X X X X EI 1 0 0 0 0 0 0 0 0 0 E2 1 1 0 X X X X X X X E0 X 1 0 X X X X X X X E3 1 1 1 0 X X X X X X E1 X 1 1 0 X X X X X X E4 1 1 1 1 0 X X X X X E2 X 1 1 1 0 X X X X X Inputs E5 1 1 1 1 1 0 X X X X E3 X 1 1 1 1 0 X X X X E4 X 1 1 1 1 1 X X X X E6 1 1 1 1 1 1 0 X X X E7 1 1 1 1 1 1 1 0 X X E5 X 1 1 1 1 1 1 0 X X (a) E6 X 1 1 1 1 1 1 1 0 X E8 1 1 1 1 1 1 1 1 0 X E7 X 1 1 1 1 1 1 1 1 0 E9 1 1 1 1 1 1 1 1 1 0 QC 1 1 1 1 1 1 0 0 0 0 QD 1 1 1 1 1 1 1 1 0 0 QB 1 1 1 1 0 0 1 1 0 0 QC 1 1 1 1 0 0 0 0 1 1 QA 1 1 1 0 1 0 1 0 1 0 Outputs QB 1 1 0 0 1 1 0 0 1 1 QA 1 0 1 0 1 0 1 0 1 0 GS 1 1 0 0 0 0 0 0 0 0 E0 1 0 1 1 1 1 1 1 1 1 (b) The GS is active low when any input is low : This indicates when any input is active. The EO (Enable output) is active low when all inputs are high. Using the enable output along with the enable input (EI), allows priority encoding of N-input singls. Both EO and GS are active high when the enable input is high. (a) [152] Experiments in Digital Electronics Octal Inputs (b) BCD Outputs Enable Input 0 1 2 3 4 5 6 7 C B A GS Enable Output 1 0 0 0 0 0 0 0 0 0 x 1 x x x x x x x 0 x 1 x x x x x x 0 1 x 1 x x x x x 0 1 1 x 1 x x x x 0 1 1 1 x 1 x x x 0 1 1 1 1 x 1 x x 0 1 1 1 1 1 x 1 x 0 1 1 1 1 1 1 x 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 +VCC (5V ) LED’s Current limiting resister 6 7 9 (c) Binary outputs EI Fig.6.6.3: 74LS148 (a) pin diagram and (b) function table (c) Block diagram of octal to binary encoder. Procedure: (1) Insert an IC on the power project board. Connect the circuit as shown above. (2) Give input through binary switch or hook them up to the +5V supply (logic 1) or ground (logic 0). (3) Observe the outputs. (4) Prepare the truth table. Combinational Logic Circuits-Data Processing Circuits [153] Observation: 1. Decimal to BCD highest priority encoder: 0 1 X X X X X X X X X 0 1. 1 1 X X X X X X X X 0 1 2 1 X X X X X X X 0 1 1 Decimal Inputs BCD Outputs BCD (active low inputs) (active low outputs) (negative logic) 3 1 X X X X X X 0 1 1 1 4 1 X X X X X 0 1 1 1 1 5 1 X X X X 0 1 1 1 1 1 6 1 X X X 0 1 1 1 1 1 1 7 1 X X 0 1 1 1 1 1 1 1 8 1 X 0 1 1 1 1 1 1 1 1 9 1 0 1 1 1 1 1 1 1 1 1 D C B A Truth table for octal to binary encoder: Octal Inputs Primary Outputs Enable Input 0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 0 0 0 x 1 x x x x x x x 0 x 1 x x x x x x 0 1 x 1 x x x x x 0 1 1 x 1 x x x x 0 1 1 1 x 1 x x x 0 1 1 1 1 x 1 x x 0 1 1 1 1 1 x 1 x 0 1 1 1 1 1 1 x 1 0 1 1 1 1 1 1 1 C B A GS Enable Output Result: Verified the above encoder logic circuits. Precautions: 1. Check all IC's used in the circuits before making them use. 2. Check power supplies of the power project board. 3. Do not leave an input floating. [154] Experiments in Digital Electronics 7. Sequential Circuits-Flip-Flops EXPERIMENT-7.1 Object: To study and verify the operation of SR, D, JK, and T Flip-Flops using universal gate ICs. Equipment/Components required: 1. Equipment: Power Project board and Digital Digital Multimeter. 2. Components: ICs: One 7404 (Hex inverter), One 7400 (Quadruple 2-input NAND gates), One 7402 (Quadruple 2-input NOR gates), One 7410 (Triple 3input NAND gates). Diode: Two LEDs Miscellaneous: Two Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: A Flip-flop is a digital circuit that has two outputs, Q and Q , which are always in opposite states. If Q is high 'l', then Q is low '0', and the flip-flop is said to be set, on, or preset. If Q is low '0', then Q is high '1' and the flip-flop is said to be reset, off, or clear. It is also known as a sequential circuit, which can maintain a binary state indefinitely (as long as power is delivered to the circuit) until directed by an input signal to switch states. The most basic types of flip-flops operate at signal levels and are referred to as latches. Flip-flops are constructed from basic circuits (latch). There are several types of flip-flop. 1. Latchs Types: 1.1 SR latch: The two NAND gates are cross-coupled so that the output first NAND/NOR gate is connected to one of the input of second NAND/NOR gate and vice-versa. It has two inputs, ‘S’ (set) and ‘R’ (reset). The two crossed NAND/NOR gates in Fig. 7.1.1 and 7.1.2 form a set reset latch. Sequential Circuits-Flip-Flops [155] Inputs Outputs S R Q Q 0 0 Q(t) Q (t ) 0 1 1 1 0 1 0 1 0 1 0 0 (a) Comments Present state Reset Set Race condition (b) (c) Fig.7.1.1: SR latch with NOR gates (a) function table (b) logic diagram (c) graphic symbol Inputs Outputs S R Q Q 0 0 1 1 0 1 1 0 1 0 0 1 1 1 Q(t) Q (t ) Comments Race condition Set Reset Present state (a) (b) (c) Fig.7.1.2: SR latch with NAND gates (a) function table (b) logic diagram (c) graphic symbol 1.2 SR latch with control input: The SR latch can be modified by providing an additional control input that determines when the state of the latch can be changed. The logic diagram and its function table are shown in Fig.7.1.3. Inputs C S R 0 X X Outputs Q Q Q(t) Q (t ) 1 0 0 Q(t) Q (t ) No change 1 1 1 0 1 1 1 0 1 0 1 1 1 0 1 Reset Present state Race condition (a) Comments No change (b) (c) Fig.7.1.3: SR latch with NAND gates and control input (a) function table (b) logic diagram (c) graphic symbol [156] Experiments in Digital Electronics 1.3 D-Latch: One way to eliminate the race condition/undesirable condition of the indeterminate state in the SR latch is D-latch. This circuit is often called a data/ transparent latch. The logic diagram and its function table are shown in Fig.7.1.3. Inputs Outputs D 1 2 1 2 D Q Q Comments 0 1 0 1 1 0 Reset Set 00 4 5 00 3 6 Q Q (a) (b) (c) Fig.7.1.4: D latch with NAND gates (a) function table (b) logic diagram (c) graphic Symbol 1.4 D-Latch with control input: This latch has only two inputs {D (data) and C (control)} and two outputs � Q andQ � . The logic diagram and its function table are shown in Fig.7.1.5. Inputs Input Outputs s C D Q Q Comments 0 X Q(t) Q (t ) No change/Present state 1 0 1 1 Reset 0 1 1 0 Set (a) (b) (c) Fig.7.1.5: D latch with control input (a) function table (b) logic diagram (c) graphic Symbol 2. Flip-Flop Types: The state of a latch or flip-flop is switched by a change in the control input. This momentary change is called a trigger and the transition it causes is said to trigger the flip-flop. The D-latch with pulses in its control input is essentially a flip-flop that is triggered every time the pulse goes to the logic '1' level. As long as the pulse input remains in this level, any changes in the data input will change the output and the state of the latch. Flip-flop circuits are constructed in such a way as to make them operate properly when they are part of a sequential circuit that employs a common clock. The problem Sequential Circuits-Flip-Flops [157] with the latch is that it responds to a change in the level of a clock pulse. A positive level response in the control input allows changes, in the output when the input changes while the clock pulse stays at logic 1. The key to proper operation of a flip-flop is to trigger it only during a signal transition. A clock pulse goes through two transitions from 0 to 1 and return from 1 to 0. The positive transition is defined as the positiveedge and the negative transition as the negative-edge as shown in Fig.7.1.6 (b, and c). There are two ways that a latch can be modified to form a flip-flop. One way is to employ two latches in a special configuration that isolates the output of the flip-flop from being affected while its input is changing. Another way is to produce a flip-flop that triggers only during a signal transition (from 0 to 1 or from 1 to 0), and is disabled during the rest of the clock cycle pulse duration. Positive edge means positive transition i.e. signal transition from 0 to 1. Negative edge means negative transition, i.e. signal transition from 1 to 0. (a) Response to positive level (b) Positive-edge response (c) negative-edge response Fig.7.1.6: clock response in latch and flip-flop 2.1 Edge-triggered D, JK and T flip-flop: A clock input is included in edge-triggered flip-flops. This input is marked with a small triangle. The most economical and efficient flip-flop is the edge-triggered D flip-flop because it requires the smallest number of gates. Other types of flip-flops that can be constructed by using the D flip-flop and external logic used in the design of digital systems are the JK and T flip-flops. Fig.7.1.7 shows the function table, graphic symbol of the D flip-flop. The function table, graphic symbol of a JK and T flip-flop constructed with a D flip-flop is shown in Fig. 7.1.8.and Fig. 7.1.9. There are three operations performed on a flip-flop: set it to 1, reset it to 0, or compliment its output. This can be verified by investigating the circuit applied to the D input: Inputs Output CLK D Comments Q Q 0 X Q(t) Q (t ) Present State No change 1 1 0 1 0 1 1 0 Set Reset (a) (b) (c) Fig.7.1.7: Positive edge-triggered D Flip-Flop (a) functional table (b) logic diagram (c) graphic symbol. Experiments in Digital Electronics Inputs Output Comments CLK J K Q Q 0 X X Q(t) Q (t ) Present State/ No change 1 0 0 Q(t) Q (t ) No change 1 1 1 0 1 1 1 0 1 1 0 0 1 Set Reset Toggle Q (t ) [158] Q (t ) (a) (b) (c) Fig.7.1.8: Positive edge-triggered JK Flip-Flop (a) function table (b) logic diagram (c) graphic symbol Inputs CLK Output Comments T Q Q 0 X Q(t) Q (t ) 1 0 Q(t) Q (t ) 1 1 Q (t ) Q(t) Present State/ No change Present State/ No change Toggle (a) (b) (c) Fig.7.1.9: Positive edge-triggered T Flip-Flop (a) function table (b) logic diagram (c) graphic symbol 2.2 Race-Around Condition of JK flip-flop: The inherent difficulty of S-R flip-flop (i.e., S = R = 1) is eliminated by using the feedback connections from the outputs to the inputs of gate as shown in the JK flip-flop using NAND gates. The truth tables and next state tables of JK and SR flipflop were formed with the assumption that the inputs do not change during the clock pulse (CLK=1). But the consideration is not true because of the feedback connections. Fig, 7.1.10: A clock pulse. [159] Sequential Circuits-Flip-Flops In JK flip-flop the inputs are J = K = 1 and Q = 1, and a pulse as shown in Fig, 7.1.10 is applied at the clock input. After a time interval t p equal to propagation delay through two NAND gates in series, the outputs will change to Q = 0. So now we have J = K = 1 and Q = 0. After another time interval of the output will change back to Q=1. Hence, we conclude that for the time duration to �t of the clock pulse, the output will oscillate between 0 and 1. Hence, at the end of the clock pulse, the value of the output is not certain. This situation is referred to as race-around condition. Generally, the propagation delay of TTL gates is of the order of nano-seconds. So if the clock pulse is of the order of micro-seconds, then the output will change thousands of times within the clock pulse. This race-around condition can be avoided if �t � 2t p � T . Due to the small propagation delay of the ICs, it may be difficult to satisfy the above condition. A more practical way to avoid the problem is to use the master-slave configuration. 1.1 Master-Slave D Flip-flop: The first flip-flop is called the master and the second, the slave. The circuit samples the D input and changes its output Q only at the positive-edge of the clock input. When the clock is '0', the output of the inverter is '1'. The slave flip-flop is enabled and its output Q is equal to the master output. The master flip-flop is disabled because the clock is '0'. When the input pulse changes to the logic '1' level, the data from the external D input is transferred to the master. The slave, however, is disabled as long at the clock remains in the 'l' level because its clock input is equal to '0'. Any change in the input changes the master output, but can’t affect the slave output. When the pulse returns to '0', the master is disabled and is isolated from the D input. At the same time, the slave is enabled and the value of the master is transferred to the output of the flip-flop at Q. Thus, the output of the flip-flop can change only during the operation of the clock from '1' to '0'. It is also possible to design the circuit so that the flip-flop output changes on the negative edge of the clock. This happens in a flip-flop that has an inverter between the clock terminals of the master and the slave, as shown in Fig. 7.1.11. (a) (b) Fig.7.1.11: Master-Slave D Flip-Flop (a) graphic Symbol (b) logic diagram [160] Experiments in Digital Electronics 2.4 Master-Slave JK flip-flop: A master-slave (M-S) flip-flop is shown in Fig. 7.1.12. Basically a masterslave flip-flop is a system of two flip-flops ones being designated as master and the other is the slave. The clock pulse is applied to the master and the inverted version of the same clock pulse is applied to the slave. When CLK=1, the first flip-flop (i.e., the master) is enabled and the outputs Qm and Q m respond to the input J and K, as shown in figure 7.1.12. At this time, the second flip-flop (i.e., the slave) is disabled because the CLK is low on the second flip-flop. Similarly, when CLK becomes low, the master becomes disabled and the slave becomes active, since now the CLK is high. Therefore, the output Qs and Qs follows the outputs respectively. Since the second flip-flop just follows the first one, it is referred to as. Hence the configuration is referred to as master-slave (M-S) flip-flop. 3. (a) (b) Fig.7.1.12: JK M-S Flip-Flop (a) logic diagram (b) graphic Symbol Characteristics equations for flip-Flops: From the function table for flip-flops, we can make the next state table. Table 7.1.1: Next state/ Characteristics state equation table P.S I/Ps Q(t) S R N.S P.S I/Ps N.S P.S I/P N.S P.S I/P N.S Q(t+1) Q(t) J K Q(t+1) Q(t) D Q(t+1) Q(t) T Q(t+1) 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 X 1 1 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 0 1 1 0 0 0 1 1 0 1 1 1 1 0 1 1 X 1 1 1 1 0 1 1 0 The logical properties of a flip-flop as described in the above function/ * P.S � Present state, N.S � Next state Sequential Circuits-Flip-Flops [161] characteristic table can be expressed also algebraically with a characteristic/next state equation. The characteristics equation/next state equation for the SR flip-flop can be derived from the characteristic table. We obtained �S � RQ (t )� Q (t � 1) SR � � � �SR � 0 � It states that the next state of the output will satisfy the above two equations. For the D flip-flop, The characteristic equation is; Q (t � 1) D � D It states that the next state of the output will be equal to the value of input D in the present state. The characteristics equation/next state equation for the JK flip-flop can be derived from the characteristic table. We obtained Q(t � 1) JK � QJ � KQ Where Q is the value of the flip-flop output prior to the application of the clock edge. The characteristics/next state equation for the T flip-flop is obtained from the next state output value of the T flip-flop in the next state table. Q (t � 1) T � T � Q 4. Asynchronous/direct inputs of Flip-Flops: Some flip-flops have asynchronous inputs that are used to force the flip-flop into a particular state independent of the clock. The input that sets the flip-flop to 1 is called a preset or direct set. The input that clears the flip-flop to 0 is called clear or direct reset. When power is turned on in a digital system, the state of the flip-flop is unknown. The direct inputs are useful for bringing all the flip-flops in the system to a know starting state prior to the clocked operation. The function table, circuit diagram, and graphic symbols of a active high direct inputs of flip-flops are shown in Fig. 7.1.13 and active low inputs are shown in Fig.7.1.14. PRE Asynchronous Inputs PRE 0 0 1 1 F lip flop response 1 2 CLR 0 1 0 1 S Clocked O peration Q = 0 Clear Q = 1 Set Not Used (a) 1 1 2 00 3 2 10 12 Q 11 CLK 3 4 00 R 6 10 4 6 Q 5 5 4 3 (b)typeCLR (c) Fig. 7.1.13: (a) Active high direct inputs of D Flip-Flop (a) function table (b) logic diagram (c) graphic Symbol [162] Experiments in Digital Electronics PRE Asynchronous Inputs PRE CLR 0 0 1 1 0 1 0 1 Flip-flop response S 2 Not Used Q = 1 Set Q = 0 Clear Clocked Operation 1 2 1 00 3 10 12 Q 13 CLK 3 4 00 R 6 4 10 6 Q 5 5 CLR (a) (b) (c) Fig.7.1.14: active low direct inputs of SR type Flip-Flop (a) function table (b) logic diagram (c) graphic Symbol Procedure: (1) Insert ICs on the power project board. Connect the power supply to the proper pin of the chip. (2) Construct the circuit on the breadboard. (3) Connect the LEDs to the output with a current limiting resistor. (4) Connect the inputs of the gate to the switch provided on the trainer/ board or hook them up to the +5V supply (logic 1) or ground (logic 0) as required. (5) Vary these inputs as mentioned in the table and observe LED outputs. (6) Prepare the truth table. Observation Table: P.S Inputs (I/Ps) Next state (N.S) P.S Q(t) 0 0 S 0 0 R 0 1 Q(t+1) Q(t) 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 0 1 1 1 1 Inputs (I/Ps) Next state (N.S) P.S J 0 0 K 0 1 Q(t+1) Q(t) Q(t) 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 1 I/ P Next state (N.S) D 0 1 Q(t+1) Q(t) 0 0 0 1 P.S 1 1 Result: Verified the different latches and flip-flops. Precautions: 1. Check all the gates inside ICs before putting them to use. 2. Check power supplies of the power project board. 3. Do not leave an input floating. I/ P Next state (N.S) T 0 1 Q(t+1) Q(t) Q (t ) 0 1 Sequential Circuits-Flip-Flops [163] EXPERIMENT-7.2 Object: To study and verify Flip-Flops using ICs. Equipment/Components required: 1. Equipment: Power Project board and Digital Multimeter. 2. Components: ICs: One 74 LS 279 (Quad set-reset latch), One IC 7474 (Dual D flipflop), One IC 7473 dual JK flip-flop, One 7476 (Dual JK negative edge triggered master slave). Diode: Two LED Miscellaneous: Two Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: 1. Flip-flops ICs: Flip-flops are available in ICs. Some common types of TTL and CMOS family ICs are giving in table 7.2.1. Table 7.2.1: Most commonly used TTL and CMOS ICs Number 7470 7472 7473 7474 7475 7476 74100 74104 74105 74107 74109 74116 74175 74276 74279 74390 74HC74 74HC73 2. Standard TTL Standard TTL Standard TTL Standard TTL Standard TTL Standard TTL Standard TTL Standard TTL Standard TTL Standard TTL Standard TTL Standard TTL Standard TTL Standard TTL LS Standard TTL CMOS CMOS Function Edge-triggered JK JK master-Slave Dual JK master-slave Dual D Quad latch Dual JK negative edge triggered master slave 4-bit bistable latch JK master-slave JK master-slave Dual JK master slave Dual JK positive edge triggered Dual 4-bit latches with clear Quad D flip-flop with clear Quad JK flip-flop Quad set-reset latch Individual clocks with flip-flops Dual D with set-reset Dual JK with reset. Function table and pin out diagram: The following figures show the function table and pin diagram for the different flip-flop ICs. The function table specifies the circuit operation and pin assignment [164] Experiments in Digital Electronics indicate pin numbers. The IC 74LS279 is a quad set-reset latch. The pinout and function table for this circuit are given in Fig. 7.2.1. Inputs S1 S2 R 0 0 0 1 X 1 X 0 1 1 1 0 1 1 Outputs Q(t) Q (t ) Race condition 1 0 1 0 0 1 1 No change (a) (b) Fig7.2.1: IC 74LS279Set-reset (a) function table (b) pin diagram The IC 7474 is a dual D flip-flops. The pinout and truth table for this circuit are given in Fig. 7.2.2. Outputs (t n �1 ) Q(t) Q (t ) Inputs (t n ) PRE CLR D (S) 1 0 0 1 1 (R) 0 1 0 1 1 X X X 1 0 0 1 1 0 Race condition 1 0 0 1 (a) (b) Fig7.2.2: IC 7474 Dual D flip-flop (a) function table (b) pin diagram The IC 7473 is a dual JK flip-flops. The pinout and function table for this circuit are given in Fig. 7.2.3. Inputs (t n ) J CLR (R) 0 X 1 0 1 1 1 K X 0 Outputs (t n�1 ) Q(t) Q (t ) 0 Q(t) 1 Q (t ) 1 0 1 0 0 1 0 1 1 1 Q(t) Q (t ) (a) (b) Fig7.2.3: IC 7473 dual JK flip-flop (a) function table (b) pin diagram Sequential Circuits-Flip-Flops [165] The IC 7476 is a dual JK flip-flops. The pinout and function table for this circuit are given in Fig. 7.2.4. J K Outputs (t n�1 ) Q(t) Q (t ) X X X 0 0 1 1 X X X 0 1 0 1 1 0 0 1 1 1 No change 0 1 1 0 Toggle Inputs (t n ) PRE CLR ( (S) (R) 0 1 1 0 0 0 1 1 1 1 1 1 1 1 (a) (b) Fig7.2.4: Dual JK negative edge triggered master slave -7476 (a) function table (b) pin diagram Procedure: (1) Insert ICs on the power project board. Connect the power supply to the proper pin of the chip. (2) Connect the LEDs to the output with a current limiting resistor. (3) Connect the inputs of the IC to the switch provided on the trainer/board or hook them up to the +5V supply (logic 1) or ground (logic 0) as required. (4) Vary these inputs as given in the function table and observe LED outputs. (5) Prepare the truth table. Observation Table: P.S Inputs (I/Ps) Q (t ) S R 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 P.S Inputs Next (I/Ps) state (N.S) Q ( t � 1) Q (t ) J K 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Next P.S I/P state (N.S) Q ( t � 1) Q (t ) D Next P.S I/P state (N.S) Q (t � 1) Q (t ) T 0 0 1 1 0 0 1 1 Result: Verified the output for each flip-flop IC. 0 1 0 1 0 1 0 1 Next state (N.S) Q ( t � 1) [166] Experiments in Digital Electronics Precautions: 1. Check each gate in ICs before designing the circuit. 2. Check power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-7.3 Object: To study and verify the conversion of Flip-Flops. Equipment/Components required: 1. Equipment: Power Project board and Digital Multimeter. 2. Components: ICs: One 74 LS 279 (Quad set-reset latch), One IC 7474 (Dual D flip-flop), One 7473 dual JK flip-flop, One 7476 (Dual JK negative edge triggered master slave), One 7400, One 7408, One 7432, One 7404, One 7486. Diode: Two LED Miscellaneous: Two Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: VLSI contains thousands of gates within one package. Circuits are constructed by interconnecting various gates to provide a digital system. Each flip-flop is constructed from an interconnection of gates. The most economical and efficient flip-flop constructed in this manner is the edge-triggered D flip-flop because it requires the smallest number of gates. Other types of flip-flops can be constructed by using the D flip-flop and external logic. JK and T flip-flops are widely used in the design of digital systems. To convert one type of flip-flop into another type, a combination circuit is designed (using function table shown in Table 7.3.1, next state equation shown in Table 7.3.2, and the excitation table shown in Table 7.3.3) and such that if the inputs of the required flip-flop are fed as inputs of the combinational circuit and the output of the combinational circuit is connected to the inputs of the actual flip-flop, then the output of the actual flip-flop is the output of the required flip-flop. Table 7.3.1: Function table of flip-flops Inputs (I/Ps) S 0 0 R 0 1 Next state (N.S) Q(t+1) Q(t) 0 1 1 0 1 1 Race Inputs (I/Ps) J 0 0 K 0 1 Next state (N.S) Q(t+1) Q(t) 0 1 1 0 1 1 Q (t ) I/P D 0 1 Next state (N.S) Q(t+1) 0 1 I/P T 0 1 Next state (N.S) Q(t+1) Q(t) Q (t ) Sequential Circuits-Flip-Flops [167] Table 7.3.2: Next state Characteristics equation table for flip-flops P.S Q(t) 0 0 0 0 1 1 1 1 I/Ps S R 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 N.S Q(t+1) 0 0 1 X 1 0 1 X P.S Q(t) 0 0 0 0 1 1 1 1 I/Ps J K 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 N.S Q(t+1) 0 0 1 1 1 0 1 0 P.S Q(t) 0 0 1 1 I/P D 0 1 0 1 N.S Q(t+1) 0 1 0 1 P.S Q(t) 0 0 1 1 I/P T 0 1 0 1 N.S Q(t+1) 0 1 1 0 Table 7.3.3: Excitation table for flip-flops P.S N.S Flip-flop inputs Q(t) Q(t+1) S R J K D T 0 0 0 X 0 X 0 0 0 1 1 0 1 X 1 1 1 0 0 1 X 1 0 1 1 1 X 0 X 0 1 0 Conversion of flip-flops: With the help of conversion table, we can find the next state decoder circuit for the actual flip-flop converted to another, which is basically a combination circuit. 1. SR flip-flop to D flip-flop: Table 7.3.4: Conversion table for SR to D flip-flop Flip-flop P.S N.Sinputs N.S Required I/Ps Q(t) D Q(t+1) S R 0 0 0 0 X 0 1 1 1 0 1 0 0 0 1 1 1 1 X 0 From the above conversion table, the k-map simplification of the Boolean expressionss for S and R inputs are: S � D , R � D .The SR flip-flop can be converted into D flip-flop by giving the value of S and R in the SR flip-flop. Fig.7.3.1 shows the logic diagram for D flip-flop converted from a SR flip-flop and an inverter. Then the next state equation for SR flip-flop will become the next state equation for the D flipflop: Fig.7.3.1: D flip-flop using SR flip-flop. [168] Experiments in Digital Electronics 2. SR flip-flop to JK flip-flop: Conversion table P.S Q(t) 0 0 0 0 1 1 1 1 Flip-fl op I/P s J K 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 N .S Q(t+ 1) 0 0 1 1 1 0 1 0 R eq u ired I/Ps S R 0 X 0 X 1 0 1 0 X 0 0 1 X 0 0 1 From the above conversion table, the k-map simplification of the Boolean expressions for S and R inputs a re: S � QJ , R � QK .The SR flip-flop can be converted into a JK flip-flop by giving the value of S and R in the SR flip-flop. Fig.7.3.2 shows the logic diagram for the JK flip-flop converted from the SR flip-flop. Then the next state equation for the SR flip-flop will become the next state equation for the JK flipflop as: � S � RQ(t ) � ��QJ � (QK )Q �� Q(t � 1) SR � � � ��� � SR � 0 � ��QJ .QK � 0 �� � QJ � (Q � K )Q � QJ � K Q � Q(t � 1) JK 3. Fig.7.3.2: JK flip-flop using SR flip-flop. SR flip-flop to T flip-flop: Conversion table P.S Q(t) 0 0 1 1 Flip flop I/Ps T 0 1 0 1 N.S Q(t+1) 0 1 1 0 Required I/Ps S 0 1 X 0 R X 0 0 1 Sequential Circuits-Flip-Flops [169] From the above conversion table, the k-map simplification of the Boolean expressions for S and R inputs are: S � QT , R = QT. The SR flip-flop can be converted into a T flip-flop by giving the value of S and R in the SR flip-flop. Fig.7.3.3 shows the logic diagram for the T flip-flop converted from an SR flip-flop and two AND gates. The next state equation for SR flip-flop will become the next state equation for the T flip-flop as: � S + R Q � t �� Q �t +1� SR = � � � QT � �QT � � SR=0 � � QT � �Q � T � Q �T �Q � QT � QT � Q�t � 1� T 4. Fig.7.3.3: T flip-flop using SR flip-flop. D flip-flop to SR flip-flop: Conversion table P.S Q(t) 0 0 0 0 1 1 1 1 Flip flop I/Ps S R 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 N.S Q(t+1) 0 0 1 X 1 0 1 X Required I/P’s D 0 0 1 X 1 0 1 X From the above conversion table, the k-map simplification of the Boolean expressions for D input is D � S � RQ � t � . The D flip-flop can be converted into SR flip-flop by giving the value of D in the D flip-flop. Fig.7.3.4 shows the logic diagram for D flip-flop converted from the SR flip-flop. The next state equation for D flip-flop will become the next state equation for the SR flip-flop. [170] Experiments in Digital Electronics 1 S 2 3 7432 D Q CLK 1 R 5. 2 04 4 5 7408 6 Q Fig .7.3.4: SR flip-flop using D flip-flop. D flip-flop to JK flip-flop: Conversion table P.S Q(t) 0 0 0 0 1 1 1 1 Flip flop I/Ps J K 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 N.S Q(t+1) 0 0 1 1 1 0 1 0 Required I/P’s D 0 0 1 1 1 0 1 0 From the above conversion table, the k-map simplification of the Boolean expressions for D input is: D � QJ � Q K .The D flip-flop can be converted into a JK flip-flop by giving the value of D in the D flip-flop. Fig.7.3.5 shows the logic diagram for D flip-flop converted from the JK flip-flop. The next state equation for D flip-flop will become the next state equation for the JK flip-flop as: Q(t � 1) D � D � QJ � Q K � Q(t � 1) JK 1 2 J 00 3 PRE 9 10 K 1 04 2 4 00 6 00 8 2 D Q5 CLK 3 Q6 5 CLR Fig.7.3.5: JK flip-flop using D flip-flop.. Sequential Circuits-Flip-Flops [171] 6. D flip-flop to T flip-flop: Conversion table P.S Q(t) 0 0 1 1 Flip-flop I/P’s T 0 1 0 1 N.S Q(t+1) 0 1 1 0 Required I/P’s D 0 1 1 0 From the above conversion table, the k-map simplification of the Boolean expressions for D input is: D � QT � QT .The D flip-flop can be converted into a T flip-flop by giving the value of D in the D flip-flop. Fig.7.3.6 shows the logic diagram for D flip-flop converted from T flip-flop. The next state equation for D flip-flop will become the next state equation for the T flip-flop as: Q(t � 1) D � D � QT � QT � Q(t � 1) T Fig.7.3.6: T flip-flop using D flip-flop.. 7. JK flip-flop to SR flip-flop: Conversion table: P.S Q(t) 0 0 0 0 1 1 1 1 Flip-flop I/Ps S R 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 N.S Q(t+1) 0 0 1 X 1 0 1 X Required I/P’s J K 0 X 0 X 1 X X X X 0 X 1 X 0 X X [172] Experiments in Digital Electronics From the above conversion table, the k-map simplification of the Boolean expressions for S and R inputs are: J � S , K � R .The JK flip-flop can be converted into a SR flip-flop by giving the value of J and K in the SR flip-flop. Fig.7.3.7 shows the logic diagram for the JK flip-flop converted from the SR flip-flop. The next state equation for JK flip-flop will become the next state equation for the SR flip-flop as: Q(t � 1) JK � QJ � KQ � QS � RQ � QS � RQ( S � 1) � QS � RQS � RQ � QS � RQS � RQS � RQ {SR � 0} � QS � RQ � QS ( R � R ) � QS � QS � RQ � S � RQ � Q(t � 1) SR S Q CLK Q R 8. Fig.7.3.7: SR flip-flop using JK flip-flop.. JK flip-flop to D flip-flop: Conversion table P.S Q(t) 0 0 1 1 N.S D 0 1 0 1 N.S Q(t+1) 0 1 0 1 Required I/P’s J K 0 X 1 X X 1 X 0 From the above conversion table, the k-map simplification of the Boolean expressions for S and R inputs are: J � D , K � D .The JK flip-flop can be converted into a D flip-flop by giving the value of J and K in the JK flip-flop. Fig.7.3.8 shows the logic diagram for D flip-flop converted from JK flip-flop. The next state equation for JK flip-flop will become the next state equation for the D flip-flop as: Sequential Circuits-Flip-Flops [173] Q (t � 1) JK � QJ � Q K � QD � QD �D � Q (t � 1) D Fig.7.3.8: D flip-flop using JK flip-flop. 9. JK flip-flop to T flip-flop: Conversion table P.S Q(t) 0 0 1 1 N.S T 0 1 0 1 N.S Q(t+1) 0 1 1 0 Required I/P’s J K 0 X 1 X X 0 X 1 From the above conversion table, the k-map simplification of the Boolean expressions for J and K inputs are: J � T , K � T .The JK flip-flop can be converted into a T flip-flop by giving the value of J and K in the JK flip-flop. Fig.7.3.9 shows the logic diagram for T flip-flop converted from JK flip-flop. Then the next state equation for JK flip-flop will become the next state equation for the T flip-flop as: Q(t � 1) JK � QJ � Q K � QT � QT �T �Q � Q(t � 1) T Fig.7.3.9: T flip-flop using JK flip-flop. [174] Experiments in Digital Electronics 10. T flip-flop to SR flip-flop: Conversion table P.S Q(t) 0 0 0 0 1 1 1 1 Flip-flop I/Ps S R 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 N.S Q(t+1) 0 0 1 X 1 0 1 X Required I/P’s T 0 0 1 X 0 1 0 X From the above conversion table, the k-map simplification of the Boolean expressions for T input is: T � QS � QR .The T flip-flop can be converted into a SR flip-flop by giving the value of T in the T flip-flop. Fig.7.3.10 shows the logic diagram for SR flip-flop converted from T flip-flop. The next state equation for T flip-flop will become the next state equation for the SR flip-flop as: � Q (t � 1) T � QT � QT � Q (QS � QR ) � Q QS � QR � � � � QS � Q QR S Q � S R � QS � QR � QS R � QS � QR � QS R � QSR � QS (1 � R ) � QR (1 � S ) � QS � QR ( S � 1) � QS � QR � QRS � QRS � QS � QR � QS � � � S Q � Q � QR � S � QR � S � QR SR � 0 SR � Q (t � 1) SR 1 S 2 00 3 1 2 R 32 3 T Q Q Q Q CLK 4 00 6 5 Fig.7.3.10: SR flip-flop using T flip-flop. Sequential Circuits-Flip-Flops [175] 11. T flip-flop to D flip-flop: Conversion table: P.S Q(t) 0 0 1 1 Flip-flop I/Ps D 0 1 0 1 N.S Q(t+1) 0 1 0 1 Required I/P’s T 0 1 1 0 From the above conversion table, the k-map simplification of the Boolean expressions for D input is: T � QD � Q D � Q � D .The T flip-flop can be converted into D flip-flop by giving the value of T in the T flip-flop. Fig.7.3.11 shows the logic diagram for D flip-flop converted from the T flip-flop. The next state equation for T flip-flop will become the next state equation for the D flip-flop as: Q(t � 1) T � Q � T � Q � Q � D � 0 � D � D � Q(t � 1) D 1 D 2 86 3 T Q CLK Q Fig.7.3.11: D flip-flop using T flip-flop. 12. T flip-flop to JK flip-flop: Conversion table: P.S Q(t) 0 0 0 0 1 1 1 1 Flip-flop I/P J K 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 N.S Q(t+1) 0 0 1 1 1 0 1 0 Required I/P T 0 0 1 1 0 1 0 1 [176] Experiments in Digital Electronics From the above conversion table, the k-map simplification of the Boolean expressions for T input is: T � QJ � QK .The T flip-flop can be converted into a JK flip-flop by giving the value of T in the T flip-flop. Fig.7.3.12 shows the logic diagram for the JK flip-flop converted from the T flip-flop. The next state equation for T flipflop will become the next state equation for the JK flip-flop as: Q (t � 1) T � Q � T � Q � (Q J � QK ) � Q (QJ � QK ) � Q (QJ � QK ) � QJ � Q (QJ .QK ) � QJ � Q{(Q � J ).(Q � K )} � QJ � Q K � Q J K � Q J � Q K (1 � J ) � Q J � Q K � (Q (t � 1) JK 1 J 2 00 3 9 10 K 00 8 T Q CLK 4 00 6 Q 5 Fig.7.3.12: JK flip-flop using T flip-flop. Procedure: (1) Insert ICs on the power project board. Connect the power supply to the proper pin of the chip. (2) Construct each logic circuit on the breadboard. (3) Connect the LEDs to the output with a current limiting resistor. (4) Connect the inputs of the gate to the switch provided on the trainer/ board or hook them up to the +5V supply (logic 1) or ground (logic 0) as required. (5) Vary the inputs and observe next state output through LED output. Sequential Circuits-Flip-Flops [177] (6) Prepare the truth table. Observation Table: Inputs (I/Ps) S 0 0 1 1 R 0 1 0 1 Next state (N.S) Q(t+1) Inputs (I/Ps) J 0 0 1 1 K 0 1 0 1 Next state (N.S) Q(t+1) I/P D 0 1 Next state (N.S) Q(t+1) 0 1 Result: Verified the all converted flip-flops. Precautions: 1. Check all ICs and gates before making use of them. 2. Check power supplies of the power project board. 3. Do not leave an input floating. I/P T 0 1 Next state (N.S) Q(t+1) [178] 8. Sequential Circuits-Registers EXPERIMENT-8.1 Object: To study and verify the operation of the 4-bit shift right register using D-FlipFlops. Equipment/Components required: 1. Equipment: Power Project board, Edge triggered generator, and digital multimeter. 2. Components: ICs: Two 7474 (Dual D-type edge-triggered flip-flop), two 7400. Diode: Four LED Miscellaneous: Four Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: A register is a device capable of storing a number of bits. We know that a flip-flop has a memory element. Thus, flip-flop can be connected together to form a register. A shift register consists of a group of flip-flops connected so that each flipflop transfers its bit of data to the next flip-flop of the register when a clock pulse arrives. Data may have to be shifted left or shifted right. We have shifted left and shifted right registers. The data can be in serial form or parallel form. Thus we can have four types of shift registers: 1. Serial in- Serial out: The data is loaded into and read from the shift register serially. Fig.8.1.1 shows the circuit of a 4-bit serial in-serial out (SISO) shifts right register using four D flip-flops. The Q outputs of one flip-flop are connected to the D input of the next flip-flop. Thus, the inputs to second, third and fourth flip-flop are connected by their preceding flip-flops output. The data in each flip-flop is shifted to the next flip-flop on the arrival of a positive edge of clock pulse. Since it is a 4-bit register, 4 clock pulses are required to shift the data through this register. Sequential Circuits-Registers [179] � VCC � VCC 14 logic ‘1’ 4 2 D PRE1 5 12 D Q1 1 2 (SI) CLK 11 CLK1 3 1 logic ‘1’ PRE2 9 Q2 2D 3 3 2 Q1 6 PRE3 Q3 5 12 D PRE4 Q4 4 11 CLK3 3 Q2 8 CLR2 9 CLK4 4 Q3 6 Q4 CLR3 13 1 logic ‘1’ 10 4 CLK2 CLR1 CLR1 14 logic ‘1’ 10 CLR4 1 8 13 GND GND Fig.8.1.1: SISO shifts right register. 2. Serial in-Parallel out: The data is loaded into the register serially but read in parallel mode, i.e., data is available from all bits simultaneously. Fig.8.1.2 shows the circuit of a 4-bit serial in-parallel out (SIPO) shifts right register using four D flip-flops. The Q outputs of one flip-flop are connected to the D input of the next flipflop. Thus, the inputs to second, to the third and fourth flip-flop are connected by their preceding flip-flops output. The data in each flip-flop is shifted to the next flip-flop on the arrival of a positive edge of the clock pulse. Output terminals and data are available at all of them together. Since it is a 4-bit register, after 4 clock pulses we see all the data is available in the outputs of this register. PRE logic '1' � VCC � VCC 14 14 10 4 (SI) CLK 2 D 1 3 PRE1 5 12 D Q1 2 11 CLK1 1 PRE2 Q2 CLR1 9 2 D 3 3 CLK2 2 Q1 6 PRE3 Q3 12 5 11 CLK3 3 Q2 8 CLR2 Q3 6 CLR3 13 1 10 4 PRE4 D4 Q4 CLK4 4 Q4 CLR4 1 9 8 13 GND GND CLR logic '1' Q1 Q2 Q3 (Data parallel out) Fig.8.1.2: SIPO shifts right register. Q4 [180] Experiments in Digital Electronics 3. Parallel in- Serial out: The data is loaded in parallel form and read serially. Fig.8.1.3 shows the circuit of a 4-bit parallel in-serial out (PISO) shifts right with four bits. It uses D flip-flops and four data input lines: A (LSB), B, C, and D. Moreover, it has a Shift Load input which allows four bits of data to be entered into the register simultaneously. When control input is low, the output of gates G1, G4, G7 will be the complement of the input data � i.e. � B,C,D � , while the output of gates G2, G5, G8 will remain in the logic '1' state. The output of gates G1G2, G4G5 and G7G8 are connected to the input of gate G3 G6 G9 . Hence, the output of gates G3 G6 G9 will be the complement � � of the input data i.e. � B,C,D � B,C,D . In this mannar, data is loaded into the input of each flip-flop. Similarly, when the control input is high, data is shifted from left to right. A (LSB) C B D (MSB) Shift Load 1 2 00 9 10 00 4 5 00 � VCC 12 3 13 00 5 00 logic ‘1’ 14 logic ‘1’ 2 D PRE1 5 Q1 1 3 2 00 6 11 CLK1 1 D2 Q2 CLR1 1 13 00 � VCC 3 logic ‘1’ 9 2 D 3 logic ‘1’ 10 PRE3 Q3 PRE4 5 Q2 8 CLR2 3 Q3 6 CLR3 1 13 12 11 3 CLK3 2 2 00 11 4 CLK2 Q1 6 1 12 14 PRE2 12 8 3 10 4 CLK 1 4 6 9 10 00 11 8 GND D4 Q4 9 CLK4 4 Q4 CLR4 8 13 GND CLR logic '1' Fig.8.1.3: PISO shifts right register. 4. Parallel in-Parallel out: The data is loaded in parallel and read from the register in parallel, i.e., all bits are loaded simultaneously and read simultaneously. Fig.8.1.4 shows the circuit of a 4-bit parallel in-parallel out (PIPO) shifts right register using four D flip-flops. The data in each flip-flop is shifted to the output after the arrival of a positive edge of clock pulse. Output terminals and data are available at all of them together. A, B, C, and D are the parallel data bits and Q1, Q2, Q3, and Q4 are parallel data outputs. After one clock pulse, all the input data is available in the outputs. Sequential Circuits-Registers [181] Parallel data in (PI) A C B � VCC D � VCC 14 10 4 CLK 2 D PRE1 5 Q1 1 12 3 11 CLK1 1 PRE2 D2 Q2 Q1 6 CLR1 2 3 D3 Q2 8 PRE4 Q3 11 Q3 6 CLR3 13 Q4 9 CLK4 4 Q4 8 CLR4 1 13 GND Q2 Q1 D4 5 CLK3 3 CLR2 1 PRE / CLR �logic '1' � PRE3 9 CLK2 2 10 4 Q3 GND Q4 (Data parallel out) Fig.8.1.4: PIPO shifts right register. Procedure: (1) (2) (3) (4) (5) (6) Insert the IC in the proper place on the power project board. Connect the circuit as shown in the above figures. Connect LED to the output through a current limiting resistor. Give input to the flip-flop and start the clock generator. Observe LED output. Verify that on application of one clock pulse, the data is transferred by one bit to the right. Observation Table: 1. SISO shift right register. Inputs Data Output clock Q1 Q2 Q3 Q4 [182] Experiments in Digital Electronics 2. SIPO shift right register. Inputs Data 3. Output clock Q1 Q2 4. Shift Load Output clock Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q3 PIPO shift right register. Inputs Data Q4 PISO shift right register. Inputs Data Q3 Shift Load Output clock Result: Verified the 4-bit shift right registers using D-Flip-Flops. Precautions: 1. Check all the flip-flops before putting them to use. 2. Check the power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-8.2 Object: To study and verify the operation of the 4-bit shift right register using registers IC's. Equipment/Components required: 1. Equipment: Power Project board and digital multimeter. Sequential Circuits-Registers [183] 2. Components: ICs: One 7491 (8-bit serial shift register, totem pole output), One 74164 (8-bit shift register with parallel outputs, totem pole output), One 74165 (8-bit shift register with parallel inputs, totem pole output), One 74195 (4-bit universal shift register), Diode: four LEDs. Miscellaneous: Four Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: A register is a group of flip-flops connected so that each flip-flop transfers its bit of data to the next flip-flop of the register when a clock pulse arrives. Data may have to be shifted left or shifted right. Thus, we have shifted left and shifted right registers. The data can be in serial form or parallel form. Thus, we can have four types of shift register ICs. 1. Serial in-Serial out: IC 7491 is an 8-bit serial shift register with totem pole output. It uses eight clocked SR flip-flops. Thus, it is an 8-bit register; designated as SRG 8 (shift register 8 bits). Serial data and input control are gated through inputs A & B. Fig.8.2.1 shows the function table and pin diagram of 7491. Input tn Output tn+8 A B Q 1 0 X 1 X 0 1 0 0 Q 0 1 1 (a) (b) t n : Time before clock pulse, t n�8 : Time after eight clock pulse X : Don't care Fig.8.2.1: IC type 7491 (a) function table (b) pin diagram 2. Serial in-Parallel out: IC 74164 is 8-bit shift register with parallel totem pole output. It has two serial inputs, A and B, an active low reset (R) and parallel outputs QA to QH. It uses SR flipflops.Fig.8.2.2 shows the function table and pin diagram of IC 74164. [184] Experiments in Digital Electronics Input tn R 0 1 1 1 1 T X 0 ? ? ? Output tn+1 A X X 1 0 X B X X 1 X 0 QA 0 QB ….QH 0…0 No change 1 Shift 0 Shift 0 Shift (a) R = Reset input, T = clock input, A B = enable input (b) QA , QB ...QH � data outputs,QA � LSB. Fig.8.2.2: IC type 74164 (a) function table (b) pin diagram 3. Parallel in-Serial out: IC 74165 is 8-bit shift register with parallel inputs, totem pole output, with (S/L) terminal. A, B, C, D, E, F, G, H are the terminals for 8-bit data input. An additional terminal SE is provided for serial data input. The clock can be inhibited any time by a high on its CLK INH input. The serial data output is Q H and its Shift Load complement is Q H . Fig.8.2.3 shows the function table and pin diagram of IC 74165. Input Intern Output S/L FE T A…H SE QA QB ...QG QH � SQ 0 1 1 1 X 0 1 0 X 0 X ↑ X X X X X X A SE B…G H No change No change Shift right (a) FE = Enable input, SE = serial input on shift register, (b) SQ = serial output on shift register, Fig.8.2.3: IC 74165 (a) function table (b) pin diagram 4. Parallel in-Parallel out: IC 74195 is a 4-bit universal shift register with a Shift Load (S/L) terminal. When Sequential Circuits-Registers [185] S/L input is low, the data on parallel lines A, B, C, and D can be entered synchronously on the positive edge of the clock pulse. When S/L input is high, then stored data shifts to the right (i.e. QA to QD) synchronously with the clock. This IC can also be used for serial input-serial output. J and K are serial data inputs to the first stage of IC. A QD can be used for serial data output. The active low clear is asynchronous. Fig.9.2.4 shows the function table and pin diagram of IC 74195. Input R S/L T 1 1 0 1 1 ↑ 0 X X 1 0 ↑ 1 1 ↑ Output J X 0 X X 0 K QA QB QC QD X No change in output 1 No change in output X Asynchronous clear X Load input data 0 Shift from QA towards QD, QA = 0 1 1 ↑ 1 1 Shift from QA towards QD, QA = 0 1 1 ↑ 1 0 Q n Shift right (a) (b) Fig.8.2.4: IC 74195 (a) function table (b) pin diagram Procedure: (1) (2) (3) (4) (5) (6) Insert the IC in the proper place on the power project board. Connect the circuit as shown in the above figures. Connect LED to the output through a current limiting resistor. Give input to the flip-flop and start the clock generator. Observe LED output. Verify that on application of one clock pulse, the data is transferred by one bit to the right or left. Observation Table: 1. SISO shift right register. Inputs Data Outputs clock QA QB QC QD [186] Experiments in Digital Electronics 2. SIPO shift right register. Inputs Data 3. Outputs clock QA QB 4. Shift Load Outputs clock QA QB QA QB QC QD QC QD PIPO shift right register. Inputs Data QD PISO shift right register. Inputs Data QC Shift Load Outputs clock Result: Verified the 4-bit shift right registers using register IC's. Precautions: 1. Check all the flip-flops before putting them to use. 2. Check the power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-8.3 Object: To study and verify the function table operation of the 4-bit shift right register using registers IC. Equipment/Components required: 1. Equipment: Power Project board and digital multimeter. Sequential Circuits-Registers [187] 2. Components: ICs: One 7491 (8-bit serial shift register, totem pole output), One 74164 (8-bit shift register with parallel outputs, totem pole output), One 74165 (8-bit shift register with parallel inputs, totem pole output), One 74195 (4-bit universal shift register), Diode: Four LED Miscellaneous: Four Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: A register is a group of flip-flops connected so that each flip-flop transfers its bit of data to the next flip-flop of the register when a clock pulse arrives. Data may have to be shifted left or shifted right. Thus, we have shifted left and shifted right registers. The data can be in serial form or parallel form. Thus, we can have four types of shift register ICs. 1. Serial in-Serial out: IC 7491 is an 8-bit serial shift register, totem pole output. It uses eight clocked SR flip-flops. Thus, it is an 8-bit register; designated as SRG 8 (shift register 8 bits). A and B are two input lines. Serial data input and control input are gated through there inputs. Fig.8.2.1 shows the function table and pin diagram of the 7491. 2. Serial in-Parallel out: IC 74164 is an 8-bit shift register with a parallel totem pole output. It has two serial inputs, A and B, active low reset (R) and parallel outputs QA to QH. It uses SR flip-flops.Fig.8.2.2 shows the function table and pin diagram of IC 74164. 3. Parallel in-Serial out: IC 74165 is an 8-bit shift register with parallel inputs, a totem pole output, with a Shift Load (S/L) terminal. A, B, C, D, E, F, G, H are the terminals for 8-bit data input. An additional terminal SE is provided for serial data input. The clock can be inhibited at any time by a high on its CLKINH input. The serial data output is QH and its complement is Q H . Fig.8.2.3 shows the function table and pin diagram of IC 74165. 4. Parallel in-Parallel out: IC 74195 is a 4-bit universal shift register, with (S/L) terminal. When S/L input is low, the data on parallel lines A, B, C, and D can be entered synchronously on the positive edge of the clock pulse. When S/L input is high, then stored data shifts to the right (i.e. QA to QD) synchronously with clock. This IC can also be used for serial input-serial output. J and are serial data inputs to the first stage of IC. The QD can be used for serial data output. The active low clear is asynchronous. Fig.8.2.4 shows the function table and pin diagram of IC 74195. [188] Experiments in Digital Electronics Procedure: (1) Insert the registered IC in the proper place on the power project board. (2) Connect LED to the output through a current limiting resistor. (3) Give input to register and start the clock generator. (4) Observe LED output. (5) Verify that on application of one clock pulse, the data is transferred by one bit to the right or left. Observation Table: 1. Serial in- Serial out: IC type 7491 Output tn+8 Input tn 2. A B 1 0 X 1 X 0 Q Q Serial in- Parallel out: IC type 74164. Input tn R 0 1 1 1 1 3. T X 0 ↑ ↑ ↑ A X X 1 0 X Output tn+1 B X X 1 X 0 QA QB….QH Parallel in- Serial out: IC type 74165 Input Intern Output S/L FE T A…H SE QA QB...QG QH = SQ 0 X X X 1 0 0 X X 1 1 X X X 1 0 ↑ X Sequential Circuits-Registers [189] 4. Parallel in- Parallel out: IC type 74195. Input R S/L T 1 1 0 1 1 ↑ 0 X X 1 0 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ Output J X 0 X X 0 1 1 K QA X 1 X X 0 1 0 QB QC QD Result: Verified the 4-bit shift registers using ICs. Precautions: 1. Be sure about the IC used in the circuits and confirm about the proper pin numbers. 2. Check the power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-8.4 Object: To study and verify the operation of universal shift register IC. Equipment/Components required: 1. Equipment: Power Project board and digital multimeter. 2. Components: ICs: One 74194 (4-bit directional shift register),. Diode: Four LED Miscellaneous: Four Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: A universal shift register can shift data in both directions, i.e. to the left as well as the right .The logic gates are arranged in such a way that data bits can be transferred from one stage to the next in either direction depending on control line input. A universal shift register can be constructed from flip-flops. It is also available in IC form. IC 74194 is a 4-bit universal shift register. Fig.8.4.1 shows its symbol and pin connections. A, B, C, and D are inputs. QA, QB, QC, and QD are the outputs. Parallel loading is achieved by applying 4-bits of data simultaneously to inputs A, B, C, and D and high to S0 and S1 inputs at positive edge of the clock Parallel data is loaded into the register. Experiments in Digital Electronics [190] When S0 is high and S1 is low, the shift right operation occurs at positive edge of the clock. In this mode, serial data can be entered at SR SER (shift right serial input). When S0 is low and S1 is high, shift left operation occurs at positive edge of the clock. In this mode, serial data can be entered at shift left serial input (SL SER). Input Output R S0 S1 T SEI SEr QA QB QC QD 1 0 0 X X X No change No change 1 X X 0 X X 0 X X X X X 0 0 0 0 1 1 1 ↑ X X A B C D 1 0 1 ↑ X 1 1 shift right shift right 1 0 1 ↑ X 0 0 1 1 0 ↑ 1 X shift left 1 shift left 0 1 1 0 ↑ 0 X SEI= serial input for shift left, SER = serial input for shift right S0, S1= mode select inputs, A, B, C, and D inputs on shift registers (a) (b) Fig.8.4.1: IC 74194 (a) function table (b) pin configurations Procedure: (1) Insert IC 74194 in the proper place on the power project board. Connect LEDs to outputs QA, QB, QC, and QD through a current limiting resistor. (2) Give input at SR SER. Set S0 = 1 and S1 = 0.observe LED output with the application of each clock pulse. Sequential Circuits-Registers [191] (3) Give input at SL SER. Set S0 = 0 and S1=1. Observe LED output with the application of each clock pulse. (4) Give input at A, B, C, and D. Set SR SER=0 and SL SER =0. Set S0 = 1 and S1 = 1.observe LEDs output with the application of each clock pulse. Change S1 = 0. Observe LEDs output. Verify that shift right operation in parallel loading is being achieved. Set S0 = 0 and S1 = 1. Observe LED output. Verify that shift left operation in parallel loading is being achieved. (5) Prepare a truth table in each of the steps. Observation Table: R 1 1 0 1 1 1 1 1 S0 0 X X 1 0 0 1 1 S1 0 X X 1 1 1 0 0 Input T SEI X X 0 X X X ↑ X ↑ X ↑ X ↑ 1 ↑ 0 SEr X X X X 1 0 X X Output QA QB QC QD Result: Verified the operation of the universal shift register IC. Precautions: 1. Check power supplies of the power project board. 2. Do not leave an input floating. EXPERIMENT-8.5 Object: To study and verify the operation of 4-bit Ring counter and Johnson counter using IC 74195. Equipment/Components required: 1. Equipment: Power Project board and digital multimeter. 2. Components: ICs: One 74195 (4-bit parallel access shift register). Diode: Four LEDs. Miscellaneous: Four Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Experiments in Digital Electronics [192] Brief theory: A counter can be designed to generate any desired sequence of states. Counters can also be constructed by means of shift registers. 1. Ring Counter: A ring counter is a circular shift register with the signal from the serial output QD going into the serial input. Connect the J and K input together to form a serial input. Use the load condition to preset the ring counter to an initial value of 1000. Rotate the single bit with the shift condition and check the state of the register after each clock pulse. Fig.8.2.4 shows the function table and pin diagram of IC 74195. Fig.8.4.1 shows the IC 74195 used as a ring counter. Fig.8.5.1: IC 74195 as a ring counter 2. Johnson counter: It's also known as switch-tail ring counter uses the complement output of QD Sequential Circuits-Registers [193] for the serial input. Preset the switch-tail ring counter to 0000 and predict the sequence of states that will result from shifting. Verify your prediction by observing the state sequence after each shift. Fig.8.5.2 shows the IC 74195 used as a Johnson counter. Fig.8.5.2: IC 74195 as a Johnson counter. Procedure: (1) Insert the registered IC on the proper place on the power project board. (2) Connect LED to the output through a current limiting resistor. (3) Give input to register and start the clock generator. (4) Observe LED output. (5) Verify that on application of one clock pulse, the data is transferred by one bit to the right. [194] Experiments in Digital Electronics Observation Table: 1. Ring Counter Input R S/L T 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 2. J 1 1 1 1 1 1 1 1 Output K 1 1 1 1 1 1 1 1 QA QB QC QD QB QC QD Johnson Counter Inputs R S/L T 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ J 1 1 1 1 1 1 1 1 Output K 1 1 1 1 1 1 1 1 QA Result: Verified the operation of the Ring and Johnson counter. Precautions: 1. Check all the flip-flops. 2. Check the power supplies of the power project board. 3. Do not leave an input floating. Sequential Circuits-Registers [195] EXPERIMENT-8.6 Object: Design, construct, and verify a 4-bit serial adder. Equipment/Components required: 1. Equipment: Power Project board and digital multimeter. 2. Components: ICs: One 7474 (Dual D flip-flop), One 7476 (Dual JK master slave flipflop), One 7491 (8-bit shift register), One 7408 (Quadruple 2-input AND gates),One 7402 (Quadruple 2-input NOR gates), One 7486 ( Quadruple 2-input EX-OR gates). Diode: Two LED Miscellaneous: Two Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: We can design and construct a four-bit serial adder using a sequential logic concept. The state table that specifies the sequential circuit is listed in Table 8.6.1. The present state of Q(t) is the present value of the carry. The present carry in Q(t) is added together with inputs X and Y to produce the sum bit in output S. The next state of Q is equal to the output carried. Note that the state table entries are identical to the entries in a full-adder truth table, except that the input carry is now the present state of Q (t) and the output carry is now the next state of Q (t+1). Table 8.6.1: State table for serial adder Present Inputs State Q(t) X Y 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Next State Q(t+1) 0 0 0 1 0 1 1 1 Output Flip-Flop Inputs ( using JK) S J K 0 0 X 1 0 X 1 0 X 0 1 X 1 X 1 0 X 0 0 X 0 1 X 0 Flip-Flop Inputs (using D) D 0 0 0 1 0 1 1 1 1. Design using JK flip-flop: If the JK flip-flop is used for Q, it is necessary to determine the values of inputs J and K by referring to the excitation table. This is done in the last two columns of table 8.6.1. The two flip-flop input equations and the output equation can be simplified by means of K -map. [196] Experiments in Digital Electronics J � XY K � XY � (X � Y) S � X �Y �Q Fig. 8.6.1 shows the serial adder circuit using J and K flip-flop and register. Shift Control SO SI SUM X Shift Register (1) 4 1 2 86 3 5 86 6 CLK Serial Input SO SI 1 Y Shift Register (2) 2 08 3 I Q CLK4 2 3 1 Q K CLR 4 5 02 08 6 logic ‘1’ Fig. 8.6.1: Serial adder circuit using J and K flip-flop. Design using D flip-flop: If D flip-flop is used for Q, it is necessary to determine the values of input D by referring to the excitation table. This is done in the last two column of table 8.6.1. The D flip-flop input equation and the out put equation can be simplified by means of K-map to D � XY � QY � QX S � X �Y �Q Fig. 8.6.2 shows the 4-bit serial adder circuit using D flip-flop, full adder and 4-bit shift right register. Sequential Circuits-Registers [197] Fig. 8.6.2: Serial adder circuit using D flip-flop. Procedure: (1) Insert the ICs on proper place of power project board. (2) Connect LEDs to the output through a current limiting resistor. (3) Give input to the serial adder sequentially and observe LED output. Observation Table: S.No. C in (input carry) Inputs X (Addend) Y (Augends) Outputs 0 1 2 3 4 5 6 7 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Cout (Carry) Result: Verified 4-bit serial adder circuit. Precautions: 1. Check all the gates inside the ICs before using them. 2. Check power supplies of the power project board. 3. Do not leave an input floating. S (Sum) [198] 9. Sequential Circuits-Counters EXPERIMENT-9.1 Object: To design and verify the operation of 4-bit asynchronous binary counter using IC 7473 (JK Flip-Flops). Equipment/Components required: 1. Equipment: Power Project board and Digital multimeter. 2. Components: ICs: Two 7473 (Dual JK master-slave flip-flop). Diode: Four LED Miscellaneous: Four Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: A counter is probably one of the most useful and versatile subsystems in a digital system. A counter consists of flip-flops. A counter driven by a clock can be used to count the number of clock cycles. The function of a counter is to count the number of clock pulses. Since the clock pulses occur at known intervals, the counter can be used as an instrument for measuring time and, therefore, period or frequency. There are basically two different types of counters-synchronous and asynchronous. An asynchronous binary counter is also called a serial or ripple counter. The ripple counter is simple and straightforward in operation and its construction requires a minimum amount of hardware. It does, however, have a speed limit. Each flip-flop is triggered by the previous flip-flop, and thus the counter has a cumulative settling time. Counters such as these are called serial or asynchronous. Fig.9.1.1 shows the circuit of a 4-bit ripple counter consisting of four negative edge triggered JK flip-flops. QA is the least significant bit and QD is the most significant bit. The flip-flops are connected in a series. The QA output is connected to clock terminal of the second flip-flop. The QB output is connected to the clock of the third flip-flop and so on. It is known as a ripple counter because the carry moves through the flip-flops like a ripple in water. Sequential Circuits-Counters [199] QA (LSB) QD (MSB) QC QB (+5V) 14 1 CLK QA JA 12 7473-1 7 JB QA 13 KA 2 9 QC JC 1 5 7473-1 1 3 QB KB QB 8 6 1 3 JD QD 9 5 7473-2 2 7 QC 13 KC 2 7473-2 2 QD KD 8 6 CLR QA 7473 : Pin 4 = VCC = +5V Pin 11 = GND = 0 V. QB QC QD Fig. 9.1.1: four bit asynchronous (ripple) counter Initially, the clear is made low and all flip-flops are reset giving an output of 0000. When the clear becomes high, the counter is ready to start. As LSB receives its clock pulse, its output changes from 0 to 1 and its total output is 0001. When the second clock pulse arrives, QA resets and carries (i.e., QA goes from 1 to 0 and the second flip-flop will receive clock input). Now the output is 0010. The third clock pulse changes QA to 1, giving a total output of 0011. The fourth clock pulse causes QA to reset and QB also resets and carries on, giving a total output of 0100 and the process goes on. Table 9.1.1 shows the action of counting. The number of output states of a counter is known as the modulus. A ripple counter with four flip-flops can count from 0 to 15 and is, therefore, known as a mod-16 counter, while one with six flip-flops can count from 0 to 63 and is a mod-64 counter, and so on. [200] Experiments in Digital Electronics Table 9.1.1: four bit ripple counter Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 QD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 QC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 QB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 QA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Ripple counters are simple to fabricate but have the problem that the carry has to propagate through a number of flip-flops. The delay times of all the flip-flops are added. Therefore, they are very slow for some applications. Procedure: (1) Insert IC in the proper place on the power project board and construct the circuit as shown in Fig.9.1.1 (2) Initially asynchronously clear the outputs of all flip-flops to 0000. (3) Apply clock input to first flip-flop. (4) Observe the LED outputs. (5) Verify the truth table. Sequential Circuits-Counters [201] Observation Table: Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK QD QC QB QA � � � � � � � � � � � � � � � � Result: Verified the operation of a 4-bit asynchronous binary counter. Precautions: 1. Check all your flip-flops before putting them to use. 2. Check the power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-9.2 Object: To design and verify the operation of an asynchronous decade counter using IC 7473 (JK Flip-Flops). Equipment/Components required: 1. Equipment: Power Project board and digital multimeter. 2. Components: ICs: One 7473 (Dual JK master-slave flip-flop), One 7410 (three 3input NAND gates), Diode: Four LED [202] Experiments in Digital Electronics Miscellaneous: Four Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: A decade counter is also known as a mod-10 counter or BCD counter. It counts from 0 to 9. Thus, it requires 10 pulses to reset. It is used in frequency counters, digital voltmeters, wristwatches, etc. Design: To design an asynchronous (ripple) decade counter, total number of flip-flops is required as per the given formula: 2 n � N ( total number of count � 10) therefore n � 4 i.e., ‘n’ number of flip-flops. That means sixteen possible states, out of which ten are valid and the remaining six are invalid. The counter has ten stable states, 0000 through 1001, i.e., it counts from 0 to 9. The initial state is 0000 and after nine clock pulses it goes to 1001. After the ninth clock pulses, the counter goes to state 0000. Table 9.2.1 shows the sequence of asynchronous decade counters. Table 9.2.1: Sequence of decade counter Count 0 1 2 3 4 5 6 7 8 9 10 QD 0 0 0 0 0 0 0 0 1 1 0 QC 0 0 0 0 1 1 1 1 0 0 0 QB 0 0 1 1 0 0 1 1 0 0 0 QA 0 1 0 1 0 1 0 1 0 1 0 Reset 1 1 1 1 1 1 1 1 1 1 0 The circuit is shown in Fig. 9.2.1. It is seen that, in many respects, it is similar to a ripple counter. However, it skips 10 to 15 states. This is possible because just after nine clock pulses, it generates its own clear signal and reset to 0000. It uses four JK flip-flops and one NAND gate. Initially, low clear causes 0000, when clear is high; the counter is ready to start. It is seen that the inputs of NAND gates are QA and QD. The counter operates as usual while counting from 0 to 9. After ninth clock pulses, the output is 0000 i.e., both QA and QD are high when the clock is negative edge triggered. This forces the NAND gate output to be low, which in turn resets the counter and its output is 0000. Hence, output of the NAND gate goes high and the counter starts again. Sequential Circuits-Counters [203] QA(LSB) QB QD 1 QC 2 (+5V) 14 JA 1 CLK QA 12 7 QA KA 13 JC QC QD JD 7473-2 2 1 2 QB 8 3 12 9 5 7473-2 KB 2 7 7473-1 1 3 9 1 5 7473-1 QB JB 10 KC 6 QC 13 2 QD KD 8 6 CLR CLR = 0 : (clear the data) 7473 : VCC GND 7410 : VCC GND = 1: (operation mode) - Pin 4 Pin 11 Pin 14 Pin 7 Fig. 9.2.1: 4-bit asynchronous (ripple) decade counter, Procedure: (1) Insert IC in the proper place on the power project board and construct the circuit as shown in Fig.9.2.1 (2) Initially asynchronously clear the outputs of all flip-flops to 0000. (3) Apply clock input to first flip-flop. (4) Observe the LED outputs. (5) Verify the truth table. Observation: Truth table for 4-bit decade counter Clock pulse � � � � � � � � � � QD 0 0 0 0 0 0 0 0 1 1 QC 0 0 0 0 1 1 1 1 0 0 QB 0 0 1 1 0 0 1 1 0 0 QA 0 1 0 1 0 1 0 1 0 1 Count 0 1 2 3 4 5 6 7 8 9 [204] Experiments in Digital Electronics Result: Verified the operation of the asynchronous decade-counter. Precautions: 1. Check all your flip-flops before putting them to use. 2. Check power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-9.3 Object: To design and verify the operation of a 4-bit synchronous binary counter using JK Flip-Flops. Equipment/Components required: 1. Equipment: Power Project board and digital multimeter. 2. Components: ICs: One 7473 (Dual JK master-slave flip-flop), One 7408 (Quadruple 2-input AND gates). Diode: Four LED Miscellaneous: Four Resistor � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: In a synchronous counter, all the flip-flops are clocked together. A counter consists of flip-flops. A synchronous binary counter is also called a parallel counter. An increase in the speed of operation can be achieved by use of a parallel or synchronous counter. Here, every flip-flop is triggered by the clock (synchronism), and thus the settling time is simply equal to the delay time of a single flip-flop. The increase in speed is usually obtained at the price of increased hardware. Fig.9.3.1 shows the circuit of a 4-bit parallel counter consisting of four negative edge triggered JK flip-flops. Since all the flip-flops are clocked together, the delay time is less. The flip-flop corresponding to LSB has its input JK fed from voltage +Vcc. Therefore, it responds to each negative clock pulse. However, the other three flip-flops can respond to the negative clock pulse under certain conditions. The QA flip-flop toggles on negative clock edge only if QA is 1. The QB flip-flop toggles on negative clock edge only when QA and QB are high (due to presence of the AND circuit) and so on. A low clear signal resets the counter so that Q = 0000. When clear goes high, the counter is ready to start. The first negative clock edge sets QA to 1 so that Q = 0001. At second negative clock pulse QB and QA toggle and Q=0010. The third negative clock pulse increases the count by 1 so that Q = 0011. Sequential Circuits-Counters [205] The successive Q outputs are 0100, 0101 and so on up to 1111. The next clock edge resets the counter to 0000 and the cycle is repeated. More flip-flops can be added to increase the count. Q QB QA(LSB) 1 3 2 08 14 12 JA 1 QA 7 QB CLK 13 QA KA 5 08 6 JC 9 QC JD 7473-1 7473-2 2 1 QB 8 KB 2 3 QD 9 5 1 1 3 4 7 JB 5 7473-1 D QC 7473-2 2 QC KC 13 CLR = 0: Counter clear the F/Fs QD 8 KD 2 6 6 Power Pin Number = 1: Counter in operation 7473 : VCC GND 7408 : VCC GND - Pin 4 Pin 11 Pin 14 Pin 7 Fig. 9.3.1: four bit synchronous counter Design: To design a 4-bit synchronous counter: 1. Required number of flip-flops n = 4. 2. Fig. 9.3.2 shows the state /transition diagram for a 4-bit synchronous counter. It is a graphical means of depicting the sequence of the states through which the counter progresses. 0000 1111 0001 1110 0010 1101 0011 1100 0100 0101 1011 0110 1010 0111 1001 1000 Fig. 9.3.2: state /transition diagram [206] Experiments in Digital Electronics 3. Table 9.3.1 shows the excitation table. It lists the present state and next state and required excitation. Table 9.3.1: Excitation table Present state QD Q C QB QA 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 QD 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Next state QC Q B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 QA 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 JD 0 0 0 0 0 0 0 1 X X X X X X X X KD X X X X X X X X 0 0 0 0 0 0 0 1 Required excitation J C KC JB KB JA 0 X 0 X 1 0 X 1 X X 0 X X 0 1 1 X X 1 X X 0 0 X 1 X 0 1 X X X 0 X 0 1 X 1 X 1 X 0 X 0 X 1 0 X 1 X X 0 X X 0 1 1 X X 1 X X 0 0 X 1 X 0 1 X X X 0 X 0 1 X 1 X 1 X KA X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 Obtain the following minimal expression for the excitation of the flip-flops JA � KA � 1 J B � K B � QA J C � K C � QAQB J D � K D � QAQBQC Fig 9.3.1 shows a four bit synchronous counter. Initially, the clear is made low and all flip-flops are reset, giving an output of 0000. When the clear becomes high, the counter is ready to start. As LSB receives its clock pulse, its output changes from 0 to 1 and its total output 0001. When the second clock pulse arrives, QA resets and carries (i.e., QA goes from 1 to 0 and the second flip-flop will receive clock input). Now the output is 0010. The third clock pulse changes QA to 1, giving a total output 0011. The fourth clock pulse causes QA to reset and carry and QB also resets and carries, giving a total output of 0100 and the process goes on. Table 9.1.1 shows the action of counting. The number of output states of a counter is known as modulus. A synchronous counter with four flip-flops can count from 0 to 15 and is, therefore, known as a mod-16 counter, while one with six flip-flops can count from 0 to 63 and is a mod-64 counter, and so on. Sequential Circuits-Counters [207] Procedure: (1) Insert IC into proper place on power project board and construct the circuit as shown in Fig.9.3.1. (2) Initially, asynchronously clear the outputs of all flip-flops to 0000. (3) Apply clock input to all flip-flops. (4) Observe the LEDs outputs. (5) Verify the truth table Observation: Truth table for 4-bit synchronous binary counter S. No. Input CLK Flip Flops Output QD QC QB QA Decimal Value 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Result: Verified the synchronous binary counter. Precautions: 1. Check all your flip-flops before putting them to use. 2. Check the power supplies of the power project board. 3. Do not leave an input floating. EXPERIMENT-9.4 Object: To study and verify the counters using ICs. Equipment/Components required: 1. Equipment: Power Project board and digital multimeter. 2. Components: ICs: One 7490 (4-bit, ripple-type decade counter), 7492 (Divide by 12 counter), One 7493 (4-bit binary counter). [208] Experiments in Digital Electronics Diode: Four LED Miscellaneous: Four Resistors � 330 � � 0.25watt, Single core wire, Cutter and stripper Brief theory: Counters are available in a single IC package. The following are the common ICs used in the digital lab. 1. IC-7490 chip study: Fig.9.4.1 (a) shows the logic diagram and (b) the block diagram, (c) the pin diagram for the IC-74LS90, which is a 4-bit, ripple-type decade counter. The device consists of four master-slave flip-flops internally connected to provide a divide-bytwo section and a divide-by-five section. Each section has a separate clock input to initiate state changes of the counter on the high-to-low clock transition. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. (a) (b) Sequential Circuits-Counters [209] (c) 1 3 2 08 1 (+5V) CLK IN 5 VCC 14 CLKA CLKB 12 9 8 8 QA QB QC QD IC 7490 as Mod - 7 MR1 MR2 GND MS1 2 3 12 6 MS2 7 GND (d) (e) Fig.9.4.1: IC-74LS90 (a) logic diagram (b) block diagram (c) pin diagram (d) mod-7 counter (e) mod-10 counter [210] Experiments in Digital Electronics A gated NAND asynchronous master reset (MR1, MR2) is provided which overrides both clocks and reset all the flip flops. In addition, it provided a gated NAND asynchronous master set, (MS1, MS2). Since the output from the divide-by-two section is not internally connected to the succeeding stage, the device may be operated in various counting modes. In a BCD counter, the CLKB input must be externally connected to the QA output. The CLKA input receives the incoming count, producing a BCD count sequence. In a symmetrical biquinary divide-by-ten counter, the QC output must be connected externally to the CLKA input. The input count is then applied to the CLKA input and a divide-by ten square wave is obtained at the output. To operate as a divide-by-two and divide-by five counter, no external interconnection is required. The first flip-flop is used as a binary element for the divide-by-two function ( CLKA as input and QA as output). The CLKB input is used to obtain a divide-by-five operation. Table 9.4.1 shows the mode selection-function table and the BCD count sequence-function table for the IC-7490. Table 9.4.1: mode solution function table for IC-7490 Function table Reset/Set inputs Outputs MR1 MR2 MS1 MS2 QD Q C QB QA 1 1 0 1 1 X X X 1 X 0 X 0 X 0 0 X X X 0 0 X=Don’t care. X 0 1 1 X 0 X 0 0 0 0 0 0 0 0 1 0 0 1 Count Count Count Count Count Sequence Outputs Count 0 1 2 3 4 5 6 7 8 9 QD QC QB QA 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 Note: Output QA connected to CLKB input 2. IC-7492 chip study: Table 9.4.2 shows the logic function and cont sequence for IC-74LS92, is a 4bit, ripple-type divide by 12 counter. Sequential Circuits-Counters [211] Table 9.4.2: mode solution function table for IC-7492 Function table Inputs Outputs MR1 MR2 QD Q C QB 1 1 0 0 0 0 X Count X 0 Count Count 0 1 2 3 4 5 6 7 8 9 10 11 QA 0 Count Sequence Outputs QD QC QB 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 QA 0 1 0 1 0 1 0 1 0 1 0 1 Fig. 9.4.2 shows the pin configuration for IC-74LS92, is a 4-bit, ripple type divide by 12 counter. LED 1 (+5V) CLK IN 5 VCC 14 CLKA CLKB 12 9 8 11 QA QB QC QD IC 7492 as Mod - 12 MR1 MR2 GND 2 3 10 (a) MS1 6 MS2 7 GND [212] Experiments in Digital Electronics (b) (c) 1 (+5V) 5 V CC CLKB 12 11 9 8 Q A QB QC Q D IC 7492 as Mod - 8 counter CLK IN CLKA GND 10 MR1 6 MR2 7 GND (d) Fig. 9.4.2: IC74LS92 (a) mod-12 counter (b) logic diagram (c) pin diagram (d) mod-8 counter. Sequential Circuits-Counters [213] 3. IC-7493 chip study: Fig.9.4.1 (a) shows the logic diagram and (b) the pin diagram for the IC-74LS93, is a 4-bit, ripple counter. This device consists of a single flip-flop and a 3-bit asynchronous counter. This arrangement is for flexibility. It can be used as a divide by-2 device using only the single flip-flop, or it can be used as a modulus-8 counter using only the 3-bit counter portion. The device also provides gated reset inputs, MR1 and MR2. When both of these inputs are high, the counter is reset to the 0000 state by CLR . Additionally, the 7493A can be used as a 4-bit modulus-16 counter by connecting the QA output to the CLKB input. The device consists of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide-by-eight section. Each section has a separate clock input to initiate state changes of the counter on the high-to-low clock transition. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. (a) (b) Fig.9.4.3: IC-74LS93 (a) logic diagram and (b) pin diagram A gated NAND asynchronous master reset (MR1, MR2) is provided which overrides both clocks and resets all the flip flops. Since the output from the divide-bytwo section is not internally connected to the succeeding stages, the device may be operated in various counting modes. In a 4-bit ripple counter, the output QA must be connected externally to the input CLKB. The input count pulses are applied to the input CLKA. Simultaneously, divisions of 2, 4, 8, and 16 are performed on QA, QB, QC, and QD outputs as shown in the function Table 9.4.3. As a 3-bit ripple counter, the input count pulses are applied to the input. Simultaneous frequency division of 2, 4, Experiments in Digital Electronics [214] and 8 are available at the QB, QC, and QD outputs, respectively. Table 9.4.3 (a) shows the mode selection-function table and (b) the BCD count sequence-function table for the IC-7493. Table 9.4.3 : mode selection function table for IC-7493 Function table Count Sequence Reset Outputs Outputs Inputs Count MR1 MR2 Q D Q C Q B QA QD QC QB QA 1 1 0 0 0 0 0 0 0 0 0 0 1 Count 1 0 0 0 1 1 0 Count 2 0 0 1 0 0 0 Count 3 0 0 1 1 4 0 1 0 0 (a) 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 (b) Note: Output QA connected to input of clock pulse CLKB. . Procedure: (1) Insert IC in the proper place on the power project board and connect the circuit. (2) Initially reset the output (0000) by using asynchronous inputs.. (3) Using count operation in function table, apply clock pulses using clock generator. (4) Verify the operation by observing the LED output. Observation Table: Make different table for different IC as shown above. Result: Verified the counter sequence using IC. Precautions: 1. Check all the ICs before putting them to use. 2. Check the power supplies of the power project board. 3. Do not leave an input floating. [215] Appendix-A STANDARD GRAPHIC SYMBOLS The IEC (International Electro technical Commission) and the IEEE (Institute of Electrical and Electronics Engineers) have developed a system of logic symbols that show the relationship of each input to each output, without showing the internal circuitry. This standard has been approved by industry, government, and professional organizations and is consistent with international standards. The standard uses a rectangular-shapeed outline and a general symbol to represent each particular logic function. The rectangular-shape graphic symbol and the general symbol for gates are shown in Fig. A.1 to A.3. & A IN 1 A.B B A 2-output OR gate & A A Buffer 1 B 1 A 2-input AND gate A.B OUT A A+B B A 1 A A A �B NOT gate =1 Y =A B Y � A �B B B 2-input NAND gate =1 A 2-input NOR gate B 2-input Ex-OR gate 2-input Ex-NOR gate Fig.A.1 Rectangular-shape graphic symbol for gates (British-symbol) IN A Y=AB & 1 Y=A+B A 1 OUT Y=A B 2-input AND gate 2-output OR gate Y � AB A A 1 & B NOT gate Buffer A 2-input NOR gate 2-input NAND gate A Y � A �B =1 1 B Y � A � B=A B =1 B 2-input Ex-OR gate 2-input Ex-NOR gate Fig.A.2 : Rectangular-shape graphic symbol for gates (IEC symbol) [216] Experiments in Digital Electronics A A Y=A.B Y=A Y=A+B A B B 2-input AND gate 2-output OR gate Y�A Buffer Y � AB A Y � A �B A A B B 2-input NAND gate NOT gate A A Y � A �B B 2-input NOR gate Y =A B B 2-input Ex-OR gate 2-input Ex-NOR gate Fig. A.3: General symbol for gates (ANSI symbol) The standard graphic symbols for 4-bit parallel adders (IC 7483 and IC 74LS283) are shown in fig. A.4. 10 5 8 A 3 1 7 B S1 6 S2 12 2 S3 6 15 S4 SUM 11 4 A 9 3 13 IC 74LS283 15 4 S1 1 S2 13 S3 10 S4 11 16 Carry in SUM 2 B IC 7483 14 14 5 12 VCC GND Carry out Carry in 7 8 16 VCC GND 9 Carry out Fig.A.4: Rectangular-shape graphic symbol 4-bit parallel adder The standard graphic symbol for multiplexers are (IC 74151 and IC 74157) shown in fig, A.5. Appendix-A [217] 15 1 EN EN A B C D0 D1 D2 D3 D4 D5 D6 D7 Control (Select) MUX 1 11 MUX Control input 10 (Select input) 9 4 3 2 1 15 14 13 12 B1 2 3 A2 B2 5 6 A3 B3 11 10 A4 B4 14 13 A1 5 6 Y Y IC 74151 4 Quadrupla 2×1MUX 7 9 (8X1MUX) IC 74157 12 5 12 5 12 VCC GND VCC GND Y1 Y2 Y3 Y4 Fig.A.5: Graphic symbol for multiplexers Table A.1 gives the description of some general qualifying symbols used in digital electronic logic circuits. A general qualifying symbol defines the basic function performed by the device represented. Table A.1: General qualifying symbols. Symbol Description & AND function �1 OR function 1 Buffer or NOT function =1 Exclusive-OR function MUX Multiplixer DMUX Demultiplexer X/Y Coder, decoder or code converter [218] Experiments in Digital Electronics � Adder � Multiplier COMP Magnitude Comparator ALU Arithmetic Logic Unit SRG Shift Register CTR Counter RCTR Ripple Counter Table A.2 gives the list of qualifying symbols associated with input and output. Table A.2: Qualifying symbols associated with inputs and outputs Symbol Description Active-low input or output (IEC Symbol) Logic negative input or output (Active-low input or output) British Symbol Dynamic indicator input EN Enabel input Shift right Shift left Figure A.6 gives the standard graphic symbol for IC 74155 (Dual 1×4 DEMUX) Appendix-A [219] X/Y A B C EN 13 D0 3 D1 D2 D3 D4 1 15 2 D5 D6 IC 74155 D7 14 Fig.A.6: Standard graphic symbol for IC 74155 connected as a 3×8 decoder. Fig. A.7 gives the standard graphic symbol for D flip-flop Q D D CLK Control Q D latch D Q Q Positive-edge-triggered D Flip-flop Q CLK D Q CLK Q Negative-edge-triggered D Flip-flop Q Master-slave D Flip-flop Fig.A.7: Graphic symbol for D flip-flop [220] Experiments in Digital Electronics Fig. A.8 gives the standard graphic symbol for IC 7476 and 7474 with direct/ asynchronous set and reset. 2 PRE1 J1 4 CLK1 K1 CLR1 1 16 7 PRE2 14 Q1 15 Q1 CLK2 K2 1 3 J2 Q2 9 6 Q2 12 2 8 CLR2 7476 (Dual JK flip-flop) VCC (a) GND 4 PRE CLK 3 D 2 CLR 1 7474 5 Q 6 Q One-half 7474 D flip-flop (b) Fig. A.8: Graphic symbol for flip-flop with asynchronous inputs. Fig.A.9 gives the standard graphic symbol for a 4-bit register (74175 : Quad D-flip-flop) CLR 1 9 CLK D1 4 D2 5 D3 12 D4 13 74175 16 2 Q1 3 Q1 7 Q2 6 Q2 10 11 Q3 Q3 15 Q4 14 Q4 8 VCC GND Graphic symbol for a four-bit register Fig.A.9: Graphic symbol for a four-bit register. Appendix-A [221] Fig. A.10 gives the standard graphic symbol for the bi-directional shift register (IC 194) with parallel load. 1 SRG 4 9 Select/Control Inputs 10 CLR S0 S1 CLK Shift right serial input Parallel inputes A B C D Shift left serial input 11 2 3 IC type 74194 4 5 6 7 15 QA 14 QB 13 QC 12 QD 16 8 VCC GND Fig.A.10: Graphic symbol for bi-directional shift register with parallel load. Fig. A.11 gives the standard graphic symbol for a shift register (IC 74195) with parallel load. 1 9 CLR Shift Load Shift � Logic '1' Load � Logic '0' 10 (CLK) CLK J Parallel inputes SRG 4 K 2 3 A 4 B 5 C 6 D 7 74195 16 8 VCC GND 15 QA 14 QB 13 QC 12 QD 11 QD Fig.A.11: Graphic symbol for a shift register with parallel load [222] Experiments in Digital Electronics Fig. A.12 and A.13 represent the standard graphic symbols for ripple coumter (IC 7493) and 4-bit binary counter (IC 74161) with parallel load. MR1 2 & MR2 3 RCTR devide-by-two A 12 QA 9 QB 8 QC 11 QD devide-by-eight IC type 7493 B 5 10 VCC GND Fig.A.12: Graphic symbol for 4-bit ripple counter CLR 1 Load 9M1 CTR DIV 16 M2 ENT 10 ENP 7 2 data inputs CLK A 3 B 4 C 5 D 6 15 IC type 74161 15 QA 14 QB 13 QC 12 QD Outputs Fig. A.13: Graphic symbol for 4-bit binary counter with parallel load [223] Appendix-B CIRCUITS USED IN DIGITAL LABORATORIES Following circuits are used in digital electronics laboratories for performing the experiments. Fig. B.1 gives the circuit diagram of 5V DC power supply. TTL devices require an operating voltage of 5 V. It uses an IC-7805, a three-terminal regulator, and it is quite adequate to handle a load up to 1 amp. Bridge Rectifier 9 1 230 V AC IN 3 IC 7805 2 0 C1 2200 F 230 V primary 0-9 secondary 2A Transformer C2 0.22 F +5V DC OUT C3 0.22 F Fig.B.1: Regulated power supply (5V) for TTL devies Fig. B.2 and B.3 gives the circuit diagram for a bank of logic switches (Double pole single through). 1 2 3 4 (DPST Swich) GND (logic '0') = 0 Fig. B.2: Four logic switches [224] Experiments in Digital Electronics VS 1 2 3 4 5 1 00 00 6 3 2 04 4 04 VS Fig. B.3: Debounce switch Fig. B.4 and B.5 shows the circuit diagram of four logic monitors. The LED in the logic monitor begins to glow brightly as the voltage beings to rise at 2.4 V. They do not glow if the input voltage is below 2V. 180 1K BC108 Inputs 180 LED (Red) 1K BC108 10 F LED (Red) GND Fig. B.4: Logic monitor Appendix-B [225] Positive voltage 1K 1K 1K 1K Output 0 2 4 6 8 1 3 5 9 2 4 7 9 �4050: VDD is pin1 � �� GND is pin 8�� (7406) � � �7406: VCC is pin 14 � GND is pin 7�� �� (4050) Input 3 10K 5 10K 10 10K 6 10K Fig. B.5: 4-Buffered LEDs Fig B.6, B.7 and B.8 gives the circuit diagram for the clock pulse generator (555 Timer), positive and negative clock generator (555 Timer) and clock pulse generator using IC-72555. 10K 2 7 Trigger input 6 10 F 4 8 6LR VCC Trigger Discharge 555 Output Threshold 1 5 0.01 F GND Fig. B.6: 555 Timer circuit [226] Experiments in Digital Electronics VCC CLK (Negative) 1K Fine Frequency Adjustment 7 20K 1K 1� F 0.01� F 10 � F 0.1� F 8 (Discharge) 1 03 3 2 3 4 03 6 CLK (Positive) 5 555 2(Trigger) 5 6(Threshold) 1 0.01K 0.01� F GND Course Frequency Adjustment Fig. B.7: Positive and negative clock generator using 555 and 7403 IC (+5V) VCC 0.01 F RA 4 CLR 5k 8 5 6 + Compare 5k Trigger 1 v cc 3 R Q S Q - 5k 2 vcc 3 Upper Comparator + 3 Output Lower Comparator Compare 72555 Timer 7 Discharge RB 1 C GND Fig. B.8: Clock pulse generator using IC-72555 [227] Appendix-C BRIEF DESCRIPTION OF DIGITAL ICS Digital ICs are classified as: TTL (Transistor-transistor logic), ECL (Emittercoupled logic), MOS (Metal-oxide semiconductor), and CMOS (Complementary metal-oxide-semiconductor. TTL is popular among logic families. ECL is used only in systems requiring high-speed operation. MOS and CMOS are based on field-effect transistors. They are widely used in large-scale integrated circuits because of their high component density and relatively low power consumption. CMOS logic consumes far less power than MOS logic. There are various commercial integrated circuit chips available. TTL ICs are usually distinguished by numerical designations such as the 5400 and 7400 series. The former has a wide operating temperature range, suitable for military use, and the later has a narrower temperature range, suitable for industrial and laboratory use. Some of the standard absolute maximum ratings and specifications for the 74XX series logic family are given below: Table C.1: Characteristics of TTL Logic Families Su b F a m ily VC C GND T T L L o g ic V OH L ev el s V IH VOL V IL F req u en c y lo w cu rren t o u tp u t TTL M i n im u m circu i t o u tp u t d ri v e Hi gh cu rren t cu rren t o u tp u t TTL circu i t lo w cu rren t o u tp u t TTL circu i t Fan -o u t cap ab i li ty * Hi gh cu rren t o u tp u t TTL circu i t O p erat in g free -air te m p erat u re ran g e P a ra m ete rs S t o rag e T e m p e r at ure R an ge S ta n d a rd LS AL S S 5 V ±1 0 % 0 V o lt 2 .7 V o lt 2 .0 V o lt 0 .4 V o lt 0 .8 V o lt < 70M Hz AS 5 V± 5% 5 V ±5 % 5 V ±5 % 5 V± 10% < 35 M H z <4 0 M H z < 1 2 5 M Hz < 200M H z 16mA 20m A 8mA 48mA 24m A 24 /4 8m A 64 m A 4 8 /6 4 m A 40 20 20 50 50 120 60 6 0/120 160 1 2 0 /1 6 0 20mA 0 0 C to + 70 0 C - 65 0 C to + 15 0 0 C *Taking the number of LS-TTL load as an example Experiments in Digital Electronics [228] VOH: Minimum output voltage level a TTL device will provide for a high signal. VIH: Minimum input voltage level to be considered a high signal. VOL: Maximum output voltage level a device will provide for a low signal. VIL: Maximum input voltage level to still be considered a low signal. For each TTL IC, such as 7404, 74LS01, 74AS04, 74F04, 74ALS04, their pin arrangement and logic function are the same, but they have a significant difference in circuit speed and power consumption. below: 1. The brief descriptions of some TTL digital ICs used in this book are given 7400: Quad 2-input NAND Gates Brief Description: The 7400 is a 14-pin integrated circuit consisting of four 2-input NAND gates, each gate performing the logic NAND gate function. The remaining two pins are reserved for the power supply. These gates are useful for providing the fundamental functions of digital circuits. Features: � Propagation delay for each gate will be 10 ns. � The maximum toggle speed is 25 MHz. � Power utilization for each gate is 10 mW. � Independent 2-input NAND Gates : 4. � The output can be interfaced with TTL, NMOS, and CMOS. � The range of operating voltage will be large. Package: 14 pin D.I.L. / (14 pin FLAT) [229] Appendix-C Pin Configurations: Vc c I npu ts of G ate 4 14 13 12 11 10 9 8 1 2 3 4 5 6 7 O utput 2 G ND Inputs of G ate 1 O utput 1 Outp u t 4 In pu ts of Gate 3 Input s of G ate 2 Ou tpu t 3 Vcc: Supply Voltage; GND: Ground Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 2. 7401: Quad 2-input NAND Gates (open collector outputs) Brief Description: The 7401 is a 14-pin integrated circuit consisting of four 2-input NAND gates with open collector outputs, each gate performing the logic NAND gate function. These are intended for applications where a TTL “totem pole” output configuration is not required. This IC may be used to implement active-low wired-OR or active-high wired-AND functions by connecting them to other open-collector outputs. Aside from the output, the circuitry is the same as the standard quadruple 2-input gate 7400. Features: � The output can directly interface to CMOS, NMOS and TTL � Wide Operating Conditions. Package: 14 pin D.I.L. / (14pin FLAT) [230] Experiments in Digital Electronics Pin Configurations: Output 4 14 13 12 11 10 9 8 1 2 3 4 5 6 7 O utput 1 Inputs of G ate 4 Inputs of G ate 1 O utput 2 Output 3 Inputs of Gate 3 V cc Input s of G ate 2 GND Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 3. 7402: Quad 2-input NOR Gates Brief Description: The 7402 IC is a high-speed quad 2-input NOR gate that utilizes silicon-gate CMOS technology to achieve high speed at nominal power dissipation. This IC contains four independent gates, each of which performs the logic NOR function. Features: � Maximum current allowed to draw through each gate output: 8mA � TTL outputs � Low power consumption. � Maximum ESD: 3.5KV. � Typical Rise Time: 15ns. � Typical Fall Time: 15ns. Package: 14 pin D.I.L./ (14 pin FLAT) [231] Appendix-C Pin Configurations: Vcc Output 4 Inputs of Gate 4 Output 3 Inputs of Gate 3 14 13 12 11 10 9 8 1 2 3 4 5 6 7 Output 1 Inputs of Gate 1 Output 2 Inputs of Gate 2 GND Specifications: 4. Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 7403: Quad 2-input NAND Gates (open collector outputs) Brief Description: The 7403 IC package contains four independent positive-logic, open collector, NAND gates. The outputs of one gate can be connected to inputs of another within the same chip or another chip as long as they share the same ground. Package: 14 pin D.I.L. [232] Experiments in Digital Electronics Pin Configurations: Vcc In puts of Gate 4 14 13 12 11 10 9 8 1 2 3 4 5 6 7 O utput 2 GND Input s of G ate 1 O utput 1 Outp u t 4 In pu ts of Gate 3 Input s of G ate 2 O utp u t 3 Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 5. 7404: Hex Inverter (NOT) Gates Brief Description: The 7404 is the most commonly used 14-pin NOT gate. It consists of six inverters that perform logical invert action. The output of an inverter is the complement of its input logic state. Features: � Maximum current allowed to draw through each gate output: 8mA � Totally lead-free � Maximum Rise Time: 15ns � Maximum Fall Time: 15ns Package: 14 pin D.I.L. / (14pin FLAT) [233] Appendix-C Pin Configurations: Vcc Input of Gate 6 Output 6 Input of Gate 5 Output5 Input of Gate 4 Output 4 14 13 12 11 10 9 8 1 2 3 4 5 6 7 Input of Gate 1 Output 1 Input of Gate 2 Output 2 Input of Gate 3 Output 3 GND Specifications: Parameter Supply Voltage (Vcc) Input Voltage Operating free-air temperature range Storage Temperature Range 6. 7408: Quad 2-input AND Gates Specificatins 7V 5.5V 00 C to + 700 C - 650 C to + 1500 C Brief Description: The 7408 is a high-speed CMOS Logic Quad AND Gate. This contains four independent 2-input AND gates in one package. An AND gate is a digital logic gate with two or more inputs and one output that performs a logical conjunction. The output of an AND gate is true only when all of the inputs are true. Package: 14 pin D.I.L./ (14 pin FLAT) [234] Experiments in Digital Electronics Pin Configurations: Vcc In puts of Gate 4 14 13 12 11 10 9 8 1 2 3 4 5 6 7 O utput 2 GND Input s of G ate 1 O utput 1 Outp u t 4 In pu ts of Gate 3 Input s of G ate 2 O utp u t 3 Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 7. 7410: Triple 3- input NAND Gates Brief Description: The IC 7410 contains three independent 3-input positive NAND gates, designed as an HF/50MHz specialized rig with excellent performance. The IC-7410 employs a high-grade DSP unit and a double conversion super-heterodyne system developed from the latest technology used in our higher grade rigs, such as the IC-7800/7700/ 7600 series. Features: � Three 3-Input NAND Gates � Outputs Directly Interface to CMOS, NMOS and TTL � Large Operating Voltage Range � Wide Operating Conditions Package: 14 pin D.I.L. / (14 pin FLAT) [235] Appendix-C Pin Configurations: Vcc Input of Gate 1 Output 1 14 13 12 11 10 9 8 1 2 3 4 5 6 7 Two Inputs of Gate 1 Inputs of Gate 3 Inputs of Gate 2 Specifications: Parameter Supply Voltage (Vcc) Input Voltage Operating free-air temperature range Storage Temperature Range 8. 7411: Triple 3-input AND gates Output 3 Output 2 GND Specificatins 7V 5.5V 00 C to + 700 C - 650 C to + 1500 C Brief Description: This integrated circuit contains three independent positive logic, three-input AND gates, each performing the logic AND function. Features: � Three 3-Input AND Gates � Outputs Directly Interface to CMOS, NMOS and TTL � Large Operating Voltage Range � Wide Operating Conditions Package: 14 pin D.I.L./(14 pin FLAT) [236] Experiments in Digital Electronics Pin Configurations: Vcc Input of Gate 1 Output 1 14 13 12 11 10 9 8 1 2 3 4 5 6 7 Two Inputs of Gate 1 Inputs of Gate 3 Inputs of Gate 2 Output 3 Output 2 GND Specifications: Parameter Supply Voltage (Vcc) Input Voltage Operating free-air temperature range Storage Temperature Range 9. Specificatins 7V 5.5V 00 C to + 700 C - 650 C to + 1500 C 7420: Dual 4-input NAND gates Brief Description: The 7420 is a dual-quad input NAND gate IC. It has two independent fourinput NAND gates, a combination of NOT AND, each performing the logic NAND operation. Package: 14 pin D.I.L./ (14 pin FLAT) [237] Appendix-C Pin Configurations: V cc T w o inpu t of Gate 2 NC In p uts of Gate 2 Ou tpu t2 14 13 12 11 10 9 8 1 2 3 4 5 6 7 Tw o Input s of G ate 1 NC Tw o Input s of G ate 1 Out put 1 GN D NC: No Connection Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 10. 7421: Dual 4-input AND gates Brief Description: The 7421 IC comprises two independent four-input AND gates, each performing the logic AND function. Features: � Two Independent 4-Input AND Gates � Standard Pin Configuration � Operating Temperature to 70°C � Standard TTL Switching Voltages Package: 14 pin D.I.L./(14 pin FLAT) [238] Experiments in Digital Electronics Pin Configurations: Vcc Two input of Gate 2 NC Inputs of Gate 2 Output2 14 13 12 11 10 9 8 1 2 3 4 5 6 7 Two Inputs of Gate 1 NC Two Inputs of Gate 1 Output 1 GND Specifications: Parameter Supply Voltage (Vcc) Input Voltage Operating free-air temperature range Storage Temperature Range 11. Specificatins 7V 5.5V 00 C to + 700 C - 650 C to + 1500 C 7423: Expandable Dual 4-input NOR gate with enable/strobe Brief Description: The 7423 IC is a TTL expandable dual 4-input positive NOR gate with strobe. This contains dual 4-input positive NOR gates with a strobe in a 16 lead-plastic DIP type. Enable/strobe input is AND’ed with the four normal inputs. This device is expandable and performs Boolean functions. [239] Appendix-C Pin Configurations: Vcc Two input of Gate 2 NC Inputs of Gate 2 Output2 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 Output 1 GND Two Inputs of Gate 1 NC Inputs of Gate 1 Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 12. 7430: Single 8-input NAND gate Brief Description: The 7430 IC is a NAND gate with 8 inputs. It is 14-pin IC and has 1 circuit with an 8-input NAND gate. This gate is very useful for providing the basic functions used in the implementation of digital integrated circuit systems. Features: � High noise immunity � Minimal variation in switching times with temperature � Low output impedance � Good capacitive drive capability Package: 14 pin plastic DIP type package / (14 pin FLAT) [240] Experiments in Digital Electronics Pin Configurations: Vcc NC Inputs of Gate 1 NC NC Output2 14 13 12 11 10 9 8 1 2 3 4 5 6 7 Inputs of Gate 1 GND Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 13. 7432: Quad 2-input OR Gates Brief Description: IC 7432 is a logic gate IC that consists of four independent OR gates, each of which performs the logic OR function. This gate is very useful for providing the basic functions used in the implementation of digital integrated circuit systems. Features: � Four 2-Input Logic OR Gates � Outputs Directly Interface to CMOS, NMOS and TTL � Large Operating Voltage Range � Wide Operating Conditions Package: 14 pin D.I.L./ (14 pin FLAT). [241] Appendix-C Pin Configurations: Vcc Inputs of Gate 4 14 13 12 11 10 9 8 1 2 3 4 5 6 7 Output 2 GND Inputs of Gate 1 Output 1 Output 4 Inputs of Gate 3 Inputs of Gate 2 Output 3 Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 14. 7441: BCD-to-decimal decoder/driver (open-collector) Brief Description: The 7441 is a BCD-to-decimal decoder designed specifically to drive coldcathode indicators. This device is also capable of driving other types of low-current devices. This is a monolithic binary-coded decimal (BCD)-to-decimal decoder. The BCD to be decoded is applied to the four input lines. The unique output corresponding to the decimal equivalent of the input number falls to a low-level logic. Package: 16 pin D.I.L. / (16 pin FLAT) [242] Experiments in Digital Electronics Pin Configurations: D0 D1 D5 D4 GND D6 D7 D3 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 D8 D9 A D Vcc B C D2 D C B A: Active high BCD Inputs, A is LSB, D0 to D9 : Active low Decimal Outputs Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 15. 7445: BCD-to-decimal decoder/driver (open collector: 30 V outputs) Brief Description: This IC is a BCD-to decimal decoder/driver consisting of eight inverters and four-input NAND gates. The inverters are connected in pairs to make BCD input data available to the NAND gates. Full decoding of BCD input logic ensures that all outputs remain off for all invalid binary input conditions. Features: � fully compatible for use with TTL or DTL logic circuits � Output transistor is capable of sinking 80 mA � Compatible for interfacing with most MOS integrated circuits. � High-performance capability � Use as indicator/relay drivers, or as open-collector logic-circuit drivers. Package: 16 pin D.I.L. / (16 pin FLAT) [243] Appendix-C Pin Configurations: Vcc A B C D D9 D8 D7 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 D0 D1 D2 D3 D4 D5 D6 GND D C B A: Active high BCD Inputs, A is LSB, D0 to D9 : Active low Decimal Outputs Specifications: 16. Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 7446/7447: BCD-to-seven segment decoder/driver (open-collector) Brief Description: This is a BCD to seven-segment display decoder/driver IC with active low outputs. The IC is stand-alone and requires no external components other than the LED current limiting resistors. The output of the IC has complete ripple blanking and requires no external driver transistors. It incorporates automatic leading/ or trailingedge, zero blanking control (RBI and RBO). A Lamp test of these devices may be performed at any time when the BI/RBO mode is at a high logic level. Features: � Single BCD to 7-Segment Decoder with Open Collector Output � Active-low output for driving common anode. � Full ripple blanking input/output controls and a lamp test input � Outputs Directly Interface to CMOS, NMOS and TTL � Large Operating Voltage Range � Wide Operating Conditions [244] Experiments in Digital Electronics Package: 16 pin D.I.L. / (16 pin FLAT) Pin Configurations: Vcc f g a b c d e 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 B C LT BI/RBO RBI D A GND D C B A: Active high BCD Inputs, a to g: Seven LED of seven segment display Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 17. 7448: BCD-to-seven segment decoder/driver Brief Description: The 7448 is a BCD to seven segment decoder/driver used to display numbers [245] Appendix-C decoded in binary coded decimal format. The seven-Segments are a small seven LEDbased device used to represent a single numeric value from 0 to 9. Each seven-segment has seven input pins to light up a single led in each of the seven segments. This IC is used for common cathode configuration. Package: 16 pin D.I.L. / (16 pin FLAT) Pin Configurations: Vcc f g a b c d e 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 B C LT BI / RBO RBI D A GND D C B A: Active high BCD Inputs, a to g: Seven LED of seven segment display Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C [246] Experiments in Digital Electronics 18. 7449: BCD-to-seven segment decoder/driver (open-collector) Brief Description: The 7448 is a BCD to seven-segments decoder and driver for common cathode configuration. This package accepts a 1-2-4-8 positive logic BCD input and converts it to the proper pattern to eliminate the seven-segment display. High output is intended to light the segment. Package: 16 pin D.I.L. / (16 pin FLAT) Pin Configurations: Vcc f g a b c d 14 13 12 11 10 9 8 1 2 3 4 5 6 7 B C BI D A e GND D C B A: Active high BCD Inputs, a to g: Seven segments of LED (Common cathode). Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C [247] Appendix-C 19. 7472: AND-Gated J-K FLIP- FLOP Brief Description: This IC is a Single AND Gated JK Master/Slave Flip-Flop. It is a single flip flop with gating used to perform logic on the J and K inputs. Separate active low PRESET AND CLEAR inputs override the clock and permit the flip flop to be directly set to either state. The flip flop is termed Master-Slave since the J and K information is loaded into the Master section when the clock voltage rises and is transferred to the Slave section and output when the clock voltage falls. The device also features a special clock line clamp to reduce ringing and prevent false clocking. Features: � Single AND Gated JK Master/Slave Flip-Flop � Outputs Directly Interface to CMOS, NMOS and TTL � Large Operating Voltage Range � Wide Operating Conditions Package: 14 pin D.I.L./ (14 pin FLAT) Pin Configurations: Vcc PRE CLK (�) K3 K2 K1 Q1 14 13 12 11 10 9 8 1 2 3 4 5 6 7 NC CLR J1 J2 J3 Q1 GND CLK (�) : Negative Edge Triggering, J = J1J2J3; K= K1K2K3 [248] Experiments in Digital Electronics Specifications: Parameter Supply Voltage (Vcc) Input Voltage Operating free-air temperature range Storage Temperature Range 20. 7473: Dual J-K FLIP- FLOP Specificatins 7V 5.5V 00 C to + 700 C - 650 C to + 1500 C Brief Description: The 74LS73 is a dual in-line JK flip flop IC. It contains two independent J-K flip-flops with individual J-K, clock and direct clear inputs. The 7473 is a negative pulse triggered flip-flop. An active-low Asynchronous CLEAR input is provided on 7473 and is designed for use in high-speed control and counting applications. The device also features a special clock line clamp to reduce ringing and prevent false clocking. Specifications: � High speed of operation � Optimum power dissipation � High noise immunity � Guaranteed Clock Skew Package: 14 pin D.I.L./ (14 pin FLAT) 25 MHz toggling 45 mW/ff 1V 15 ns [249] Appendix-C Pin Connectios: J1 Q1 Q1 GND K2 Q2 Q2 14 13 12 11 10 9 8 1 2 3 4 5 6 7 CLK1(�) CLR1 K1 Vcc CLK2 (�) CLR 2 J2 Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 21. 7474: Dual D- type FLIP- FLOPs Brief Description: The 7474 is an edge-triggered device. The Q output will change only on the edge of the input trigger pulse. This device is designed for use where the flexibility of two inputs, such as on a JK or an RS flip flop, is not required. It was only a single data input. The logical level applied to this data input is transferred to the Q output when the clock pulse voltage rises to a logical 1. Package: 14 pin D.I.L./ (14 pin FLAT) [250] Experiments in Digital Electronics Pin Configurations: Vcc CLR 2 D3 CLK2 (�) PRE2 Q2 Q2 14 13 12 11 10 9 8 1 2 3 4 5 6 7 D1 CLK1(�) PRE1 Q1 Q1 GND . CLR1 Specifications: 22. Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 7475: Dual 2-Bit Transparent Latches Brief Description: The 7475 contains four transparent D-Latches with a common enable (gate) on latches 1 and 2, and another common enable on latches 3 and 4. When Q follows D (latch enabled), then the latch is said to be transparent. Features: � 4-bit Bi stable Latch in a 16-Pin DIP Package � Designed as a Temporary Storage for Binary Information � Latches Feature Complementary Q Outputs � Fast Switching Speed � Standard TTL Switching Voltages � Outputs Directly Interface to CMOS, NMOS and TTL � Large Operating Voltage Range � Wide Operating Conditions [251] Appendix-C Package: 16 pin D.I.L./ (14 pin FLAT) Pin Configurations: Q1 Q2 Q2 EN 1-2 GND Q3 Q3 Q4 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 Q1 D1 D2 EN 3-4 Vcc D3 D4 Q4 Specifications: Parameter Supply Voltage (Vcc) Input Voltage Operating free-air temperature range Storage Temperature Range 23. 7476: Dual JK FLIP- FLOP Specificatins 7V 5.5V 00 C to + 700 C - 650 C to + 1500 C Brief Description: The 7476 is a positive edge triggered flip flop with individual J-K, clock, preset, and clear inputs. The J and K inputs must be stable when the clock is high. The 7476 is a master-slave J-K flip-flop. It has synchronous inputs of J, K and clock pulse, two asynchronous inputs preset (PRE) and clear (CLR) to set and clear flip flops. [252] Experiments in Digital Electronics Features: � 4 bit bi -stable latch in a sixteen pin DIP package. � The operating voltage range for IC is 4 to 6V � Input voltages range HIGH state is a minimum of 2V and the LOW state is 0.8V. I � Draws output voltages for the HIGH state is 3.5V and LOW state is 0.25V. � Large operating voltage range � Fast switching speed Package: 16 pin D.I.L./ (16 pin FLAT) Pin Configurations: K1 Q1 Q1 GND K2 Q2 Q2 J2 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 CLK1(�) PRE1 CLR1 J1 Vcc CLK2 (�) PRE2 CLR 2 [253] Appendix-C Specifications: 24. Parameter Supply Voltage (Vcc) Input Voltage Operating free-air temperature range Storage Temperature Range 7482: 2-bit Binary Adder Specificatins 7V 5.5V 00 C to + 700 C - 650 C to + 1500 C Brief Description: The 7482 is a 2-bit binary full adder in a 14-Lead DIP type package that performs the addition of two-bit binary numbers. Sum outputs are provided for each bit, and the resultant carry out is obtained from the second bit. Package: 14 pin D.I.L. Pin Configurations: A1 B1 S1 GND Cout NC NC 14 13 12 11 10 9 8 1 2 3 4 5 6 7 A0 B0 Vcc Cin NC NC . S0 Experiments in Digital Electronics [254] Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 25. 7483: 4-bit Binary Adder Brief Description: The IC 7483 is a 4-bit parallel adder that consists of four interconnected full adders along with the look-ahead carry circuit. This binary full adder has two four-bit binary numbers. A carry input is included, and four outputs are provided along with the resultant carry. Since the carry-ripple-time is the limiting delay in the addition of a long word-length, carry-look-ahead circuitry has been included in the design to minimize this delay. Features: � 4-bit Full Adder with Carry Out. � Output Propagation delay: 16nS. � Maximum Input Low Voltage: 0.8V. � Minimum Input High Voltage: 2V. � Easily expandable through high speed cascading input � Typical power 275 mW � Typical propagation delay from carry-input to carry output is 12 ns. Package: 14 pin D.I.L. [255] Appendix-C Pin Configurations: B3 S3 Cout 16 15 14 1 2 A3 S2 Cin GND B0 A0 S0 13 12 11 10 9 3 4 5 6 7 8 A2 B2 Vcc S1 B1 A1 Specifications: 26. Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 7485: 4-bit Magnitude Comparator Brief Description: The IC 7485 is a 4-bit magnitude comparator that can be used for the comparison of straight binary numbers and BCD coded numbers. This device is fully expandable through the use of cascading inputs. A digital comparator is widely used in combinational systems and is specially designed to compare the relative magnitudes of binary numbers. To compare two binary numbers, first, their MSB (Most Significant Bits) are compared. Features: � Compares 4-bit Binary or BCD Codes and Outputs Greater, Less Than or Equal. � Outputs Directly Interface to CMOS, NMOS and TTL. � Large Operating Voltage Range. � Wide Operating Conditions. [256] Experiments in Digital Electronics Package: 16 pin D.I.L. Pin Configurations: Vcc A3 B2 16 15 14 1 2 3 B3 A>B A2 A1 B1 A0 B0 13 12 11 10 9 4 5 6 7 8 A<B GND A=B A>B Cascading Inputs A>B A=B Outputs Connect first 7483’s cascading Inputs as: A>B, A<B to logic ‘0’, and A=B to logic ‘1’. Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 27. 7486: Quad EX-OR Gates Brief Description: The 7486 is a quad 2-input EX-OR gate IC, and each gate has the functionality of the EX-OR (Exclusive-OR) gate function. The internal gates in these ICs are made of Schottky Transistors of low power. [257] Appendix-C Features: � Four 2-Input Exclusive OR Gates. � Outputs Directly Interface to CMOS, NMOS and TTL. � Large Operating Voltage Range. � Wide Operating Conditions. � Typical noise immunity 1V � Average Propagation delay15ns � Average Propagation dissipation 40 mw per gate Package: 14 pin D.I.L./ (14 pin FLAT) Pin Configurations: Vcc Inputs of Gate 4 14 13 12 11 10 9 8 1 2 3 4 5 6 7 Output 2 GND Inputs of Gate 1 Output 1 Output 4 Inputs of Gate 3 Inputs of Gate 2 Specifications: Parameter Supply Voltage (Vcc) Input Voltage Operating free-air temperature range Storage Temperature Range Absolute Maximum Rating: Output 3 Specificatins 7V 5.5V 00 C to + 700 C - 650 C to + 1500 C Same as 7400. [258] Experiments in Digital Electronics 28. 7490: BCD Counter Brief Description: The IC 7490 is a decade counter IC in which four master-slave flip-flops are internally connected to provide a divide-by-2 and divide-by-5 counter, which can generate output code in BCD. It is an Asynchronous Decade Counter IC, which can count the binary numbers from 0000 to 1001. After 1001, it gets reset and again starts counting. As the IC 7490 gets reset after counting ten numbers, it is called the MOD10 Decade Counter. Gating is provided to reset the counters to design the different MOD-N counters. Features: � BCD decade counter � Count pulses at a frequency of 20 MHz. � High speed at moderate power dissipation, � High noise immunity and minimal variation in performance over temperature. Package: 24 pin D.I.L./ (24 Pin FLAT) Pin Configurations: CLKA (�) NC QA QD GND QB QC 14 13 12 11 10 9 8 1 2 3 4 5 6 7 CLKB(�) MR1 MR2 NC Vcc MS1 MS2 [259] Appendix-C CLK (�) : Negative Edge Triggering. The MOD of the IC 7490 is set by changing the MR1 and MR2 pins. If any one of MR1 & MR2 is at high or MS1 & MS2 is at ground, the counter will reset all the outputs QA, QB, QC, and QD to 0. Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 29. 7491:A 8-bit Serial-in Serial-out Shift Register Brief Description: This IC is a monolithic serial-in, serial-out, 8-bit shift register that utilizes TTL circuits and is composed of eight R-S master-slave flip-flops, input gating, and a clock driver. The input data of the first flip-flop is controlled by gated inputs A and B and an internal inverter to form the complementary inputs to the first bit of the shift register. The drive for the internal common clock line is provided by an inverting clock driver. Features: � Typical noise immunity 1.0 V � Typical power dissipation 175 mW � Full fan out 10 � Storing and transferring data at clock rates up to 22 MHz. Package: 14 pin D.I.L./ (14 pin FLAT) [260] Experiments in Digital Electronics Pin Configurations: Q Q A B GND CLK(�) NC 14 13 12 11 10 9 8 1 2 3 4 5 6 7 .NC NC NC NC Vcc NC NC CLK(�) : Negative Edge Triggering Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C Absolute Maximum Rating: Same as 7400. 30. 7492: Divide-by-12 Counter Brief Description: The IC 7492 is a 4-Bit ripple counter (4 cascaded counting elements) that consists of four dc-coupled master-slave flip flops that are internally interconnected to provide a divide-by-two and a divide by-six counter. This counter is fully programmable and can also be used as a 4-bit latch. This high-speed counter will accept count frequencies of 0 to 40 MHz at the clock A input and 0 to 20 MHz at the clock B inputs. Features: � Contains a divide-by-two Section and a divide-by-six Section � Sections can be Combined to form BCD, modulo-12 or modulo-16 Counters � Operating Temperature to 70°C � Standard TTL Switching Voltages � High Count Rates: 42MHz. � Low Power Consumption: 45mW. � Low power dissipation [261] Appendix-C Package: 14 pin D.I.L./ (14 Pin FLAT) Pin Configurations: CLKA (�) NC QA QB GND QC QD 14 13 12 11 10 9 8 1 2 3 4 5 6 7 CLKB (�) . NC NC NC Vcc MR1 MR2 Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 31. 7493: 4-bit Binary Counter Brief Description: The IC 7493 is a 4-bit binary counter that consists of four master-slave JK flip-flops internally connected to provide a MOD-2 up-counter and a MOD-8 upcounter. The MOD-2 and MOD-8 up-counters can be used independently or in combination. In this combination, the output of QA is connected to the input of CLKB, and pulses to be counted are applied to the input CLKA, then the circuit operates as a normal binary counter. [262] Experiments in Digital Electronics Features: � 4-Bit Binary Counter � Output High Voltage: 3.5V. � Output Low Voltage: 0.25V � Output current when high: (-) 0.4mA. � Output current when low: 8mA. � Input clock frequency: 32MHz and 16MHz. Package: 14 pin D.I.L Pin Configurations: CLKA (�) NC QA QD GND QB QC 14 13 12 11 10 9 8 1 2 3 4 5 6 7 CLKB (�) . MR1 MR2 NC Vcc NC NC [263] Appendix-C Specifications: 32. Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 7495: 4-bit Serial/Parallel-in, Parallel- out Shift Register Brief Description: The 74LS95 is a 4-bit Shift Register with serial and parallel synchronous operating modes. The serial shift-right and parallel load are activated by separate clock inputs selected by a mode control input. A mode control input enables a rightshift or left-shift operation, depending on whether its input is a zero or one. Data transfer occurs on the negative transition of the clock pulse. Features: � Output High Voltage: 3.5V. � Output Low Voltage: 0.25V � Output current when high: -0.4mA. � Output current when low: 8mA. Package: 14 pin D.I.L. / (14 pin FLAT) [264] Experiments in Digital Electronics Pin Configurations: Vcc QA QB QC QD CLK1 (�) CLK2 (�) 14 13 12 11 10 9 8 1 2 3 4 5 6 7 Serial Input. A B C D MOD GND Specifications: 33. Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 74138: 1 to 8 Demultiplexer Brief Description: The IC 74138 is a 3 to 8 line decoder and is mainly used for 1 into 8 line demultiplexing applications with the help of an enable input pin as a data input pin. Its main function is to decode or otherwise demultiplex applications. There are three enable/strobe input pins: G2A, G2B, and G1. G2A and G2B are active low pins, which means when low signals are applied to those pins, they will be active. G1 is an active high pin, which means it is active when there is a high signal. Any one of these pins can be used as data input. Features: � This IC is particularly designed for high-speed Decoding capacity. � Integrates 3-enable pins for simplifying cascading. � clamped with Schottky diodes which are the high performance � Impartial propagation delays. � Supply voltage ranges from 1.0V-5.5V � Standard propagation delay is 21nsec. [265] Appendix-C Package: 16 pin D.I.L Pin Configurations: Vcc Y0 Y1 Y2 Y3 Y4 Y5 Y6 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 A B C G2A G2B1 G1 Y7 GND Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 34. 74139: Dual 1 to 4 Demultiplexer Brief Description: The 74139 comprises two separate two-line-to-four-line decoders in a single package. The active-low enabled input can be used as a data line in demultiplexing applications. It is specifically designed for high-speed memory decoders and data transmission systems. [266] Experiments in Digital Electronics Features: � Contains two fully independent 2-to-4-line decoders/demultiplexers � Schottky clamped for high performance � Typical propagation delay (3 levels of logic) is 21 ns � Typical power dissipation is 34 mW Package: 14 pin D.I.L. Pin Configurations: Vcc G2 A2 B2 2Y0 2Y1 2Y2 2Y3 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 G1 A1 B1 1Y0 1Y1 1Y2 1Y3 GND Specifications: Parameter Supply Voltage (Vcc) Input Voltage Operating free-air temperature range Storage Temperature Range Specificatins 7V 5.5V 00 C to + 700 C - 650 C to + 1500 C [267] Appendix-C 35. 74147: Decimal-to-BCD Priority Encoder Brief Description: The 74147 is a Decimal to BCD Priority Encoder. It is a TTL encoder that features priority decoding of the inputs to ensure that only the highest-order data line is encoded. The implied decimal zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level. Package: 16 pin D.I.L. Pin Configurations: . Vcc NC D D3 D2 D1 D9 A 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 D4 D5 D6 D7 D8 C B GND D1 to D9: Active Low Decimal Data. A, B, C, and D: Active Low Binary Outputs where A is LSB. Specifications: Parameter Supply Voltage (Vcc) Input Voltage Operating free-air temperature range Storage Temperature Range Specificatins 7V 5.5V 00 C to + 700 C - 650 C to + 1500 C [268] Experiments in Digital Electronics 36. 74148: Octal-to-Binary Priority Encoder Brief Description: The IC 74148 is an 8 data line to 3 line encoder (octal to binary). This IC ensures that only the highest priority or order data is encoded. The device has an inbuilt cascading circuit when input EI and output EO are enabled, which allows for octal extension without external cascading circuits. Features: � Current supply: 40mA to 60mA. � High-level input voltage: 2V. � Low-level input voltage: 0.8V. � High-level output voltage: 2. V to 3.3V. � Low level output voltage: 0.2V to 0.4V. Package: 16 pin D.I.L. Pin Configurations: . Vcc EO GS D3 D2 D1 D0 A 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 D4 D5 D6 D7 EI C B GND [269] Appendix-C Specifications: Parameter Supply Voltage (Vcc) Input Voltage Operating free-air temperature range Storage Temperature Range 37. 74150: 16 X 1 Multiplexer Specificatins 7V 5.5V 00 C to + 700 C - 650 C to + 1500 C Brief Description: The 74150 is a sixteen to one line multiplexer. It has an enable/strobe input, which must be at a low logic level to enable the multiplexer. A high level at the enable input forces the enable output to be high, and the output Y is the inverted input. Package: 24 pin D.I.L./ (24 Pin FLAT) Pin Configurations: Vcc D8 D9 D10 D11 D12 D13 D14 D15 A B C 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 D7 D6 D5 D4 D3 D2 D1 D0 EN Y D GND D1 to D15: Active high Data Inputs; A, B, C, and D: Active high Control (Select) Inputs where A is LSB [270] Experiments in Digital Electronics Specifications: Parameter Supply Voltage (Vcc) Input Voltage Operating free-air temperature range Storage Temperature Range 38. Specificatins 7V 5.5V 00 C to + 700 C - 650 C to + 1500 C 74151: 8 X 1 Multiplexer Brief Description The TTL74151 is a high-speed 8-input digital multiplexer that provides the ability to select one bit of data from up to eight inputs in one package. An additional facility of this IC is active low enable input. This means active-low enable input makes this multiplexer perform its operation depending on the selection line, otherwise disable. This can be used as a universal function generator to generate any logic function of four variables. Both assertion and negation outputs are provided. Features: � Typical propagation delay 15 ns � Typical power dissipation 135 mW � Strobe override � Performs parallel-to-serial conversion Package: 16 pin D.I.L./ (16 Pin FLAT) [271] Appendix-C Pin Configurations: Vcc D4 D5 D6 D7 A B C 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 D3 D2 D1 D0 Y Y EN GND D0 to D7: Active high Data Inputs, A, B, and C: Active high Control (Select) Inputs where A is LSB, Y: active high output and Y is active low output, EN :active low enable input Specifications: 39. Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 74153: Dual 4 X 1 Multiplexers Brief Description The74153 is a data multiplexer or data selector IC. It has inverters and drivers that supply fully complementary data selection to the AND-OR-NOT gates. It also has on-chip and binary decoding. It has a dual 1 of 4 data multiplexer in one IC package. This device acts as a double-pole four-throw switch. Two SELECT Lines determine which of the four inputs is chosen. However, the same input for both fourline sections will be selected. Features: � Typical propagation delay 20 ns � Typical power dissipation 170 mW � Input clamping diode [272] Experiments in Digital Electronics Package: 16 pin D.I.L./ (16 Pin FLAT) Pin Connections: E2 A 2D3 2D2 2D1 2D0 Y2 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 E1 B 1D3 1D2 1D1 1D0 Y1 GND Vcc Lower 4 X 1 MUX: 1D0 to 1D3 active high data input, E1 : active low enable for lower MUX, and Y1: active high output.. Upper 4 X 1 MUX: 2D0 to 2D3 active high data input, E2 is active low enable for lower MUX, and Y2 is active high output. A, and B: Active high Binary Data Control (Select) Inputs where A is LSB common for both MUX. Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C [273] 40. Appendix-C 74154: 1 X 16 Demultiplexer/Decoder Brief Description: In the 74LS154 IC, each of these 4-line-to-16-line decoders utilizes TTL circuitry to decode four binary-coded inputs into one of sixteen mutually exclusive outputs when both the enable inputs, EN1 and EN2, are low. The demultiplexing function is performed by using the 4 input lines to address the output line, passing data from one of the enable inputs to the other enable input. When either enable input is high, all outputs are high. Features: � Performs the demultiplexing function by distributing data from one input line to any one of 16 outputs � Input clamping diodes simplify system design � High fan-out, low-impedance, totem-pole outputs � Typical propagation delay 3 levels of logic 23 ns Strobe 19 ns � Typical power dissipation 45 mW Package: 24 pin D.I.L./ (24 Pin FLAT) [274] Experiments in Digital Electronics Pin Configurations: Vcc A B C D EN2 EN1 Y15 24 23 22 21 20 19 18 1 2 3 4 5 6 Y0 Y1 Y2 Y3 Y4 Y5 Y14 Y13 Y12 Y11 17 16 15 14 13 7 8 9 10 11 12 Y6 Y7 Y8 Y9 Y10 GND EN1 and EN2 : active low enable input, A, B C D : active high inputs, Y to Y15 : active low outputs when both enable are low, and when either (or both) enable inputs are high, Specifications: 41. Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 7V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 74157: Quad 2X1 Multiplexers Brief Description: The 74HC157 is a 2-input (2X1) Multiplexer IC. It has four similar multiplexers inside it, and hence it is called Quad Package 2-Input Multiplexer. Each has two input pins (for the first MUX: input 1A and 1B) and one output pin (for the first MUX: output 1Y), which forms a 2X1 Multiplexer. It selects four bits of data from two sources under the control of common data select input when the enable input is active low. Features: � 2-input Multiplexer Quad Package. � Minimum high-level Input Voltage: 3.15V @ (Vcc = 4.5V) � Maximum low-level Input Voltage: 1.35V @ (Vcc = 4.5V) � TTL/CMOS Input Logic compatibility. [275] Appendix-C � Maximum Propagation Delay: 25ns @ (Vcc = 4.5V) Package: 24 pin D.I.L./ (24 Pin FLAT) Pin Configurations: EN A4 B4 Y4 A3 B3 Y3 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 S A1 B1 Y1 A2 B2 Y2 GND Vcc A and B: active high data inputs, Y: active high output, EN : common active low enable input Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 7V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 42. 74164: 8-bit Serial-in, Parallel-out Shift Register Brief Description: The 74LS164 is a high-speed shift register with serial input of data and parallel [276] Experiments in Digital Electronics output of data. Data at serial input is fed through one input of AND gate, and it is synchronous with the LOW to HIGH transition of the clock. In other words, the transition of data occurs on every positive edge of the input clock. Features: � 8-bit Gated Serial Inputs with Asynchronous Clear � Clocking Occurs on the Low-to-High Transition of the Clock Input � Data at the Serial Inputs can be Changed on High or Low State of the Clock � Standard TTL Switching Voltages Package: 24 pin D.I.L./ (24 Pin FLAT) Pin Configurations: Vcc QH QG QF QE CLR CLK(�) 14 13 12 11 10 9 8 1 2 3 4 5 6 7 A B QA QB QC QD GND A and B ( Serial input A, B): These pins are used to serial input data to the IC, which needs to be converted into parallel output. These are serial data input pins, CLK (�) : This input pin is for a clock signal. It is an active high rising edge pin. CLR : This pin [277] Appendix-C is used to perform the function of master reset. This is an active low input pin. QA to QH : These are output pins and are used for providing parallel data of 8 bits as output, Vcc : terminal for feeding positive power supply, GND: ground terminal of power supply. Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 7V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 43. 74165: 8-bit Serial/Parallel-in, Parallel-out Shift Register Brief Description: The 74LS165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputting occurs asynchronously when the Parallel Load (S/L) input is LOW. With S/L HIGH, serial shifting occurs on the rising edge of the clock; new data enters via the Serial input (SI). The 2-input OR clock can be used to combine two independent clock sources, or one input can act as an active LOW clock enable. Features: � 8-bit Serial Shift Register for Serial Data Output � Complementary Outputs � Gated Clock Inputs � Direct Overriding Load Inputs Package: 24 pin D.I.L./ (24 Pin FLAT) [278] Experiments in Digital Electronics Pin Configurations: CLKINH(�) D C B A SI QH 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 S/L CLK(�) E F G H QH GND Vcc For clock operation, S/L must be high. The two clock inputs perform identically; one can be used as a clock inhibit by applying a high signal. To avoid double clocking, however, the inhibit signal should only go high while the clock is high. Otherwise, the rising inhibit signal will cause the same response as a rising clock edge. The flip-flops are edge-triggered for serial operations. The serial input data can change at any time, provided only that the recommended setup and hold times are observed with respect to the rising edge of the clock. CLK (�) and CLKINH(�) : Clock (LOW-to-HIGH Going Edge) Inputs, SI: Serial Data Input, S/L: Asynchronous Parallel Load (Active low input load data and active high shift the data) Input, A to H: Parallel Data Inputs, QH: Serial active high Output, QH : Serial active low Output. Specifications: Parameter Supply Voltage (Vcc) Input Voltage Operating free-air temperature range Storage Temperature Range 44. 74180: 9-bit Parity Generator/Checker Specificatins 7V 7V 00 C to + 700 C - 650 C to + 1500 C Brief Description The 74180 is a universal, monolithic, 9-bit (8 data bits plus 1 parity bit) parity generator/checker in a 14-lead plastic DIP type package that utilizes familiar Series 74 TTL circuitry and features odd/even outputs and control inputs to facilitate operations in either odd or even/parity applications. This IC consists of eight parity inputs from A through H and two cascading inputs. There are two outputs, an even sum and an odd sum. In implementing generator or checker circuits, unused parity bits must be tied to logic zero, and the cascading inputs must not be equal. [279] Appendix-C Features: � Typical propagation delay, 30 ns � Typical power dissipation, 180 mW � Ease of expansion Package: 14 pin D.I.L./ (14 Pin FLAT) Pin Configurations: F E D C B A 14 13 12 11 10 9 8 1 2 3 4 5 6 7 G H Even input Odd input Σ Even output Σ Odd output GND Vcc A to H: parity inputs, Even input and Odd input: cascading input used when required to cascade two ICs. Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C [280] Experiments in Digital Electronics 45. 74184: BCD-to-Binary Code Converter Brief Description: The 74184 is a 6-bit BCD-to-binary code converter IC. Emitter connections are made to provide a direct read-out of converted codes at outputs Y7 through Y1. An overriding enable input is provided on each converter which when taken high. It inhibits the function, causing all outputs to go high. Package: 16 pin D.I.L Pin Connections: Vcc EN E D C B A Y10 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 Y1 Y2 Y3 Y4 Y5 Y6 Y7 GND Specifications: Parameter Supply Voltage (Vcc) Input Voltage Operating free-air temperature range Storage Temperature Range Specificatins 7V 5.5V 00 C to + 700 C - 650 C to + 1500 C [281] 46. Appendix-C 74194: 4-bit Bi-directional ( Universal) Shift Register Brief Description The IC 74LS194 is a bidirectional shift register consisting of the facility of shifting data as parallel inputs, parallel outputs, right-shift and left-shift serial inputs. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is HIGH, and S1 is LOW. Serial data for this mode is entered at the shiftright data input. When S0 is LOW, and S1 is HIGH, data shifts left synchronously, and new data is entered at the shift-left serial input. The clocking of the flip-flop is inhibited when both mode control inputs are LOW. Features: � Parallel inputs and outputs � Three operating modes: Synchronous parallel load, Right-shift, Left-shift, � Positive edge-triggered clocking � Direct overriding clear Package: 14 pin D.I.L. [282] Experiments in Digital Electronics Pin Configurations: QC QD CLK(�) S1 14 13 12 11 10 9 2 3 4 5 6 7 8 SRSI A B C D SLSI GND Vcc QA QB 16 15 1 CLR S0 Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 47. 74195: Universal 4-bit Serial/Parrel-in, Parallel-out Shift Register Brief Description: The 74195 is a 4-bit parallel access shift register in a 16-lead plastic DIP type package. It features parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct overriding clear. All inputs are buffered to lower the input drive requirements. This is a high-speed 4-bit shift register. It is useful for a wide variety of register and counter applications. Features: � Asynchronous master reset � J and K inputs to first stage � Fully synchronous serial and parallel data transfer Package: 14 pin D.I.L. [283] Appendix-C Pin Configurations: QC QD QD CLK (�) 14 13 12 11 10 9 2 3 4 5 6 7 8 J K A B C D GND Vcc QA QB 16 15 1 CLR S/L S/L: active low parallel enable inputs, A to D: parallel data inputs, J: first stage active high input, K: first stage active low input, CLK (�) : Positive edge triggered clock pulse input, CLR : Active low asynchronous input, QA to QD: parallel outputs, QD : Complementary last stage output (active low). Specifications: 48. Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 74198: 8-bit Bi-directional ( Universal) Shift Register Brief Description: The 8-bit bi-directional universal shift register IC is useful for serial-serial, serial-parallel, parallel-serial, and parallel-parallel data transfer. An asynchronous master reset input overrides all other inputs and clears the register. This Shift right is accomplished with the rising edge of the clock pulse when S0 and S1 are low and serial data for this mode is entered at the shift right data input. When S0 and S1 are high, data shift left synchronously, and new data is entered at the shift left serial input. Features: � 8-bit bi directional universal shift register � Average Propagation delay is from 26 to 30 ns per gate � Shift frequency is 25 MHz [284] Experiments in Digital Electronics Package: 24 pin D.I.L. / (24 pin FLAT) Pin Configurations: Vcc S1 SLSI H QH G QG F QF E QE CLR 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 S0 SRSI A QA B QB C QC QD CLK (�) GND D SRSI: Shift right serial input, SLSI: Shift left serial input, A to H: data inputs, QA to QH: data output. Specifications: Parameter Specificatins Supply Voltage (Vcc) 7V Input Voltage 5.5V Operating free-air temperature range 00 C to + 700 C Storage Temperature Range - 650 C to + 1500 C 49. 74199: 8-bit Serial/Parallel-in, Parallel-out Shift Register Brief Description: These 8-bit shift registers are compatible with most other TTL logic families. It is an 8-bit shift register capable of being operated in three modes. Shift right is [285] Appendix-C accomplished with the rising edge of the clock pulse when S0 and S1 are low. Serial data for this mode is entered at the shift right data input. When So and S1 is high, data shift left synchronously, and new data is entered at the shift left serial input. Clocking of flip flop is inhibited when both mode control inputs are low. The mode control should be changed only while the clock input is high. Features: � Eight bit Serial/Parallel-in and Parallel out shit register � Average Propagation delay is from 14 ns to 21 ns per gate � Shift frequency is 35 MHz � Power dissipation is 360mW Package: 24 pin D.I.L. / (24 pin FLAT) Pin Configurations: E QE CLR CLK(�) 17 16 15 14 13 7 8 9 10 11 12 C QC QD CLKINH(�) GND Vcc S/L H QH G QG F 24 23 22 21 20 19 18 1 2 3 4 5 6 K J A QA B QB QF D [286] Experiments in Digital Electronics Specifications: Parameter Supply Voltage (Vcc) Input Voltage Operating free-air temperature range Storage Temperature Range 50. 74279: Quad Specificatins 7V 5.5V 00 C to + 700 C - 650 C to + 1500 C Latches Brief Description: The 74LS279 consists of four individual and independent Set-Reset Latches with active-low inputs. Two of the four latches have an additional S input ANDed with the primary S input. A low on any S input, while the R input is high, will be stored in the latch and appear on the corresponding Q output as a high. A low on the R input, while the S input is high, will clear the Q output to a low. The simultaneous transition of the R and S inputs from low to high will cause the Q output to be indeterminate. Both inputs are voltage level triggered and are not affected by the transition time of the input data. Features: � Four Basic Set-Reset Flip-Flop. � Operating Temperature 0°C to 70°C � Standard TTL Voltages � Average Propagation delay is from 14ns to 21 ns per gate Package: 14 pin D.I.L. [287] Appendix-C Pin Configurations: 4S1 4R 4Q 3S2 3S1 3R 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 1R 1S1 1S2 1Q 2R 2S 2Q GND Vcc 51. 3Q 74280: 9-bit Parity Generator/Checker Brief Description: The 74S280 is an MSI circuit that functions as a 9-bit parity generator/checker. If the number of inputs 'A' through 'I' is high is even, then the � even output goes high and � odd output goes low. To use the IC as an even-parity generator, use � odd output to generate the parity bit. These devices are fully compatible with most other TTL circuits. Features: � 9-bit parity generator/checker � Typical power dissipation � Average Propagation delay Package: 14 pin D.I.L. : : 80 mW 14 to 21 ns per gate [288] Experiments in Digital Electronics Pin Configurations: Vcc F E D C B A 14 13 12 11 10 9 8 1 2 3 4 5 6 7 G H NC I Σ Even Σ Odd GND A to I: Data inputs, Σ Even and Σ Odd: out puts Specifications: Parameter Supply Voltage (Vcc) Input Voltage Operating free-air temperature range Storage Temperature Range Specificatins 7V 5.5V 00 C to + 700 C - 650 C to + 1500 C [289] Appendix- D BIBLIOGRAPHY A. B. BOOKS 1. A. Anand Kumar, Fundamentals of Digital Circuits, PHI Publication, 2014. 2. Balch, Complete Digital Design, McGraw-Hill Education (India), Pvt. Limited, 2005. 3. Fredrick W. Hughes, Digital Electronics (Theory and Experimentation), Prentice-Hall, 1986. 4. James Bignell and Robert Donovan, Digital Electronics (Fourth Edition), DELMAR THOMSON LEARNING, 2001. 5. M. Morris Mano, Michael D. Ciletti, Digital Design: With an Introduction to the Verilog HDL, Pearson Publication, 2012. 6. M. V. Subramanyam, Switching Theory and Logic Design, Laxmi Publications, 2005. 7. Owen Neville Bishop, Digital Electronics Projects for Beginners, PC Publishing, 1990. 8. R. J. Tocci, Digital System: Principles and Applications, Prentice-Hall Publication, 1977. 9. R. P. Jain, M. M. S. Anand, Digital Electronics Practice Using Integrated Circuits, Tata McGraw-Hill, 2001. 10. Robert Dueck, Ken Reid, Digital Electronics, Cengage Learning, 2011. 11. Virendra Kumar, Digital Electronics Theory and Experiments, New Age International Publishers, 2002. DATA MANUALS 1. BEL Semiconductors Data Manual, Bharat Electronics Ltd., Bangalore (India), 1975. 2. Condensed Data Book on Linear and Digital Integrated Circuits, General Radio Co.,Calcutta. 3. MOTOROLA : The Integrated Circuit Data Book, 1968. 4. NATIONAL TTL Data Book, 1976. : [290] Experiments in Digital Electronics C. 5. SIGNETICS Logic : TTL Data Manual, 1978. 6. TEXAS : The TTL Data Book for Design Engineers, 1976. LINKS 1. https://alldatasheet.com 2. https://www.electroniq.net/other-electronic-software/ic-databook.html 3. https://circuitverse.org/users/63092