Lead-Free Solder Films Via Novel Solution Synthesis Routes

486 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 3, SEPTEMBER 2007 Lead-Free Solder Films Via Novel Solution Synthesis Routes Ankur O. Aggarwal, Isaac R. Abothu, P. Markondeya Raj, Michael D. Sacks, and Rao R. Tummala, Fellow, IEEE Abstract—We report two novel routes, sol-gel and electroless plating, for the synthesis of lead-free solders. Novel processes with these routes were developed and demonstrated for Sn–Ag–Cu, Sn–Ag systems to achieve thin bonding layers for assembly of fine pitch integrated circuits onto substrates. Sol–gel route can be used to accurately control the final alloy composition and incorporate additives leading to the designed thermomechanical properties. In this process, the inorganic polymer solutions were spin coated and then heat-treated in a reducing atmosphere to form thin films of lead-free solders. The presence of Ag and Cu enabled easy reduction of tin oxide to tin at 400 C that was not possible with Sn precursor. With the alternate solution reduction (electroless plating) approach, bonding layers can be deposited at almost room temperatures directly on organic substrates. With this approach, the deposition selectively occurs on the metal bonding pads, which eliminates the need for any lithography. Using this approach, electroless Sn–Ag films were demonstrated on organic laminates. These thin film synthesis routes can enable short interconnections that are critical for high density, high frequency, and embedded active component packaging. Index Terms—Integrated circuits (ICs), laminates, Sn–Ag films. I. INTRODUCTION INIATURIZATION of high speed digital and high frequency wireless systems is driving the chip-package interconnections from the bulky solders of today to thin solder film based bonding with minimal electrical parasitics ( , , and ) in the near future (Fig. 1). High input/output (I/O) density multicore architectures for digital applications and ultrathin RF modules are pushing the off-chip interconnections to ultrafine pitch with minimal stand-off height. Along with added functionality and miniaturization trends, electronics is also moving towards greener and more environmentally friendly products. In the near future, consumers want a product which has a proven smaller impact on the environent, through ecological labeling and recycling considerations. Semiconductor packages are considered Restriction Of Hazardous Substances (RoHS) compliant when four elements: Pb, Br, Cl, and Sb are not intentionally added during the M Manuscript received May 9, 2006; revised December 5, 2006. This work was supported by the National Science Foundation (NSF) through the NSF ERC in Electronic Packaging, Georgia Institute of Technology under Grant EEC9402723. This work was recommended for publication by Associate Editor K.-N. Chiang upon evaluation of the reviewers comments. A. O. Aggarwal is with the C4 Group, Logic Technology Development (LTD), Intel Corporation, Hillsboro, OR 97124 USA. I. R. Abothu, P. M. Raj, M. D. Sacks, and R. R. Tummala are with the Microsystems Packaging Research Center, Georgia Institute of Technology, Atlanta, GA 30332 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCAPT.2007.900062 Fig. 1. Trend in IC interconnections going from solder-paste derived coarse pitch to fine pitch using thin solder films. manufacturing process. Reduction of Pb-content below the restrictive limits would mean a refining step that is costly and has a substantial impact on environment. Many different kinds of “lead-free” solder alloys and soldering processes for microelectronic packaging applications are being investigated or developed around the world, using multiple combinations of elements like tin, silver, copper, bismuth, indium and zinc, most of which require increased temperature profiles during the soldering process relative to the well-known tin-lead alloys. Table I shows some of the common lead-free solders. To accommodate fine pitch wafer-level flip chip interconnections, industry is responding by moving from thick solder paste printing to electroplating of solder alloys. Electroplating, in principle, can be downscaled to micro/nano size dimensions. However, electroplating of ternary lead-free solder alloys has not been widely successful so far, leading to compromised mechanical fatigue and creep properties and susceptibility to intermetallics. Conseqeuntly, current electroplated binary alloys (Sn–Cu, Sn–Ag) do not have sufficient strength and fatigue resistance to address reliability concerns at fine pitch. Incorporating additives that can improve the mechanical properties is extremely tedious with the emerging electroplating technology while solder paste route cannot be scaled down to fine pitch of 10–50 m. Therefore, there is a need for novel solder synthesis routes that can be scaled to fine pitch while having flexibility in the composition. Hence, the focus of this research is to develop novel processing routes for low-cost alloy systems with superior electrical performance and reliability. We report, for the first time, sol-gel route to synthesize lead-free materials. Sol-gel was selected because of its inherent ability to introduce trace elements with required stoichiometry into the alloy system. It offers distinct advantages such as better 1521-3331/$25.00 © IEEE AGGARWAL et al.: LEAD-FREE SOLDER FILMS 487 TABLE I WIDELY USED BINARY AND TERNARY LEAD-FREE SYSTEMS [1], [2] Fig. 2. Flowchart for the synthesis of SnAgCu lead free solder by sol-gel technology. control over stoichiometry and chemical homogeneity. Further, this approach can achieve nano-grained films with easy incorporation of suitable additives in order to tailor the mechanical properties. Purity of surface sol-gel (SSG) derived materials can be controlled by the purity of the starting chemicals, while homogeneity can be controlled by precisely controlling the hydrolysis, condensation and polymerization reactions. The starting precursors in the SSG process can be metal-organic compounds, inorganic-metal salts etc. The key, however, is to achieve ultra homogeneous mixing at atomic to molecular level. Synthesis of high purity ceramic powders via the SSG process has previously been reported [3], [4]. To the best of our knowledge, there are no reports on the synthesis of lead-free solders by solution-sol-gel (SSG) processing. Thus, the objective of the present study is to apply the strategy of atomic to molecular level mixing of the precursors and synthesize nano lead-free solder materials by sol-gel technology. Further, in this research, we explored electroless plating for a comparative study with the sol-gel processes. Electroless plating can selectively deposit thin films of metals and alloys at 50 C temperature without external power source and is hence another attractive cost-effective processing route for thin film solder based interfaces. However, the control of final alloy composition and incorporation of additives requires careful control of the plating bath, selection of reducing agents and control of processing conditions. This approach uses soluble salts in a aqueous solution and the metal ions are reduced to metal using reducing agents. Suitable catalytic surface treatment is used to selectively deposit the alloy films on the metallic pads. Metal nanoparticles and films are often formed directly in solution by reduction of metal salts. This is accomplished by using strong reducing agents such as alkali metals, alkali metal borohydrides, etc. For example, silver salts (e.g., AgNO , AgCl) or gold salts (e.g., HAuCl ) can be reduced by sodium borohydride to form silver or gold nanoparticles. For some metals such as Ag, Au, Pt, etc. weaker reducing agents (alcohols, DMF, ethylene glycol, citric acid, etc.) can be used for synthesizing the nanoparticles, which is a big advantage from the safety viewpoint. Unlike metal-organic precursors used in the sol-gel approach, this approach uses soluble salts in which the metal ions would be reduced to the metal using reducing agents. The driving force for the reduction of metal ions and their deposition is supplied by the chemical reducing agent in solution. This driving potential is essentially constant at all points of the sample surface, provided the agitation is sufficient, to ensure a uniform concentration of metal ions and reducing agents. Electroless deposits are therefore very uniform in thickness all over the part’s shape and size. The National Electronics Manufacturing Initiative (NEMI) has endorsed Sn–Ag–Cu as the lead-free solder standard for the electronics industry. Further, microalloying of grain refining elements into SnAg and SnAgCu systems is known to achieve better mechanical properties [5]. Hence, Sn–Ag–Cu and Sn–Ag alloys have been selected in this work to deposit liquid interface films of lead free solders. In this study, Sn Ag Cu was synthesized with the sol-gel process and SnAg with the electroless plating process. II. EXPERIMENTAL METHODS A. Sol-Gel Synthesis of Lead-Free Alloys The experimental procedure adopted for the synthesis of Sn Ag Cu by sol-gel process is depicted in Fig. 2. Tin (II) 2-ethylhexonate CH CH CH C H CO Sn (Aldrich), (Alfa Aesar) and Silver Copper (II) ethoxide Cu(OC H Nitrate (AgNO ) (Alfa Aesar) were used in this process. Initially, a stoichiometric amount of Tin (II) 2-ethylhexanoate was dissolved in 2-methoxyethanol (2-MOE) as solvent in a flask and refluxed at 125 C for 5 h in nitrogen atmosphere. Subsequently, copper (II) ethoxide was dissolved in 2-MOE in a separate flask and refluxed in nitrogen atmosphere at 125 C 488 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 3, SEPTEMBER 2007 TABLE II PROCESS CONDITIONS FOR ELECTROLESS PLATING for 5 h. Both the Sn and Cu precursor solutions were then cooled to room temperature. Finally, silver nitrate was dissolved in 2-MOE in a separate flask and refluxed at 125 C for 5 h. This silver precursor solution was cooled to room temperature and then added to the Sn–Cu solution and refluxed at 125 C for 5 h to obtain a clear Sn–Ag–Cu precursor solution. A similar procedure was adopted for Sn–Cu. Silicon wafers were then spin coated at 1000 RPM for 15 s with the precursor solution to form a thin organo-metallic film. The spin speed and spin time can be varied to achieve different levels of film thickness. The spin coated wafers were then reduced in the forming gas (3% H /N ) environment at 400 C in a tube furnace. The reduction time for these wafers was about 5 h. Considerable amount of precautions were taken here to isolate the tube gases from outside atmosphere by sealing the tube tightly and bleeding the tube with forming gas for about 30 min prior to reduction treatment. B. Electroless Plating of Lead-Free Alloys The substrate to be deposited with electroless plated alloy was first treated in a commercial pre-catalyst pre-dip solution Cataprep 404 (18 l DI water; 9.5 lb 404 salts) [Shipley Company, Inc.]. This is a sodium hydrogen sulfate based salt that helps in anchoring the catalyst on the wafer surface. A commercial palladium-tin catalyst solution Cataposit 44 [Shipley Company, Inc.] was used at a composition of 3 vol.% of the full strength with 97 vol.% of Cataprep 404. After the catalyst treatment process, all unbound catalyst and the acidic salt solution that make up the bath is removed by rinsing the substrate in deionized water. Electroless plating was then conducted with a solution of a laboratory formulated bath consisting of stannous chloride, silver nitrate, thiourea, sulfuric acid (concentrate) and water. The salt concentration for stannous chloride and silver nitrate can be tailored according to the required alloy compositions. In our case, the targeted alloy composition was SnAg . The catalyzed wafers are immersed in the plating bath with thorough agitation so as to cause a continuous catalytic reaction on the wafer surface. The plating reaction is carried on for about 5 min at 46 C–50 C. Following the plating reaction, the wafers are rinsed thoroughly with deionised water to remove the excess bath and kept in an oxygen free environment until further characterization. The different process conditions in this electroless plating process are succinctly shown in Table II. III. RESULTS AND DISCUSSION The synthesized lead-free sol-gel precursors were characterized with thermal gravimetiric analysis (TGA) [Perkin Elmer TGA 7 HT] before further processing. In addition, the precursors were analyzed at different stages using gas adsorption (Mi- Fig. 3. TGA for Sn–Ag–Cu lead free solder precursor. crometrics Instrument Corporation) to estimate the gel surface area and pore size, infrared (IR) spectroscopy [Digilab FTS 40A Spectrometer] to determine the amount of OH content as well as the SnO bonds in the precursors. IR spectroscopy is a useful technique for characterizing materials and providing information on the molecular structure, dynamics, and environment of a compound. Many functional groups vibrate at nearly the same frequencies independent of their molecular environment [6]. IR spectroscopy is particularly useful for determing functional groups present in a molecule. The final alloy composition was determined by XPS [PHI 5600ci]. A. Sol-Gel Lead-Free Solders The sol for synthesizing lead-free alloys was characterized with TGA in nitrogen before further processing. The TGA in Fig. 3 shows a sharp decrease in weight till 125 C corresponding to solvent evaporation. It is clear that for this set of precursors, the pyrolytic decomposition of the precursor completes at around 450 C even in the nitrogen atmosphere and can be lowered to 400 C by increasing the pyrolysis time. Silicon wafers were spin coated with precursor solutions, and then spin dried at room temperature before being reduced in the forming gas (3% H /N ) environment in a tube furnace. The reduction time for these wafers was about 5 h. To further reduce the processing time, rapid thermal processing (RTP) was also evaluated as a technique to get faster reduction of precursors into metallic films. In this case the RTP processing time was 5 min in a forming gas flow of 5 l/min at 600 C. X-Ray spectra using CuKá radiation were measured on reduced alloy films. The initial set of results showed that tin oxide cannot be reduced to metallic tin even above 500 C with the conventional sol-gel route. In order to make the process compatible with back-end wafer-level processes, the process temperature has to be atleast less than 400 C. Two strategies were explored to lower the processing temperature for this gas phase reduction. 1) Strategies for Lowering the Precursor Reduction Temperature: Precursor Gel Control: One approach that can be used to get faster reduction of these oxides is lowering the precursor particle size by changing solvent, precursor, controlling the hydrolysis AGGARWAL et al.: LEAD-FREE SOLDER FILMS 489 Fig. 5. IR Spectra for the precursor pyrolysed at 400 C in air and dry nitrogen. Fig. 4. IR Spectra for the viscous gel dried at 110–140 C for 4 h in air and dry nitrogen. and gelling by minimizing contact with moisture. The hydrolysis reactions are typically written as (1) Higher reduction temperature (2) lower formation temperature (3) Controlling hydrolysis can reduce the formation of Sn–O–Sn gel and lower the reduction temperature. Although it is possible to have non-hydrolytic condensation, Sn–O–Sn formation is going to be promoted much more when moisture is available. Gelling of the sol might take place due to the exposure of concentrated sol with moisture in the ambient atmosphere prior, during, and after the spin coating. The thin film is presumably more susceptible to rapid hydrolysis than a bulk solution. The amount of Sn–O–Sn condensation can be quantified by FTIR studies of the precursors under different conditions. Minimal Sn–O–Sn peaks in the gel are correspond to lowered reduction temperature easier solder alloy formation. The precursors were analyzed at different stages using infrared (IR) spectroscopy to qualitatively determine the amount of OH content as well as the SnO bonds in the precursors. The band at approximately 3560 cm is due to the stretching vibration of -OH groups and in well agreement with reported values [6]. Many subtle structural details can be gleaned from frequency shifts and intensity changes arising from the coupling of vibrations of different chemical bonds and functional groups as indicated in the Figs. 4 and 5. From Fig. 4, it is evident that the SnO peaks are stronger in precursors exposed to air as opposed to the ones that were dried in a nitrogen atmosphere. Further, Fig. 4 explain the increased SnO vibrations for samples pyrolysed in air as compared to the ones pyrolysed in forming gas. Therefore, tighter control over exposure of precursors to air is required in order to prevent formation of more SnO groups and hydrolysis of the precursor. Sn–Ag–Cu is a three-component system with some segregation effects from preferential hydrolysis of one or more components. Hydrolysis/condensation from Fig. 6. Gel pore size and surface area analysis with the nitrogen adsorption technique. moisture contamination can be prevented by careful control of the processing atmosphere and the pH. The surface area of the gel was analyzed with a gas adsorption technique. Fig. 6 compares the nitrogen adsorption isotherms for the precursor gel pyrolzed in air (A) and nitrogen (B). The adsorption isotherm for the sample A showed type I behavior (typically a monolayer adsorption) and was fit with the Langmuir model with a correlation coefficient of 0.9998. Sample B showed type II behavior (multilayer physical adsorption) and fit well with the BET model with a similar correlation coefficient of 0.9998. The surface area for the gel pyrolyzed in air was higher (124.3 m g) compared to that in nitrogen (47 m ). The corresponding pore diameters were 1.5 and 4.1 nm, respectively. The measurements indicate that pyrolysis in air leads to finer Sn–O–Sn particles. The reduction kinetics are faster with smaller precursor particles. In spite of this, the gel that is directly heated in the reducing atmosphere without any pyrolysis step in air may undergo easier reduction according to reactions (2-3). 490 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 3, SEPTEMBER 2007 Fig. 8. X-Ray spectra of SnAgCu and SnCu lead free solders at different temperatures. Fig. 7. Thermodynamic Stability of various metallic oxides for interconnect applications [7]. 2) Alloying With Elements of Lower Reduction Potential: Sn-Cu gel could not be easily reduced to the alloy below 500 C. On the other hand, alloying with Ag lowered the reduction temperature of Sn from 500 C to 400 C Sn peaks were observed at 400 C with the Sn–Ag–Cu precursor. It can be seen from the Ellingham diagram (Fig. 7) that Ag and Cu will be easily reduced as compared to tin. The presence of Ag and Cu also enabled easy reduction of tin oxide to tin at 400 C that was not possible with Sn–Cu precursor. The lowered thermodynamic activity of Sn in presence of Ag and Cu could possibly destabilize the tin oxide in Sn–Ag–Cu and enabled the reduction at lower temperatures. 3) Sol-Gel Process Results: Tin oxide is more stable compared to silver and copper oxides and therefore, is not easy to reduce by sol-gel process unless sol preparation was done with tight control of atmospheric conditions. For Sn–Cu precursor, no Sn peaks were evident at 400 C even after the reduction was carried for 7 h in forming gas. The XRD peaks mostly correspond to crystalline SnO with an amorphous background. After minimizing hydrolysis of the sol, both SnCu and Sn Ag Cu were synthesized from reduction in forming gas. Sn–Ag–Cu solders were formed at 400 C while Sn–Cu precursor was reduced at only a temperature of 500 C. Fig. 8 summarizes the Sn–Ag–Cu and Sn–Cu films reduced at different temperatures. Further reduction in processing temperature to less than 300 C can be achieved by controlling the atmosphere during spin coating and pyrolysis. With rapid thermal processing (RTP), the processing time can be reduced to the order of minutes. Fig. 9 shows the field emission scanning electron micrograph of Sn–Ag–Cu formed on a silicon wafer. Fig. 10 shows a micrograph of two Cr–Au coated silicon wafers bonded with Sn–Ag–Cu thin interface. The thickness of the bonding interface is 200 nm. As seen in the picture, the grain size is of the order of 10 nm. B. Electroless Plating Sn and Pb–Sn electroless finish on copper pads is a wellestablished versatile industry process. On the other hand, electroless plating of lead-free alloys has not been demonstrated Fig. 9. Field emission scanning electron micrograph of reduced Sn–Ag–Cu lead free solder on a silicon substrate. Molten solder does not wet silicon and forms the droplets. Fig. 10. Field Emission SEM of a 200 nm nano lead-free solder interface bonding two silicon wafers. before though electroless plating has several advantages over electroplating because it can be selectively done only on metal pads without the need of any photolithography steps. The plating rates are relatively low but for the proposed targets of thin reworkable bonding layers ( 1 n), the processing time is adequate. The alloy composition, as determined from XPS AGGARWAL et al.: LEAD-FREE SOLDER FILMS 491 Fig. 13. SEM of a 10-m diameter interconnect bonded to a gold pad using thin electroless plated lead free solder film. Fig. 11. XPS elemental analysis of electroless lead-free solder films. Quantitative analysis estimates 4.9 wt.% Ag in Sn. Fig. 12. High Resolution SEM micrograph of Sn–Ag thin film obtained on copper pads using electroless plating. elemental analysis was Sn Ag by wt% and is shown in Fig. 11. Because the coating is deposited chemically as compared to electrolytic plating, the problems normally associated with electroplating like edge build-up, uneven thickness, no plating in corners and recesses etc. are generally not observed with electroless plating. As can be seen from the SEM micrograph (Fig. 12), nano-grained films were achieved with relative ease with controlled compositions. This technique can be extended to ternary systems by manipulating the bath composition. 1) Demonstration of Bonding: The bonding capability of the thin lead free alloy films obtained by the electroless plating technique was evaluated in this part of the work. Lead-free solder films were electroless plated on an organic laminate (FR-4). The interconnection fabrication on the wafer side is discussed in a previous publication [8]. These thin bonding films can provide the mechanical and electrical interface between the interconnections and metal pads on the substrate. A thin coating of flux (9171, Alfa Metals) was deposited by spin coating on the lead free alloy film on metal pads before bonding. Bonding is achieved by applying pressure to the chip for less than 10 s, while the reflow temperature was kept at 250 C. Such a bond can possibly allow subsequent removal of the chip by locally heating the bonding interface. Fig. 13 shows the interconnections bonded on to an organic substrate using the electroless deposited lead free solder bonding interface. This demonstrates a 10 m interconnection between the chip and an organic substrate with a 1–2 m bonding interface. Certain minimal thickness of the bonding interface can enable reworkability by removing the chip. The coplanarity of the package and the uniformity in the interconnection height across the whole die are critical for ensuring the yield of such short interconnections with thin bonding layers. The sol-gel Sn–Ag–Cu film reduction was demonstrated to occur at 400 C. However, in order to be compatible with low loss polymers, stress buffer polymers such as BCB, silicones etc. the interconnections need to be formed at lower temperatures ( 300 C). This is a significant challenge for advanced wafer-level interconnections that various groups are exploring (examples: Sintered copper [9], carbon nanotubes [10], and [11]). For the sol-gel process, the strategies outlined in this work can bring in considerable reduction in the process temperatures and lead to ternary alloy films that cannot be easily plated. Further, incorporation of dopants to prevent grain coarsening, strengthening agents in the solder can be better accomplished with the sol-gel route. Development of new solder materials has been reported by microalloying of grain refining elements into Sn–Ag and Sn–Cu–Ag systems to achieve better mechanical properties. Presence of certain elements can lead to precipitation strengthening in the solder [12]. Introduction of additives might also prevent grain boundary sliding during steady-state creep and hence increase its creep strength although it might be at the expense of creep ductility. Inert, hybrid inorganic/organic, nano structured chemicals, were incorporated into low melting metallic materials, such as lead-free electronic solders were evaluated to achieve improved mechanical performance at elevated temperatures and service reliability of lead-free electronic solders. Organic derived nano reinforcements with appropriate functional groups to promote bonding with the metallic matrix efficiently pinned the grain boundary of solder alloys leading to the improvement in properties [13]. This technology can be easily implemented with the sol-gel route. 492 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 3, SEPTEMBER 2007 On the other hand, the process temperature is much lower with electroless plating. Electroless plating has unique advantages compared to electrolytic plating because of its selective pad deposition that can eliminate the lithography steps. With proper bath formulation, this process can be extended to ternary alloys. IV. CONCLUSION Sol-gel and electroless processes were successfully developed and demonstrated towards thin film (200 nm) bonding interfaces between metallic pads. Although sol-gel synthesis results in molecular level mixing of controlled compositions leading to homogeneous alloy compositions, it is time consuming and expensive when compared with electroless method. Electroless plating, which involves low temperature formation of metal nanoparticles and metallic films, from direct solution reduction of precursors is more attractive alternative in contrast to hydrogen reduction of the corresponding metal oxides. Solution reduction provides significant advantages as compared to sol-gel and other processes in terms of lower processing temperature and selective deposition of the alloy film on the metal pads. The ultimate goal of this research is to develop new paradigms in IC packaging and assembly technologies by means of nano-structured interconnect formation and a reworkable bonding process using nano-dimensional solder films. Solution-derived nano-solder technology is an attractive low-cost method for several applications such as MEMS hermetic packaging, wafer-wafer bonding, compliant interconnect bonding, and bump-less interconnects. REFERENCES [1] C. Jorgensen, “Lead-free electronics: Full steam ahead,” Surf. Mount Technol., May 2000 [Online]. Available: http://smt.pennnet.com/Articles/ [2] C. M. Garner, V. Gupta, V. Bissessur, A. Kumar, and R. Aspandiar, “Challenges in converting to lead-free electronics,” in Proc. Electron. Packag. Technol. Conf., 2000, pp. 6–9. [3] C. J. Brinker and G. W. Scherer, Sol-Gel Science: The Physics and Chemistry of Sol-Gel Processing. New York: Academic, 1990. [4] S. Komarineni, I. R. Abothu, and A. V. Prasada Rao, “Sol-Gel processing of some electroceramic powders,” J. Sol-Gel Sci. Technol., vol. 15, pp. 263–263, 1999. [5] L. L. Ye, Z. H. Lai, J. Liu, and A. Thölen, “Effect of Ag particle size on electrical conductivity of isotropically conductive adhesives,” in Proc. Imaps/IEEE CPMT 4th Symp. Mater. Electron. Packag., Braselton, GA, 1999, p. 262. [6] “ASM Hand Book,” ASM International, The Materials Information Society, 2007, p. 122, 9th ed.. [7] L. B. Pankratz, Thermodynamic Properties of Elements and Oxides. Washington, DC: U.S. Dept. Int. Bur. Mines Bull., 1982, p. 672. [8] A. O. Aggarwal, P. M. Raj, and R. R. Tummala, “High aspect ratio metal-polymer composite structures for nanointerconnects,” in Proc. 9th Int. Symp. Adv. Packag. Mater., Atlanta, GA, Mar. 2004, pp. 182–186. [9] W. V. Kwan, V. Kripesh, M. K. Gupta, A. A. O. Tay, and R. R. Tummala, “Low temperature sintering process for deposition of nanostructured metal for nano IC packaging,” in Proc. 5th Electron. Packag. Technol. Conf., Piscataway, NJ, 2003, pp. 551–556. [10] M. A. Guillorn, T. E. McKnight, A. Melechko, V. I. Merkulov, P. F. Britt, D. F. Austin, and D. H. Lowndes, “Individually addressable vertically aligned carbon nanofiber-based electrochemical probes,” J. Appl. Phys., vol. 91, no. 6, p. 3824, Mar. 2002. [11] L. Zhu, Y. Sun, J. Xu, Z. Zhang, D. W. Hess, and C. P. Wong, “Aligned carbon nanotubes for electrical interconnect and thermal management,” in Proc. Electron. Comp. Technol. Conf., 2004, pp. 44–50. [12] K. M. Kumar and A. A. O. Tay, “Nano-particle reinforced solders for fine pitch applications,” in Proc. 6th Electron. Packag. Technol. Conf., Dec. 2004, pp. 455–461. [13] A. Lee, K. N. Subramanian, and J.-G. Lee, “Development of nanocomposite lead-free electronic solders,” in Proc. 10th Int. Symp. Adv. Packag. Mater.: Process, Prop. Interf., Irvine, CA, Mar. 16–18, 2005, pp. 276–281. Ankur O. Aggarwal received the B.Tech (with honors) degree in ceramic engineering from Banaras Hindu University, Varanasi, India and the Ph.D. degree in materials science from the Georgia Institute of Technology, Atlanta. He is a Process Engineer with the C4 Group, Logic Technology Development (LTD), Intel Corporation, Hillsboro, OR. He has authored three U.S. patents and several publications in refereed journals and conferences. His interests are in novel packaging technologies for next-generation microprocessors.. Dr. Aggarwal received the Undergraduate Research Fellowship from the Indian Academy of Sciences and several Best Paper Awards in the field of microsystems packaging. Isaac R. Abothu received the M.S. degree in materials from Pennsylvania State University (Penn State), University Park and the Ph.D. degree in chemistry from Andhra University, Pradesh, India, in 1994. He is a Research Scientist with the Packaging Research Center (PRC), Georgia Institute of Technology (Georgia Tech), Atlanta. Prior to joining the PRC, was a Research Associate with the Institute of Materials Research and Engineering (IMRE), Singapore, MRL-Pennsylvania State University, Rutgers University, and Washington State University. He is an expert in Sol-gel Technology and has over 15 years research experience in thin film fabrication, ceramics, fibers, and coatings. At Penn State, he co-developed new “Nanocomposite Process” for electroceramics. He is author and/or co-author of over 30 publications in reputed peer reviewed international journals, Guest Editor of one of the issues of Thin Solid Films Journal and presented over 40 technical papers, three U.S. patents in pending along with several invention disclosures filed at Georgia Tech. Since joining the PRC in 2001, he has focused in the area of fabrication of high-k embedded capacitors on printed wiring board (PWB) and development of solution-derived nano lead-free solders for reworkable interconnects as a viable technology to meet the future needs in IC assembly. Dr. Abothu received the Best Paper Award at IMAPS’03, the Distinguished Alumni Award from MRL, Penn State, four International Achievement Awards from Penn State (1996–1999), the prestigious national Overseas Award from the Indian Government for his excellence in scientific research and meritorious in academics in 1992, and several Best Paper Awards in his field of research. He has been serving as Peer Reviewer for some international journals on the science and chaired and organized several international conferences. He has been serving as one of the executive committee members for emerging technologies session at the Electronics Components Technology Conference (ECTC) since 2004. P. Markondeya Raj received the B.S. degree from the Indian Institute of Technology, Kanpur, India, in 1993, the M.E. degree from the Indian Institute of Science, Bangalore, India, in 1995, and the Ph.D. degree in ceramic engineering from Rutgers University, Piscataway, NJ, in 1999. He is Assistant Research Director at the Packaging Research Center, Georgia Institute of Technology (Georgia Tech), Atlanta. He coauthored three books and over 100 publications and has four patents pending. His research expertise spans from functional thin films (sensors, capacitors, antennas, inductors), MEMS components (tunable capacitors), packaging substrates, thermomechanical reliability, device and system integration. He managed and led several government and industry funded programs in these areas. Dr. Raj received seven Best Paper Awards for his conference and journal publications which include the Distinguished Scholar Award from the Microbeam Analysis Society and the IEEE TRANSACTIONS ON ADVANCED PACKAGING Commendable Paper Award, the IEEE Outstanding Technical Paper Award, and the Philips Best Paper Award. AGGARWAL et al.: LEAD-FREE SOLDER FILMS Michael D. Sacks, photograph and biography not available at the time of publication. 493 Rao R. Tummala (F’94) received the B.E. degree in metallurgical engineering from the Indian Institute of Science, Bangalore, and the M.S. degree in metallurgical engineering and the Ph.D. degree in materials science and engineering from the University of Illinois, Chicago, in 1969. He is a Distinguished and Endowed Chair Professor, and Director of NSF ERC, Georgia Institute of Technology (Georgia Tech) Atlanta, pioneering system-on-package (SOP) vision. Prior to joining Georgia Tech, he was an IBM Fellow, pioneering such major technologies as the first flat panel display based on gas discharge , the first and next three generations of multichip packaging based on 35- layer alumina and 61-layer LTCC with copper and copper-polymer thin film, and materials for ink-jet printing and magnetic storage. He published 375 technical papers and holds 71 patents and inventions. He authored the first modern packaging reference book Microelectronics Packaging Handbook (New York: Van Nostrand, 1988) and the first textbook Fundamentals of Microsystems Packaging (New York: McGraw Hill, 2001). Dr. Tummala received numerous awards including Industry Week’s Award for Improving U.S. Competitiveness, IEEE ’s David Sarnoff and Major Education awards, Dan Hughes Award from IMAPS, the Engineering Materials Achievement Award from DVM and ASM-International, the Total Excellence in Manufacturing Award from SME, the John Jeppson’s Award from the American Ceramic Society as well as the Distinguished Alumni Awards from the University of Illinois, the Indian Institute of Science, and Georgia Tech. He is a Fellow of IMAPS and the American Ceramics Society, and a Member of the National Academy of Engineering. He was the President of the IEEE CPMT Society and the IMAPS Society.