dream, an ordeal, and ultimately, collaboration. It was accomplished with the support of many peo... more dream, an ordeal, and ultimately, collaboration. It was accomplished with the support of many people, who were indispensable for the realization of this thesis. I would like to acknowledge them in full for their support, comments, discussions, time and energy. I am ever grateful to scores of my friends who provided such a rich quilt of anecdotes, memories and insights for me to carry on with my work. • To my advisor, Prof. Rao Tummala, who always set high goals for me and continuously encouraged me to achieve them. From a research perspective, his insight and long-term vision have greatly influenced my research as well as thought process. On a personal note, his support and enthusiasm have been inspirational and working for him has been a wonderful experience.
53rd Electronic Components and Technology Conference, 2003. Proceedings.
This research focuses on evolving the best possible criteria for selecting high electrical perfor... more This research focuses on evolving the best possible criteria for selecting high electrical performance 100 micron pitch lead free solder bumping process. This is achieved through modeling and simulating the pad, process, reliability and test strategy. Coplanar waveguides (CPW) were modeled to evolve process criteria for pad design and choice of materials. Polyimide was chosen as the passivation on the chip. Further signal parasitics were studied for the passivation and a selection criterion was evolved for its thickness. The pad and the passivation layers were studied for dielectric loss when subjected to thermal c y c h g (air to ai). This evaluation leads to the selection of the hest pad contigumtion for lead free solder. An in-depth study on how internal resistance of the solder contributes to the change in parasitics is presented through numerical and simulated models. Standard under hump metallurgy (UBM) was used on the pads. Lead free solder (Sn3.5Ag0.3Cu) was chosen as the bumping material. Bumping strategy was evolved by which solder can be deposited on the UBM without stencil printing or electroplating. Flip chip B-stage underfill was also evaluated for wafer level application and standardized. This paper concludes by suggesting the hest design, process and reliability criteria which should be adopted for lead free solder 100 pm pitch flip-chip.
Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003)
As Microsystems continue to move towards higher speed and microminiaturization, the demand for in... more As Microsystems continue to move towards higher speed and microminiaturization, the demand for interconnection density both on the IC and the package increases tremendously. With the shift towards nano ICs by 2004 with cl00 nm feature sizes, the area array U 0 pitch will move towards 20-100 micron in the future. The 2002 ITRS Roadmap Update identifies the need to support sub-IOOpm pitch flip-chipiWLP and data rates of IOGbps in the package and board by the year 2010. The PRC and IMEiNUS are developing 20-100pm pitch interconnects as part of the A*STAR nano-WLP program. A critical part of this development involves hoard technology to simultaneously support wiring density to direct attach of these WLPs and high speed signals. The choice of base substrate and thin film dielectric is critical to meet the electrical performance targets and achieve reliable assembly of fine pitch WLPs. Modeling revealed that a low CTE substrate greatly enhances the reliability of all the interconnect solutions being pursued. The fabrication process was done on 30Ommx300mm and 300mmx450mm panel sizes using state-of-the-art printed wiring board and microvia processes. Data rates of 5Gbps on board have been demonstrated for line lengths of lOcm using A-PPE dielectric. Fine pitch routing using 20pm lines and spaces on Hitachi E-679F low CTE laminate to support 200pm pitch pads have been demonstrated. Initial substrates for 100pm pitch have also been designed and fabricated.
Page 1. ', ; New Paradigm in IC-Package Interconnections by Reworkable Nano-Interconnects An... more Page 1. ', ; New Paradigm in IC-Package Interconnections by Reworkable Nano-Interconnects Ankur 0. Aggarwal, P. Markondeya Raj, Isaac R. Abothu, Michael D. Sacks*, Andrew A.0 Tayt, Rao R. Tummala NSF Microsystems ...
IEEE Transactions on Components and Packaging Technologies, 2007
We report two novel routes, sol-gel and electroless plating, for the synthesis of lead-free solde... more We report two novel routes, sol-gel and electroless plating, for the synthesis of lead-free solders. Novel processes with these routes were developed and demonstrated for SnAg -Cu, SnAg systems to achieve thin bonding layers for assembly of fine pitch integrated circuits onto substrates. Sol-gel route can be used to accurately control the final alloy composition and incorporate additives leading to the designed thermomechanical properties. In this process, the inorganic polymer solutions were spin coated and then heat-treated in a reducing atmosphere to form thin films of lead-free solders. The presence of Ag and Cu enabled easy reduction of tin oxide to tin at 400 C that was not possible with Sn precursor. With the alternate solution reduction (electroless plating) approach, bonding layers can be deposited at almost room temperatures directly on organic substrates. With this approach, the deposition selectively occurs on the metal bonding pads, which eliminates the need for any lithography. Using this approach, electroless SnAg films were demonstrated on organic laminates. These thin film synthesis routes can enable short interconnections that are critical for high density, high frequency, and embedded active component packaging. Index Terms-Integrated circuits (ICs), laminates, SnAg films. I. INTRODUCTION M INIATURIZATION of high speed digital and high frequency wireless systems is driving the chip-package interconnections from the bulky solders of today to thin solder film based bonding with minimal electrical parasitics (, , and) in the near future (Fig. 1). High input/output (I/O) density multicore architectures for digital applications and ultrathin RF modules are pushing the off-chip interconnections to ultrafine pitch with minimal stand-off height. Along with added functionality and miniaturization trends, electronics is also moving towards greener and more environmentally friendly products. In the near future, consumers want a product which has a proven smaller impact on the environent, through ecological labeling and recycling considerations.
Page 1. Ultra Fine-Pitch Wafer Level Packaging with Reworkable Composite Nano-Interconnects Ankur... more Page 1. Ultra Fine-Pitch Wafer Level Packaging with Reworkable Composite Nano-Interconnects Ankur 0. Aggarwal, P. Markondeya Raj, Michael D. Sacks', Andrew AO Tay', Rao R. Tummala Microsystems Packaging Research ...
... Ankur 0. Aggarwal, P. Markondeya Raj, Rana J. Pratap, Ashok Saxena, Rao R. Tummala Microsyste... more ... Ankur 0. Aggarwal, P. Markondeya Raj, Rana J. Pratap, Ashok Saxena, Rao R. Tummala Microsystems Packaging Research Center Georgia Institute of Technology, Atlanta, GA 30332 Tel: (404) 385-2234, Fax: (404) 894-9140, Email: [email protected]http://www. ...
56th Electronic Components and Technology Conference 2006
Copper is an excellent candidate material for next generation of chip-package interconnections be... more Copper is an excellent candidate material for next generation of chip-package interconnections because of its high electrical and thermal conductivities, good mechanical properties at assembly and operating temperatures and well-established infrastructure to integrate with back-end processes with electroplating technology downscalable to nanoscale. This technology can also accommodate the increasing I/O density of future microprocessors with the best electrical and mechanical
2007 Proceedings 57th Electronic Components and Technology Conference, 2007
This paper reports the reliability of fine pitch interconnections using nano-structured nickel as... more This paper reports the reliability of fine pitch interconnections using nano-structured nickel as the primary interconnection material. Assembly was accomplished with different bonding methods to provide organic compatible lowtemperature fabrication. Au-Sn and Sn-Cu were used for solder-based assembly of nanonickel interconnections. Low modulus conductive adhesives impart lower stresses in the interconnections and enhance reliability though they add electrical parasitics. These were used as an alternate bonding route and compared to solders. Test vehicles were fabricated at 200 micron pitch to evaluate the reliability with different bonding routes. Different CTE substrates-FR4 with 18 ppm/C, advanced organic boards with 10 ppm/C, novel low CTE (3 ppm/C) substrates based on Carbon-Silicon Carbide (C-SiC) were evaluated. No underfilling was used in all the test vehicles evaluated in this study. High frequency electrical characterization was performed to compare the electrical parasitics from different bonding routes. Nanometal bumps bonded with conductive adhesives showed the highest reliability withstanding 1500 cycles. This technology can be easily downscaled to submicron and nanoscale unlike the current solder technologies leading to true nanointerconnections.
Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003)
... Ankur 0. Aggarwal, Isaac R. Abothu, P. Markondeya Raj, D. Ravi, Michael D. Sacks*, Andrew 0. ... more ... Ankur 0. Aggarwal, Isaac R. Abothu, P. Markondeya Raj, D. Ravi, Michael D. Sacks*, Andrew 0. Tay', Rao R. Tummala NSF Microsystems Packaging Research Center Georgia Institute of Technology, Atlanta, GA 30332 Tel: (404) 894-1250, Fax: (404) 894-9140, Email: ankur ...
IEEE Transactions on Electronics Packaging Manufacturing, 2008
Interconnect technologies between ICs and packages or boards have a significant impact on the IC ... more Interconnect technologies between ICs and packages or boards have a significant impact on the IC performance and packaging density. Today, the interconnections are typically accomplished with either wire bonding or flip-chip solders. While both of these technologies are incremental, they also run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect might not satisfy the thermomechanical reliability requirements at very fine-pitches. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. This paper reports fine-pitch interconnection technologies using nano-structured nickel as primary interconnection material. The nano-grained nickels are produced by electroplating process. The primary nano-structured interconnects are assembled with different bonding methods to provide organic compatible low-temperature fabrication. Au-Sn and Sn-Cu are used for solder-based assembly of nano-nickel interconnections. Low modulus anisotropic conductive films (ACFs) are also used as an alternate bonding route of the solders. No underfilling is used in all the interconnect structures evaluated in this paper. Assembly are accomplished on different coefficient of thermal expansion (CTE) substrates including FR-4 with 18 ppm C, advanced organic substrates with 10 ppm C, novel low CTE (3 ppm C) substrates based on Carbon-Silicon Carbide (C-SiC). The thermomechanical reliability of all the nano-interconnects assembled on different CTE substrates with different bonding approaches is evaluated by thermal shock testing and finite-element analysis. Nano-nickel interconnects bonded with the ACF showed the highest reliability withstanding 1500 cycles. In all cases, no apparent failure was observed in the primary nano-nickel metal interconnects. This technology is expected to be easily downscaled to submicrometer and nano-scale unlike the current solder technologies leading to true nano-interconnections.
The decrease in feature sizes of microelectronic devices has underlined the need for higher numbe... more The decrease in feature sizes of microelectronic devices has underlined the need for higher number of input-outputs (I/Os) in order to increase its functionality. This has spurred a great interest in developing electronic packages with fine and ultra fine pitches (20-100 m). Most of the compliant interconnects that are currently being developed have inductance and resistance higher than desirable. This paper presents a novel low-temperature fabrication process that combines polymer structures with electroless copper plating to create low stress composite structures for extremely fine-pitch wafer level packages. Analytical models for these structures justify the stress reduction at the interfaces and superior reliability as integrated circuit (IC)-package interconnects. Low coefficient of thermal expansion (CTE) polyimide structures with ultra-low stress, high toughness, and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80. The etching process also leads to roughened sidewalls for selective electroless copper plating on the sidewalls of polymer structures. This work also describes a selective electroless plating synthesis route to develop thin IC-package bonding interfaces with lead-free solder. Lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents at 45 C. The lead-free solder composition was controlled by altering the plating bath formulation. Solder film formed from the above approach was demonstrated to bond the metal-coated polymer interconnects with the copper pads on the substrate using a standard reflow process. Metal-coated polymer structures in conjunction with the thin solder bonding films can provide low-cost high-performance solutions for wafer-level packaging. Index Terms-Composite, interconnections, low stress, polymer column, stress relief, wafer level packaging. I. INTRODUCTION A S MICROPROCESSOR performance increases, the technical challenges escalate in the areas of power delivery, heat removal, input-output (I/O) density, and thermo-mechanical reliability. Short and reliable interconnections are also becoming very critical for the emerging need of thin mixed signal
dream, an ordeal, and ultimately, collaboration. It was accomplished with the support of many peo... more dream, an ordeal, and ultimately, collaboration. It was accomplished with the support of many people, who were indispensable for the realization of this thesis. I would like to acknowledge them in full for their support, comments, discussions, time and energy. I am ever grateful to scores of my friends who provided such a rich quilt of anecdotes, memories and insights for me to carry on with my work. • To my advisor, Prof. Rao Tummala, who always set high goals for me and continuously encouraged me to achieve them. From a research perspective, his insight and long-term vision have greatly influenced my research as well as thought process. On a personal note, his support and enthusiasm have been inspirational and working for him has been a wonderful experience.
53rd Electronic Components and Technology Conference, 2003. Proceedings.
This research focuses on evolving the best possible criteria for selecting high electrical perfor... more This research focuses on evolving the best possible criteria for selecting high electrical performance 100 micron pitch lead free solder bumping process. This is achieved through modeling and simulating the pad, process, reliability and test strategy. Coplanar waveguides (CPW) were modeled to evolve process criteria for pad design and choice of materials. Polyimide was chosen as the passivation on the chip. Further signal parasitics were studied for the passivation and a selection criterion was evolved for its thickness. The pad and the passivation layers were studied for dielectric loss when subjected to thermal c y c h g (air to ai). This evaluation leads to the selection of the hest pad contigumtion for lead free solder. An in-depth study on how internal resistance of the solder contributes to the change in parasitics is presented through numerical and simulated models. Standard under hump metallurgy (UBM) was used on the pads. Lead free solder (Sn3.5Ag0.3Cu) was chosen as the bumping material. Bumping strategy was evolved by which solder can be deposited on the UBM without stencil printing or electroplating. Flip chip B-stage underfill was also evaluated for wafer level application and standardized. This paper concludes by suggesting the hest design, process and reliability criteria which should be adopted for lead free solder 100 pm pitch flip-chip.
Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003)
As Microsystems continue to move towards higher speed and microminiaturization, the demand for in... more As Microsystems continue to move towards higher speed and microminiaturization, the demand for interconnection density both on the IC and the package increases tremendously. With the shift towards nano ICs by 2004 with cl00 nm feature sizes, the area array U 0 pitch will move towards 20-100 micron in the future. The 2002 ITRS Roadmap Update identifies the need to support sub-IOOpm pitch flip-chipiWLP and data rates of IOGbps in the package and board by the year 2010. The PRC and IMEiNUS are developing 20-100pm pitch interconnects as part of the A*STAR nano-WLP program. A critical part of this development involves hoard technology to simultaneously support wiring density to direct attach of these WLPs and high speed signals. The choice of base substrate and thin film dielectric is critical to meet the electrical performance targets and achieve reliable assembly of fine pitch WLPs. Modeling revealed that a low CTE substrate greatly enhances the reliability of all the interconnect solutions being pursued. The fabrication process was done on 30Ommx300mm and 300mmx450mm panel sizes using state-of-the-art printed wiring board and microvia processes. Data rates of 5Gbps on board have been demonstrated for line lengths of lOcm using A-PPE dielectric. Fine pitch routing using 20pm lines and spaces on Hitachi E-679F low CTE laminate to support 200pm pitch pads have been demonstrated. Initial substrates for 100pm pitch have also been designed and fabricated.
Page 1. ', ; New Paradigm in IC-Package Interconnections by Reworkable Nano-Interconnects An... more Page 1. ', ; New Paradigm in IC-Package Interconnections by Reworkable Nano-Interconnects Ankur 0. Aggarwal, P. Markondeya Raj, Isaac R. Abothu, Michael D. Sacks*, Andrew A.0 Tayt, Rao R. Tummala NSF Microsystems ...
IEEE Transactions on Components and Packaging Technologies, 2007
We report two novel routes, sol-gel and electroless plating, for the synthesis of lead-free solde... more We report two novel routes, sol-gel and electroless plating, for the synthesis of lead-free solders. Novel processes with these routes were developed and demonstrated for SnAg -Cu, SnAg systems to achieve thin bonding layers for assembly of fine pitch integrated circuits onto substrates. Sol-gel route can be used to accurately control the final alloy composition and incorporate additives leading to the designed thermomechanical properties. In this process, the inorganic polymer solutions were spin coated and then heat-treated in a reducing atmosphere to form thin films of lead-free solders. The presence of Ag and Cu enabled easy reduction of tin oxide to tin at 400 C that was not possible with Sn precursor. With the alternate solution reduction (electroless plating) approach, bonding layers can be deposited at almost room temperatures directly on organic substrates. With this approach, the deposition selectively occurs on the metal bonding pads, which eliminates the need for any lithography. Using this approach, electroless SnAg films were demonstrated on organic laminates. These thin film synthesis routes can enable short interconnections that are critical for high density, high frequency, and embedded active component packaging. Index Terms-Integrated circuits (ICs), laminates, SnAg films. I. INTRODUCTION M INIATURIZATION of high speed digital and high frequency wireless systems is driving the chip-package interconnections from the bulky solders of today to thin solder film based bonding with minimal electrical parasitics (, , and) in the near future (Fig. 1). High input/output (I/O) density multicore architectures for digital applications and ultrathin RF modules are pushing the off-chip interconnections to ultrafine pitch with minimal stand-off height. Along with added functionality and miniaturization trends, electronics is also moving towards greener and more environmentally friendly products. In the near future, consumers want a product which has a proven smaller impact on the environent, through ecological labeling and recycling considerations.
Page 1. Ultra Fine-Pitch Wafer Level Packaging with Reworkable Composite Nano-Interconnects Ankur... more Page 1. Ultra Fine-Pitch Wafer Level Packaging with Reworkable Composite Nano-Interconnects Ankur 0. Aggarwal, P. Markondeya Raj, Michael D. Sacks', Andrew AO Tay', Rao R. Tummala Microsystems Packaging Research ...
... Ankur 0. Aggarwal, P. Markondeya Raj, Rana J. Pratap, Ashok Saxena, Rao R. Tummala Microsyste... more ... Ankur 0. Aggarwal, P. Markondeya Raj, Rana J. Pratap, Ashok Saxena, Rao R. Tummala Microsystems Packaging Research Center Georgia Institute of Technology, Atlanta, GA 30332 Tel: (404) 385-2234, Fax: (404) 894-9140, Email: [email protected]http://www. ...
56th Electronic Components and Technology Conference 2006
Copper is an excellent candidate material for next generation of chip-package interconnections be... more Copper is an excellent candidate material for next generation of chip-package interconnections because of its high electrical and thermal conductivities, good mechanical properties at assembly and operating temperatures and well-established infrastructure to integrate with back-end processes with electroplating technology downscalable to nanoscale. This technology can also accommodate the increasing I/O density of future microprocessors with the best electrical and mechanical
2007 Proceedings 57th Electronic Components and Technology Conference, 2007
This paper reports the reliability of fine pitch interconnections using nano-structured nickel as... more This paper reports the reliability of fine pitch interconnections using nano-structured nickel as the primary interconnection material. Assembly was accomplished with different bonding methods to provide organic compatible lowtemperature fabrication. Au-Sn and Sn-Cu were used for solder-based assembly of nanonickel interconnections. Low modulus conductive adhesives impart lower stresses in the interconnections and enhance reliability though they add electrical parasitics. These were used as an alternate bonding route and compared to solders. Test vehicles were fabricated at 200 micron pitch to evaluate the reliability with different bonding routes. Different CTE substrates-FR4 with 18 ppm/C, advanced organic boards with 10 ppm/C, novel low CTE (3 ppm/C) substrates based on Carbon-Silicon Carbide (C-SiC) were evaluated. No underfilling was used in all the test vehicles evaluated in this study. High frequency electrical characterization was performed to compare the electrical parasitics from different bonding routes. Nanometal bumps bonded with conductive adhesives showed the highest reliability withstanding 1500 cycles. This technology can be easily downscaled to submicron and nanoscale unlike the current solder technologies leading to true nanointerconnections.
Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003)
... Ankur 0. Aggarwal, Isaac R. Abothu, P. Markondeya Raj, D. Ravi, Michael D. Sacks*, Andrew 0. ... more ... Ankur 0. Aggarwal, Isaac R. Abothu, P. Markondeya Raj, D. Ravi, Michael D. Sacks*, Andrew 0. Tay', Rao R. Tummala NSF Microsystems Packaging Research Center Georgia Institute of Technology, Atlanta, GA 30332 Tel: (404) 894-1250, Fax: (404) 894-9140, Email: ankur ...
IEEE Transactions on Electronics Packaging Manufacturing, 2008
Interconnect technologies between ICs and packages or boards have a significant impact on the IC ... more Interconnect technologies between ICs and packages or boards have a significant impact on the IC performance and packaging density. Today, the interconnections are typically accomplished with either wire bonding or flip-chip solders. While both of these technologies are incremental, they also run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect might not satisfy the thermomechanical reliability requirements at very fine-pitches. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. This paper reports fine-pitch interconnection technologies using nano-structured nickel as primary interconnection material. The nano-grained nickels are produced by electroplating process. The primary nano-structured interconnects are assembled with different bonding methods to provide organic compatible low-temperature fabrication. Au-Sn and Sn-Cu are used for solder-based assembly of nano-nickel interconnections. Low modulus anisotropic conductive films (ACFs) are also used as an alternate bonding route of the solders. No underfilling is used in all the interconnect structures evaluated in this paper. Assembly are accomplished on different coefficient of thermal expansion (CTE) substrates including FR-4 with 18 ppm C, advanced organic substrates with 10 ppm C, novel low CTE (3 ppm C) substrates based on Carbon-Silicon Carbide (C-SiC). The thermomechanical reliability of all the nano-interconnects assembled on different CTE substrates with different bonding approaches is evaluated by thermal shock testing and finite-element analysis. Nano-nickel interconnects bonded with the ACF showed the highest reliability withstanding 1500 cycles. In all cases, no apparent failure was observed in the primary nano-nickel metal interconnects. This technology is expected to be easily downscaled to submicrometer and nano-scale unlike the current solder technologies leading to true nano-interconnections.
The decrease in feature sizes of microelectronic devices has underlined the need for higher numbe... more The decrease in feature sizes of microelectronic devices has underlined the need for higher number of input-outputs (I/Os) in order to increase its functionality. This has spurred a great interest in developing electronic packages with fine and ultra fine pitches (20-100 m). Most of the compliant interconnects that are currently being developed have inductance and resistance higher than desirable. This paper presents a novel low-temperature fabrication process that combines polymer structures with electroless copper plating to create low stress composite structures for extremely fine-pitch wafer level packages. Analytical models for these structures justify the stress reduction at the interfaces and superior reliability as integrated circuit (IC)-package interconnects. Low coefficient of thermal expansion (CTE) polyimide structures with ultra-low stress, high toughness, and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80. The etching process also leads to roughened sidewalls for selective electroless copper plating on the sidewalls of polymer structures. This work also describes a selective electroless plating synthesis route to develop thin IC-package bonding interfaces with lead-free solder. Lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents at 45 C. The lead-free solder composition was controlled by altering the plating bath formulation. Solder film formed from the above approach was demonstrated to bond the metal-coated polymer interconnects with the copper pads on the substrate using a standard reflow process. Metal-coated polymer structures in conjunction with the thin solder bonding films can provide low-cost high-performance solutions for wafer-level packaging. Index Terms-Composite, interconnections, low stress, polymer column, stress relief, wafer level packaging. I. INTRODUCTION A S MICROPROCESSOR performance increases, the technical challenges escalate in the areas of power delivery, heat removal, input-output (I/O) density, and thermo-mechanical reliability. Short and reliable interconnections are also becoming very critical for the emerging need of thin mixed signal
Uploads
Papers by Ankur Aggarwal