Electrical & Computer Engineering

The performance of III-V heterojunction bipolar transistors (HBTs) has improved significantly over the past two decades. Today's state of the art Indium Phosphide (InP) HBTs have a maximum frequency of oscillation greater than 800 GHz and have been used to realize an amplifier operating above 600 GHz . In comparison to silicon (Si) based devices, III-V HBTs have superior transport properties that enables a higher gain, higher speed, and noise performance, and much higher Johnson figure- of-merit . From this perspective, the InP HBT is one of the most promising candidates for high performance mixed signal electronic systems.

A fast frequency sweep method for wideband antennas and infinite arrays based on a singular value decomposition (SVD)-Krylov model reduction method for frequency-domain tangential vector finite elements (TVFEMs) is presented. Reduced models are constructed using balanced congruence transformations constructed from the dominant invariant subspace of the system's Hankel matrix. Traditionally, forming such matrix requires the intensive computation of Gramians; the proposed method only forms their low-rank Cholesky factors via a novel adaptive proper orthogonal decomposition (POD) sampling strategy, leading to significant savings. Unlike some other model reduction methods,

Abstract Recent FPGA-based implementations of network virtualization represent a significant step forward in network performance and scalability. Although these systems have been shown to provide orders of magnitude higher performance than solutions using software-based routers, straightforward reconfiguration of hardware-based virtual networks over time is a challenge.

Abstract Network virtualization has emerged as a powerful technique to deploy novel services and experimental protocols over shared network infrastructures. Although recent research has highlighted field programmable gate arrays (FPGAs) as attractive platforms for high performance network virtualization, these devices remain inaccessible to the larger networking research community due to the absence of user-friendly programming models.

Abstract The constrained operating environments of many FPGA-based embedded systems require flexible security that can be configured to minimize the impact on FPGA area and power consumption. In this paper, a security approach for external memory in FPGA-based embedded systems that exploits FPGA configurability is presented. Our FPGA-based security core provides both confidentiality and integrity for data stored externally to an FPGA which is accessed by a processor on the FPGA chip.

System security is an increasingly important design criterion for many embedded systems. These systems are often portable and more easily attacked than traditional desktop and server computing systems. Key requirements for system security include defenses against physical attacks and lightweight support in terms of area and power consumption. Our new approach to embedded system security focuses on the protection of application loading and secure application execution.

Abstract Network virtualization presents a powerful approach to share physical network infrastructure among multiple virtual networks. Recent advances in network virtualization advocate the use of field-programmable gate arrays (FPGAs) as flexible high performance alternatives to conventional host virtualization techniques. However, the limited on-chip logic and memory resources in FPGAs severely restrict the scalability of the virtualization platform and necessitate the implementation of efficient forwarding structures in hardware.

Abstract Recent virtual network implementations have shown the capability to implement multiple network data planes using a shared hardware substrate. In this project, a new scalable virtual networking data plane is demonstrated which combines the performance efficiency of FPGA hardware with the flexibility of software running on a commodity PC.

Abstract Although soft microprocessors are widely used in FPGAs, limited work has been performed regarding how to automatically and efficiently generate soft multiprocessors. In this paper, an automated parallel compilation environment for multiple soft processors which incorporates parallel compilation and inter-processor communication structures is described.

Since our first report on terahertz detection by
bundles of single wall carbon nanotubes (SWCNTs) at the
ISSTT2008, we have fabricated a large number of additional
antenna-coupled SWCNT devices that all show terahertz
detection. The maximum voltage responsivity (SV) is about 25
V/W (intrinsic value 50 V/W) at 4.2 K, and SV decreases slowly
with temperature up to about 100 K. In this paper we further
explore different fabrication procedures and the bolometric
detection process. We also demonstrate diode type detection at
terahertz frequencies in SWCNTs for the first time. We present
results of circuit simulations and ab initio simulations of the
electronic properties of SWCNTs.

A central issue of nanoelectronics concerns their fundamental scaling limits, ie the smallest and most energy-efficient devices that can function reliably. Unlike charge-based electronics which are prone to leakage at nanoscale dimensions, memory devices based on phase change materials (PCMs) are more scalable, storing digital information as the crystalline or amorphous state of a material. Here, we describe a novel approach to self-align PCM nanowires with individual carbon nanotube (CNT) electrodes for the first time.

Abstract—In this paper we present a review of the progress that our group has done in the development of Carbon Nanotube based devices as THz detectors. We describe new techniques for fabrication of log periodic antennas, as well as for better control of the placement and selection of the CNTs.

Abstract We present new data on microwave detection in bundles of carbon nanotubes (CNTs). In particular, we derive a circuit model based on ANA measurements. We also demonstrate the first terahertz detection (up to 2.54 THz) in bundles of CNTs that were deposited through dielectrophoresis across the smallest gap in log-periodic antennas. Data are given that support the hypothesis that the detection process is bolometric at THz frequencies.

Reliable and scalable manufacturing of nanofabrics entails significant challenges. Scalable nano-manufacturing approaches that employ the use of lithographic masks in conjunction with nanofabrication based on self-assembly have been proposed. A bottom-up fabrication of nanoelectronic circuits is expected to be subject to various defects and identifying the types of defects that may occur during each step of a manufacturing pathway is essential in any attempt to achieve reliable manufacturing. This thesis aims at analyzing the sources of defects in a nanomanufacturing flow and estimating the resulting yield loss. It integrates physical fabric considerations, manufacturing sequences and the resulting defect scenarios. This is in contrast to most current approaches that use conventional defect models and assume constant defect rates without analyzing the manufacturing pathway to determine the sources of defects and their probabilities. The manufacturing pathway will be analyzed for identifying the defects introduced during each manufacturing step in the sequence, followed by yield loss estimation. vi

Various fault-tolerance techniques have been proposed in recent years to tolerate the high defect rates expected in emerging nanofabrics with unconventional nano-manufacturing techniques. The proposed techniques include modular redundancy schemes that use majority voters to vote on the '0' or 1' outputs of redundant modules. Novel nanoscale computational fabrics employ new circuit and logic styles where the likelihood of occurrence