185 questions
0
votes
1
answer
470
views
System Verilog assertion to verify that one signal is 2 clock cycle delayed version of the other
I have 2 inputs to my module, namely sig_1 and sig_2(both multi-bit). I want to check using assertions that whether sig_2 is a 2 clock cycle delayed version of sig_1, whenever sig1_1 changes.
i tried ...
0
votes
1
answer
127
views
Negating a sequence in SystemVerilog assertions
I have a reasonably basic SVA question, but I'm not sure what the trick is for getting somewhere. I'm trying to say that if A is true for 32 cycles, then B should become true at some point. ...
- 2,803
0
votes
1
answer
490
views
SVA for verifying that two signals are equivalent after some delays
I have an SVA question :
Let's say we have signal wpo, and 19-21 clocks cycles later, we have wpo(the value at time 0) == out. How to write an SVA for that.
I tried this but it doesn't work
logic [103:...
- 31
0
votes
0
answers
164
views
Evaluation at posedge of SVA assertions
I am trying to write a simple assertion in systemverilog like the following :
//Generate signal high during time where signals shouldn't change
always @(posedge FCLK) begin
if(cmd_typeA) begin
...
- 11
2
votes
1
answer
174
views
SVA assertion compile syntax errors
assert property @(posedge(clk)) !rstN |-> n==0 && full==0 && empty==1;
assert property @(posedge clk) disable iff(!rstN) ( full |=>(wr_en && $stable (n) ) );
assert ...
- 21
1
vote
1
answer
277
views
Assertion to check array contents for duplicate values
I have an array logic [254:0][7:0] array. By design, this array must consist all values from 0 to 254 exactly once.
I want to write a SystemVerilog assertion to test it.
So far, I came up with ...
- 1,124
0
votes
1
answer
443
views
64 Bit Complex Multiplier
This is the SystemVerilog code for 64 Bit Complex Multiplier
//
// SystemVerilog Project for EL Component of DSDV
// Author: Anudeep N Rao
// USN: 1RV22LVS01
//
module cmultx64
(
cmul_if if1
);
...
0
votes
1
answer
341
views
Signal Must Assert While Other Signal Is Asserted
I have a situation where a signal in a design must assert for at least one cycle while another signal is asserted for at least X cycles.
Desired Results:
Pass:
pass example 1
Pass:
pass example 2
Pass:...
- 3
-2
votes
1
answer
384
views
Why the assertion happens but its pass count is zero in the coverage result?
Consider the below code. The assert property is hit and passed according to the output but its pass count is zero in the coverage result. Why?
module tb;
reg Krdy;
reg Drdy;
reg EN;
...
- 1
2
votes
1
answer
1k
views
How do I disable assertions when signals are unknown?
I'm trying to understand a assertion in a MUX sample module.
I would like to check the interference between SEL1, SEL2 and SEL3 signals, So I declared as the below,
always @(posedge CLOCK)
assert (...
- 274
1
vote
1
answer
101
views
Parameter within module name
I'm writing a module assertion bind:
module top_assertion #(parameter WIDTH=8) (input rtl_signal);
axi_``WIDTH``_bus axi_bus;
assert property (@(posedge Clock) !$isunknown(axi_bus.valid);
endmodule
...
-1
votes
1
answer
388
views
Turning off assertion fail comments
I'm writing assertions to detect a particular sequence occurrence. In case the sequence is not not true, I get prints in log for assertion failure. But I just want to check if sequence occurred or not....
- 7
1
vote
1
answer
281
views
SystemVerilog assertion scheduling
A SystemVerilog assertion is latching the previous values even though the transition is detected.
I have the below property as part of the file. a and b are inputs whose width is 1-bit.
property ...
0
votes
1
answer
974
views
SystemVerilog assertion semantics & when to stop simulation [closed]
The vendor for the simulation tool I'm using (Cadence) has said that they must stop failing assertions at the time the assertion fails and not during the action blocks of the assertion. I prefer for ...
- 567
-2
votes
1
answer
828
views
Assertion writing without clock for async reset
I have two resets in my design. Reset_a and Reset_b. both are asynchronous reset can come at any pint of time.
i have to write assertion to check if Reset_a is asserted Reset_b also assert at any ...
-1
votes
2
answers
438
views
use System Verilog $past in clocking gate
p1: assert property (@(posedge clk) ($past(b, 2, c)) === 0);
when I run assert in VCS, it failed at 13s, 15s, 17s...
I don't know why it failed at 13s.
in 11s, $past(b, 2, c) is 0 (sampled at 7s)
but ...
- 1
0
votes
2
answers
637
views
SystemVerilog Assertion does not fail when it should
I have a simple assertion as follows:
$rose(req) |=> !req[*1:10] until ack ##1 !ack;
As I understand, on detection of $rose(req), the assertion should check for !req to be low consecutively for max ...
- 11
-1
votes
1
answer
1k
views
How to create an assertion that checks for if a signal is not high for more than 3 consecutive cycles?
I am trying to write an assertion for my SystemVerilog design which checks if a signal is never high for more than 3 cycles (implicitly it must be de-asserted eventually). My signal is called "...
-1
votes
1
answer
408
views
Checking the assertion of outputValid N cycles after the assertion of inputReady excluding the cycles when Enable is deasserted?
If there were no enable signal, inputReady ##N outputValid would do the job. But, how should I exclude the cycles when enable is deasserted? Is there a short solution?
- 1
1
vote
1
answer
2k
views
Meaning of |-> 1[0:$] in assertions
Usage example:
state==ACTIVE1 |-> 1[0:$] ##1 state==ACTIVE2
The problem the assertion is trying to solve is:
if the state machine reaches state=ACTIVE1, it will eventually reach state=ACTIVE2.
Any ...
- 97
0
votes
1
answer
427
views
Gate-level timing checks in SVA
I need to check the value of a signal after a certain amount of time a clock edge occurs. For example, I want to check that if signal b asserts to high 1ps after posedge clock occurs.
Does SVA provide ...
- 1,951
-1
votes
2
answers
1k
views
Scoreboard in UVM
What do we do when we have to create a scoreboard for a certain design logic? For a memory I understand that we can compare the data written to DUT at a certain address to the data read at the same ...
- 13
1
vote
1
answer
2k
views
How to sample covergroup at the occurence of a certain sequence?
module testbench;
bit [2:0] A;
bit [2:0] data[];
int i;
bit [2:0] b;
covergroup cov_grp;
c1 : coverpoint A {
bins b1 = {0,1,2};
bins b2 = {3,4,5};
bins b3 = {6,7};...
- 25
0
votes
1
answer
1k
views
How to check in SystemVerilog that signal went high during simulation using ModelSim
I need to check, whether during the testbenching the particular signal went at least for a single clock cycle to logic 1.
I've tested following asserts, which shall be equivalent:
initial assert ...
- 468
0
votes
3
answers
239
views
SV Assertion - Implication matches unique valid sequences
I have assertion property as
assert property P;
property P;
@(posedge clk) A |-> ##[1:5] B;
endproperty
clk - 0 1 2 3 4 5 6 7 8 9 10
A - 0 1 0 1 0 0 0 0 0 0 0
B - 0 0 0 0 1 0 0 1 0 0 0
Here ...
- 27
0
votes
1
answer
870
views
SVA Signal doesn't change while other one is true
This is very basic but I've been blocked the whole afternoon.
I need a property to check that if A is set, B cannot change.
_____________________
A ______/ \______________
...
- 36
1
vote
1
answer
395
views
How to use an input value with repetition operator?
How I can use a design input with the repetition operator in a SV assertion?
Basically, what I'm trying to implement is:
property ( ( disable iff((a) or (b) or (c) or (d))
$rose(req) |-> ...
- 11
1
vote
1
answer
642
views
Passing bus array to another module via port mapping
I have below code inside SV module where I instantiate another SV module and pass 5-bit bus to it to check for X and Z's as coded below:
input [4:0] analdo_trim;
cds_XZ_checker ...
- 455
0
votes
1
answer
628
views
Trouble with assertion for check for a variable not to change between a handshake signal
I am trying to create an assertion property that checks if a 16-bit variable num should not change between a valid from the master until we receive a ready from a slave
what I have so far is
property ...
0
votes
1
answer
2k
views
SystemVerilog property pass by reference
Is it possible to pass a signal to a property by reference? For example, I want to create a cover property to capture a register changing, and re-use this property for dozens of different registers. I'...
0
votes
1
answer
916
views
Understanding how exactly 'assert' works
I am facing a puzzling behavior of Systemverilog 'assert' when trying to verify a flip-flop had sampled the input value on a rising edge. It seems that the assert will pass if I add an arbitrarily ...
- 11
-1
votes
2
answers
823
views
recomend the way to write a monitor in UVM with defferent event polarity
I am trying to implement a monitor for VDU(Video display unit) and the way the VDU can be programmed says that sync signals have controllable polarity. This means than according to VDU settings ...
-1
votes
2
answers
2k
views
I want to add a checker that checks if clk is toggling when enable is '1'. The frequency of the clk is random (unknown)
Let's say we have a signal named "clk" and we want to make sure that clk toggles when "enable" is '1'. And the frequency of the "clk" is not known.
- 143
0
votes
1
answer
1k
views
SystemVerilog disable cover property after hit
I have a few cover property's that I expect to fire pretty frequently, and I'm seeing they are starting to impact my simulation performance because they are firing so frequently. I don't want to ...
0
votes
1
answer
369
views
sva event scheduling with $display/uvm_error
So I recall when an assertion triggers the data signals in the assertion are from just prior to the clock edge.
I'd like to put a helpful error message in my assertion to let the user know what went ...
- 3
0
votes
1
answer
181
views
SVA for the following protocol
I have to write a single SVA for the complete protocol shown in this image
I wrote the following SVA but it doesn't capture the immediate ack. How do I fix that
@(posedge clk)
$rose(val) |=>
...
0
votes
1
answer
7k
views
Why are "if..else" statements not encouraged within systemverilog assertion property?
I am writing an assertion check for the following structure
Basically, I want to check that output is equal to d1 when select signal is 0 and output is equal to d2 when select signal is 1.
I did ...
- 45
0
votes
1
answer
526
views
Using SVA, how can we write a property to check that we are not getting two req (req1 and req2) at the same time
Both req1 and req2 are asynchronous. And I want to check that at no point in the simulation, req2 is true while req1 is true. I have tried
property not_req2_while_req1;
@(negedge req1)
1 |->...
0
votes
1
answer
856
views
What is the difference between the symbol '->' and '|->' in System Verilog Assertion Properties
I have encountered an example property which works here:
property p_a;
@(posedge clk) $rose(a) -> $rose(b);
endproperty
There is no syntax error above.
Then I tried to modify to this
property ...
- 41
1
vote
1
answer
531
views
SystemVerilog always @ sequence
I want to create an always block that uses a sequence for the event control, but I'm not sure if that's allowed in SystemVerilog and I'm getting an internal compiler error when I try to do it. Here's ...
-1
votes
1
answer
598
views
Do System Verilog coverpoints and covergroups work for real variable types?
I'm looking into using coverpoints and covergroups for mixed signal verification in Cadence to verify some constrained random classes I've written. However, I haven't been able to find online if ...
- 1
0
votes
1
answer
494
views
How to specify sample delay in SystemVerilog covergroup
I need to sample signals in a cover group 1 nanosecond after posedge clock. What is the syntax to do that?
My MWE is as follows:
covergroup DEBUG_CG @ (posedge tb_clock);
debug_IR : coverpoint ...
- 1,951
0
votes
1
answer
4k
views
variable delay in assertions in System Verilog
I am a newbie learning System Verilog assertions and found a code online from verificationguide.com for variable delays in assertions. But I am unable to understand a few things.
Can someone ...
0
votes
2
answers
1k
views
Assertion for valid comes once in req-ack transaction
I want to write an assertion, which checks that "Valid should be high only once in req 1, ack 1, req 0, ack 0 transaction"
I thought of the following one, but it gives me error.
assert property (@(...
- 1,982
3
votes
1
answer
494
views
PSL assertion for variable delay pipeline
I am trying to write a PSL assertion that checks that the amount of assertions on the input match the amount of assertions on the output.
For example:
.
On the input anything can happen at any time ...
- 476
0
votes
1
answer
1k
views
usage of $past macro in system verilog for a signal to high
I am a starter in system verilog.
I want to check on a falling edge of the signal whether it is high for the past 'n' number of cycles. Usage of ##n cycles doesn't work for me.
logic x,y;
x & y ...
- 1
0
votes
2
answers
778
views
SystemVerilog Concurrent Assertion Sequence Dynamic Length
I have an array of length x. A signals output for a given testbench will be each value in the array in its respective order from 0:x-1.
In my problem in particular, the array is filter coefficients ...
- 1
1
vote
1
answer
977
views
illegal combination of always and assignment
I have planned to write verification for dual port ram with assertions but when I try to bind the property below. I have not used any rd pins or rst pins
I have take my dut from
https://www.intel....
- 85
0
votes
1
answer
341
views
How to prevent new threads of SVA
Lets assume, I have a button in my design. I want to increment counter between next two clock when button has been pressed three times and I want to check this behaviour with SVA.
I have wrote this ...
0
votes
2
answers
1k
views
Systemverilog assertion throughout syntax
I am trying to write an assertion, the spec goes like:
if a is high in any cycle, then for the next 3 cycles, c should be assert if b is not asserted.
If anytime b is asserted, c should be deasserted ...
