Um 90024

UM90024
4 kW analogue bridgeless totem-pole PFC evaluation board

Rev. 1.0 — 21 November 2023 user manual
Document information
Information Content
Keywords GaN FET, PFC, evaluation board, circuit design, PCB layout
Abstract The analogue totem-pole PFC evaluation board is a bridgeless totem-pole Power-factor-
Correction (PFC) circuit.
Nexperia UM90024
1. EVALUATION BOARD TERMS OF USE

The use of the Evaluation Board is subject to the Evaluation Board Terms of Use, which you can
find here. By using this Evaluation Board, you accept these terms.
2. High Voltage Safety Precautions

Read all safety precautions before use!
Please note that this document covers only the 4kW analogue bridgeless totem-pole PFC
evaluation board and its functions. For additional information, please refer to the Product
Specification
To ensure safe operation, please carefully read all precautions before handling the evaluation
board. Depending on the configuration of the board and voltages used, potentially lethal voltages
may be generated. Therefore, please make sure to read and observe all safety precautions
described below.
Before Use:
It is recommended that ALL operation and testing of the evaluation board is performed with the
board enclosed within a non-conductive enclosure that prevents the High Voltage supply to be
switched whilst open and accessible; see Fig. 1.
Fig. 1. Example of a safety enclosure in the Nexperia lab
UM90024 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2023. All rights reserved
user manual Rev. 1.0 — 21 November 2023 2 / 40

Nexperia UM90024
All probes should be position before turning on the High Voltage and should be held in place using
a suitable probe positioner e.g. PMK MSA100; see Fig. 2.
Fig. 2. Example of a probe positioner
Always use an oscilloscope with protective earth connected.

When probing High Voltage, ensure that the probes have the correct voltage rating / limit.
Ensure that all scope probes are compensated and de-skewed before use, refer to your
oscilloscope or probe manual for instructions on how to do this.
If possible, have a visual indicator of High Voltage located close to the evaluation board (LED bar
graph or voltmeter) To show when the Bus Voltage (Vbus) and Outputs are at dangerous levels.
Verify that none of the parts or components are damaged or missing.
Check that there are no conductive foreign objects on the board.
If any soldering or modifications are made or carried out, then please ensure that this is done
carefully so that solder splashes and debris are not created. Clean the board with Iso-propyl-
alcohol and allow it to dry.
Ensure that there is no condensation or moisture droplets on the circuit board, all testing should be
carried out within a dry environment without excessive humidity.
If used under conditions beyond the rated voltage and current specification, this may cause
defects, failure and or permanent damage.
NEVER handle the evaluation board during operation under ANY circumstances
After use the Nexperia Evaluation Board contains components which may store high voltage and
will take time to discharge. Carefully probe the evaluation board once the power has been removed
to check that all capacitors have been discharged. You must do this without touching the board
except for the multimeter probes that are being used to check.
This evaluation board is intended for use only in High Voltage Lab environments and should
be handled only by qualified personnel familiar with all safety and operating procedures. We
recommend carrying out operation and testing in a safe environment that includes restricted access
only to trained personnel, the use of High Voltage signage at all entrances, safety interlocks and
emergency stops and HV insulated flooring.
It should be noted that this evaluation board is intended to be used ONLY for evaluation purposes
and should not be used by consumers or designed into consumer equipment in its current form.

Nexperia UM90024
3. Introduction
The Nexperia Analogue Totem-Pole PFC evaluation board implements a bridgeless totem-pole
Power-Factor- Correction (PFC) circuit, using Nexperia power GaN FETs. By using a diode-free
power GaN FET bridge with low reverse-recovery charge, very-high-efficiency single-phase AC-DC
conversion is realized. In this circuit, the performance and efficiency improvement are achieved by
use of GaN FETs in both the fast-switching and slow-switching legs of the circuit. The evaluation
board is shown in Fig. 3 and Fig. 4.
Fig. 3. 4 kW analogue totem-pole PFC evaluation board; top view with control card and heatsink fitted
Fig. 4. 4 kW analogue totem-pole PFC evaluation board; top view of GaN FETs (heatsink removed)

Nexperia UM90024
3.1. Warnings
This demo board is intended to demonstrate GaN FET technology. While it provides the main
features of a totem-pole PFC, it is not intended to be a finished product and does not have all
the protection features found in commercial power supplies. Along with this explanation go a few
warnings which should be kept in mind:
1. An isolated AC source should be used for the input.
2. Use either a passive resistive load or an electronic load set to resistance mode: 360 W to 2000
W lowline, 360 W to 4000 W highline.
3. The demo board is not fully tested at large load steps. DO NOT apply a very large step in the
load (>1000 W) when it is running.
4. DO NOT manually probe the waveforms when the demo is running. Set up probing before
powering up the demo board.
5. DO NOT touch any part of the demo board when it is running.
6. When plugging the daughterboard into the sockets, make sure that the daughterboard is fully
pushed down.
7. It is not recommended to use a passive voltage probe for VDS and VGS measurements while
simultaneously using a differential voltage probe for Vin measurements unless the differential
probe has very good dv/dt immunity.
8. BE AWARE that DC negative and AC neutral are not the same node, and that unless proper
caution is taken with instrument grounding, a severe fault condition could be created.
3.2. Quick reference information

Table 1. 4 kW Analogue Totem-pole PFC evaluation board Input/Output specifications
Parameter Value
Input voltage 85 VAC to 265 VAC; 47 Hz to 63 Hz
Input current 18 A (RMS): (2000 W at 115 VAC; 4000 W at 230 VAC)
Ambient temperature <50 °C
Output voltage 385 VDC ±5 VDC
PWM frequency 65 kHz
Power dissipation in the GaN FET is limited by the maximum junction temperature. Refer to the
GAN039-650NTB data sheet.

Nexperia UM90024
4. Circuit description
The bridgeless totem-pole topology is shown in Fig. 5 below. As shown in Fig. 5 (a), two GaN FETs
Q1 and Q2 and two diodes D1 and D2 are used for the line rectification, while in Fig. 5 (b), the
circuit is modified, and the diodes are replaced by two further GaN FETs Q3 and Q4 to eliminate
diode forward voltage drops and improve efficiency.
aaa-037756
Q1 Q1 Q3
Vi D2 Vi
il il
VIN VIN
VD VD
D1
Q2 Q2 Q4
(a) Diode for line rectification (b) GaN FET for line rectification
Fig. 5. Totem-pole bridgeless PFC converter based on GaN FET
The large recovery charge (Qr) of existing silicon MOSFETs makes CCM operation of a silicon
totem-pole bridgeless PFC impractical and reduces the total efficiency. Table 2 below compares the
Nexperia GAN039-650NTB GaN FET to an equivalent CoolMOS MOSFET.
Table 2. GaN FET and equivalent CoolMOS MOSFET key parameter comparison
Parameter GAN039-650NTB IPW65R041CFD
RDSon (max) 39 mΩ 41 mΩ
ID 60 A 68.5 A
QG 26 nC 300 nC
Qr 187 nC 1.9 µC
A GaN FET totem-pole PFC in Continuous Conduction Mode (CCM) focusing on minimizing
conduction losses was designed. A simplified schematic is shown in Fig. 6 (a). It consists of a
pair of fast GaN FET switches (Q1 and Q2) operating at a high pulse width modulation (PWM)
frequency and another pair of GaN FET switches (Q3 and Q4) operating at a much lower line
frequency (50/60 Hz). The primary current path includes one fast switch and one slow switch only,
with no diode drop. The function of Q3 and Q4 is that of a synchronized rectifier as illustrated in
Fig. 6 (b) and Fig. 6 (c). During the positive AC cycle, Q4 is on and Q3 is off, forcing the AC neutral
line to be tied to the negative terminal of the DC output. The opposite applies for the negative
cycle.

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V O+ aaa-037757
Q1 Q3
LB
VS
VIN
Q2 Q4
V O-
(a) Simplified schematic
V O+ V O+
Q1 Q3 Q1 Q3
LB LB
VS VS
VIN VIN
N N
Q2 Q4 Q2 Q4
V O- V O-
(b) Positive AC half-cycle (c) Negative AC half-cycle
Fig. 6. GaN FET totem-pole bridgeless PFC converter
In either AC polarity, the two fast-switching GaN FETs (Q1 and Q2) form a synchronized boost
converter with one transistor acting as a master switch to allow energy intake by the boost inductor
(LB) and the other transistor as a slave switch to release energy to the DC output. The roles of
the two GaN FET devices interchange when the polarity of the AC input changes; therefore, each
transistor must be able to perform both master and slave functions. To avoid shoot through, a
dead time is built in between two switching events during which both transistors are momentarily
off. To allow CCM operation, the slave transistor must function as a flyback diode for the inductor
current to flow during the dead time. The diode current, however, must quickly reduce to zero
and transition to the reverse blocking state once the master switch turns on. This is the critical
process for a totem pole PFC which previously lead to abnormal spikes, instability and associated
high switching losses due to the high Qr of the body diode in modern high-voltage Si MOSFETs.
The low Qr of the GaN FET switches allows designers to overcome this barrier. As seen in Fig. 7,
inductive tests at 400 V bus using the high-side GaN FET as a master switch show healthy voltage
waveforms up to inductor current exceeding 35 A. Refer to Section 7 for more details.
With a design goal of 4.4 kW output power in CCM mode at 230 VAC input, the required inductor
current is 20 A. This test confirms a successful totem-pole power block with enough current
overhead.
One inherent issue in bridgeless totem-pole PFC is the operation mode transition at AC voltage
zero-crossing. For instance, when the circuit operation mode changes from positive half-cycle to
negative half-cycle at the zero-crossing, the duty ratio of switch Q2 changes abruptly from almost
100% to 0%, and the duty ratio of switch Q1 changes from 0% to 100%. Due to the slow reverse
recovery of diodes (or body diode of MOSFET), the voltage VS cannot jump from ground to VDC
instantly; a current spike will be induced. To avoid the problem, a soft-start sequence with a duty
ratio ramp is employed for a short period at each AC zero-crossing for better stability. Since the
Analogue totem-pole bridgeless PFC is designed to run in CCM, the larger inductance alleviates
the current spike issue at zero-crossing.

Nexperia UM90024
High-side as master
Fig. 7. Hard-switched waveform of a pair of GaN FET switches

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5. Design details
For this evaluation board, the PFC circuit has been implemented on a 4-layer PCB, with 2 oz
copper for the outer layers and 1.5 oz copper for the inner layers. GAN039-650NTB devices by
Nexperia are used for both the fast and slow switching legs. The inductor is made of a High Flux
core with the inductance of 480 μH and a DC resistance of 0.025 Ω, designed to operate at 65 kHz.
A simple 4 A rated high/low side driver IC (Si8273) with 0 V and 12 V as the on/off voltage levels
directly drives each GaN FET. A TI UCC28180DR controller IC handles the control algorithm.
The voltage and current loop controls are those of a conventional boost PFC converter. The
feedback signals are DC output voltage (VDC_OUT), AC input potential (LIVE_IN/POWER_IN)
and inductor current (I_SENSE). The input voltage polarity and RMS value are determined from
LIVE_IN/POWER_IN. The outer voltage loop output multiplied by |VAC| gives a sinusoidal current
reference. The current loop gives the proper duty ratio for the boost circuit. The polarity determines
how the PWM signal is distributed to drive Q1 and Q2. A soft-start sequence with a duty ratio ramp
is employed for a short period at each AC zero-crossing for better stability.
The circuit schematic, PCB layout and bill of materials for the Analogue bridgeless totem-pole PFC
evaluation boards are shown in the next sections.

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5.1. Mainboard schematics

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5.2. Mainboard PCB layout
Fig. 8. Mainboard PCB top layer


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Fig. 9. Mainboard PCB bottom layer

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Fig. 10. Mainboard PCB inner layers 2 (ground place) and 3 (power and ground planes)

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5.3. Daughterboard schematics

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5.4. Daughterboard PCB Layout
Fig. 11. Daughterboard PCB top layer

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Fig. 12. Daughterboard PCB bottom layer

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Fig. 13. Daughterboard PCB inner layers 2 (ground place) and 3 (power and ground planes)

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5.5. Mainboard Bill of Materials

Table 3. Mainboard Bill of Material
Part Value Voltage Package Description Supplier Supplier P/N
C1 100n 50V C0603 Capacitor, Ceramic RS 114-0367
C4 22u 25V C0805 Capacitor, Ceramic Farnell 1907510
C7 100p 100V C0603 Capacitor, Ceramic, Farnell 1740605
C0G
C0G
C9 - - C0805 Capacitor, Ceramic - -
C0G
C0G
C34 680n 450V C2220 Capacitor, Ceramic Mouser 810-
CGA9M4X7T2W864MA
C35 10n 1kV C1206 Capacitor, Ceramic Mouser 581-1206AC103KAT2A
C37 470u 450V Radial Capacitor, Electrolytic Mouser 80-ALC10A471DF450

Nexperia UM90024

CMC1 CMC 3.9mH 25A 2LN DigiKey 2258-T60405R6128X225-
TH ND
CMC2 CMC 3.9mH 25A 2LN DigiKey 2258-T60405R6128X225-
TH ND
CX1 1.5u 310V Radial Capacitor, PP Film Mouser 710-890334026030CS
CY1 4.7n 630V Radial Capacitor, PP Film DigiKey BC1615-ND
CY2 4.7n 630V Radial Capacitor, PP Film DigiKey BC1615-ND
D1 PMEG 2020EJ 20V SOD-323 Diode, Schottky Nexperia PMEG2020EJ
D2 ES1J 600V DO-214AC Diode Farnell 3519291
D3 PMEG 6002EB 60V SOD-523 Diode, Schottky Nexperia PMEG6002EB
D4 ES1J 600V DO-214AC Diode Farnell 3519291
D5 - - DO-214AC Diode - -
D6 - - DO-214AC Diode - -
D11 GBJ2506-F 600V Bridge Rectifier Farnell 3127402
F1 Fuse Clip TH Farnell 2762088
F1 Fuse Farnell 1150557
FB11 30R FB0603 Ferrite Farnell 1515741
J1 4-Pin Header TH RS 144-8185
JP1 Jumper Link SMD Farnell 2751488
JP2 Jumper Link SMD Farnell 2751488
K1 Relay SPST-NO 30A Farnell 2395974
L1 480uH AGW
L2 46.65uH AGW
LED1 LED D0603 LED, Green Farnell 8529833
LED8 LED D0603 LED, Red Farnell 2099224
Q1 GAN039 -650NTB 650V CCPAK GaN FET Nexperia GAN039-650NTB
Q5 - - TO-247 MOSFET - -

Nexperia UM90024

Q6 - - TO-247 MOSFET - -
R1 10R R1206 Resistor Farnell 1738986
R11 37.4k R1206 Resistor Farnell 2307665
R17 47R Inrush current limiter DigiKey 317-1220-ND
R18 47R Inrush current limiter DigiKey 317-1220-ND
R22 10k R0603 Resistor RS 566-890
R23 10k R0603 Resistor RS 566-890
R24 10k R0603 Resistor RS 566-890
R25 10k R0603 Resistor RS 566-890
R27 10k R0603 Resistor RS 566-890
R28 10k R0603 Resistor RS 566-890
R30 51k R0603 Resistor Farnell 2059471
R32 10k R0603 Resistor RS 566-890
R33 10k R0603 Resistor RS 566-890
R43 - R0805 Resistor - -

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R50 4m R2512 Resistor DigiKey YAG6087CT-ND
R51 4m R2512 Resistor DigiKey YAG6087CT-ND
U1 Si8273BBD -ISR1 2.5kV SOIC16 ISO Hi/Lo gate driver Mouser 634-SI8273BB-IS1R
U2 CAP-019 SOIC8 Cap discharge DigiKey 596-1684-1-ND
U3 Si8273BBD -ISR1 2.5kV SOIC16 ISO Hi/Lo gate driver Mouser 634-SI8273BB-IS1R
X1 690V 3-pos terminal block Farnell 3704713
X2 5 x MMS-105-01-L-SV RS 180-4953
X3 - - - -
X4 - - - -
X5 - - - -
X6 - - - -
X7 - - - -
X8 - - - -
X10 690V 2-pos terminal block Farnell 3704701
HS1 Heatsink/Fan assy Fischer LAM5 50 12
HS1 Housing – Fan assy Farnell 2751642
HS1 Crimp – Fan assy Farnell 2063734
HS1 Insulator 50mm sq DigiKey 345-1548-ND
HS1 M3 x 2.5mm custom
spacer
spacer
spacer
spacer
HS1 M3 x 5mm Square nut RS 837-262
HS1 Custom holder
Square nut
HS1 Custom holder
Square nut
HS1 Custom holder
Square nut

Nexperia UM90024

HS1 Custom holder
Square nut
HS1 M3 x 12mm Pozi Farnell 1420391
screw
screw
screw
screw
ST1 M3 x 15mm Standoff Farnell 1336157
ST1 M3 x 6mm Pozi screw Farnell 1419986
PCB PCBWay

Nexperia UM90024
5.6. Daughterboard Bill of Materials

Table 4. Daughterboard Bill of Material
C1 1.5n 50V C0603 Capacitor, Ceramic Mouser 81-GRM1885C1H152JA01
C2 100p 100V C0603 Capacitor, Ceramic, Mouser 581-06031C101K
C0G
C3 560n 10V C0603 Capacitor, Ceramic DigiKey 399-
C0603C564K8PAC7867CT-
ND
C4 4.7u 35V C0603 Capacitor, Ceramic Mouser 81-
GRM188R6YA475KE5D
C0G
C0G
C7 22p 100V C0603 Capacitor, Ceramic, Mouser 80-C0603C220J1G
C0G
C8 1n 50V C0603 Capacitor, Ceramic Mouser 603-CC603MRX7R9BB102
C0G
C10 22p 100V C0603 Capacitor, Ceramic, Mouser 80-C0603C220J1G
C0G
C0G
C0G
C15 10u 25V C0805 Capacitor, Ceramic Mouser 81-GRM21BC71E106KE1L
C21 1u 25V C0603 Capacitor, Ceramic Mouser 187-CL10B105KA8NNNC
C25 220u 16V SMD Capacitor, Polymer Mouser P124158CT-ND
C26 22u 25V C1206 Capacitor, Ceramic Mouser 810-C3216X5R1E226M
C27 22u 25V C1206 Capacitor, Ceramic Mouser 810-C3216X5R1E226M
C28 10n 25V C0603 Capacitor, Ceramic Mouser 603-CC603KRX7R8BB103

Nexperia UM90024

CMC1 CMC 100uH, 200mA, Mouser 810-ACT45R1012PTL001
SMD
CMC2 CMC 100uH, 200mA, Mouser 810-ACT45R1012PTL001
SMD
D1 PMEG3010EB 30V SOD-523 Diode, Schottky Nexperia PMEG3010EB
D2 BAT54C 30V SOT-23 Dual diode, Schottky Nexperia BAT54C, 215
D3 ES1J 600V DO-214AC Diode Mouser 833-ES1J-LTP
FB1 600R FB0603 Ferrite Mouser 810-MMZ1608B601CTAH0
L1 4.7uH Inductor Mouser 710-74438323047
Q1 BSH103BKR 30V SOT-23 MOSFET n-chan Nexperia BSH103BKR
Q2 SSM3J334R 30V SOT-23 MOSFET p-chan Mouser 757-SSM3J334RLF
Q3 SSM3J334R 30V SOT-23 MOSFET p-chan Mouser 757-SSM3J334RLF
R1 330R R0603 Resistor Mouser 603-AC0603FR-07330RL
R2 33k R0603 Resistor Mouser 603-AC0603FR-0733KL
R3 2.61k R0603 Resistor Mouser 660-RK73H1JTTD2611F
R4 16k R0603 Resistor Mouser 660-RK73H1JTTD1602F
R7 1M R0603 Resistor Mouser 603-RC0603FR-131ML
R8 5.1k R0603 Resistor Mouser 603-AC0603FR-075K1L
R9 470k R1206 Resistor Mouser 660-RK73H2BTTD4703F

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R15 1.8k R0603 Resistor Mouser 279-CRGCQ0603F1K8
R21 1k R0603 Resistor DigiKey RMCF0603FT1K00CT-ND
R23 5.1k R0603 Resistor Mouser 603-AC0603FR-075K1L
R36 49.9R R0603 Resistor Mouser 660-RK73H1JTTD49R9F
R40 49.9R R0603 Resistor Mouser 660-RK73H1JTTD49R9F
R43 470R R0603 Resistor Mouser 652-CR0603FX-4700ELF
R49 0R R0603 Resistor Mouser 603-RC0603FR-070RL

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T1 Flyback Transformer, Wurth 750314352
TH
U1 SOIC8 Power Factor Mouser 595-UCC28180DR
Controller
U2 SOIC8 Comparator Mouser 511-TS393IDT
U3 SOIC8 Op-amp Mouser 511-TSX712IDT
U4 SOT-23-6 Comparator with Mouser 926-LMV761MF
shutdown
U5 74LV32APW TSSOP-14 Quad 2-input OR gate Nexperia 74LV32APW
U6 74LV04PW TSSOP-14 Hex NOT gate Nexperia 74LV04PW
U7 74LV08PW TSSOP-14 Quad 2-input AND Nexperia 74LV08PW
gate
U8 74LV08PW TSSOP-14 Quad 2-input AND Nexperia 74LV08PW
gate
U9 Mini-flat Opto-coupler Mouser 512-FODM8801A
U10 SOT-23 Vref adjustable Mouser NCP432BISNT1G0SCT-
ND
U11 SOIC16 Offline switcher Mouser 863-NCP1063AD060R2G
U12 SOIC8 Comparator Mouser 511-TS393IDT
U13 SOT-23-5 Regulator LDO Mouser 497-16672-1-ND
adjustable
U14 SOT-23-5 Regulator LDO Mouser 497-16672-1-ND
adjustable
X1 TMM-105-01-L-S-RA Mouser 200-TMM10501LSRA
Z1 BZX585-B4V7 4.7V SOD-523 Diode, Zener Nexperia BZX585-B4V7
Z2 170V DO-214AC Diode, TVS Mouser 625-SMAJ170A-E3
unidirectional
Z3 16V DO-214AC Diode, Zener Mouser 621-SMAZ16-13-F
PCB PCBWay

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6. Using the board

The board can be used for evaluation of Nexperia GAN039-650NTB GaN FETs in a bridgeless
totem-pole PFC circuit. It is not a complete circuit, but rather a building block.
6.1. Turn on sequence

1. Insert the daughterboard into the corresponding connectors on the mainboard marked X2 on
the PCB, making sure that all pins are aligned correctly and inserted fully.
2. Connect an electronic/resistive load to the output terminal block marked X10 on the PCB,
making sure that the correct polarity is observed (if applicable).
The requirements for the resistive load are:
• at 115 VAC input: between 0 W and ≤2000 W
• at 230 VAC input: between 0 W and ≤4000 W
3. With the high voltage power OFF, connect the high-voltage AC power input to the input terminal
block marked X1 on the PCB; L and N (PE: Protective Earth).
4. Turn ON the AC power input (85 VAC to 265 VAC, 50 Hz to 60 Hz):
• minimum load power for turn-on sequence is 360 W
• monitor X10 output voltage with a VDC meter and verify 385 V ±5 V is generated
• load can be increased/decreased when AC supply is ON and board is functional
6.2. Turn off sequence

1. Turn OFF the high-voltage AC power input.
2. Verify input and output voltages are at 0 V.
7. Operational waveforms
Fig. 14 shows the converter start-up procedure with an AC input voltage of 230V and an output
load of 360W: CH1 shows the PWM applied to the gate of low-side GaN FET Q2, CH2 is the DC
bus voltage waveform, CH3 is the voltage waveform of fast leg switching node (SW_NODE) and
CH4 is the AC input current.
For the start-up, there are three phases to charge the DC bus to a reference voltage. Initially, the
relay K1 contacts are open and the DC bus capacitors are charged by the input voltage through the
inrush current limiters R17/R18 and the diode bridge D11. The inrush current limiters R17/R18 and
diode bridge are applied in this circuit to avoid high inrush current flow through the GaN FETs.
When the voltage on VDC_OUT is over 100 V, the relay K1 contacts are closed to bypass the
inrush current limiters, and the voltage on VDC_OUT increases to the peak of the input voltage.
After approximately 100 ms following application of the AC input, the GaN FETs are engaged
in closed-loop voltage control, in which the voltage on VDC_OUT slowly increases to the rated
voltage of 385 V.
Fig. 15 below shows the VDS of Q2 during one turn-on event of a five pulse, single-shot staircase
test at 50 kHz. The inductor is connected to the BUS voltage set at 400 V and the current flows
through the low-side GaN FET and recirculates through the high-side GaN FET. Each pulse has a
width of 3.8 μs, leading to a peak inductor current of 36 A. It can be seen that the voltage spike is
19 V at IL = 22 A.
The transient signal seen on VGS when VDS makes it's low-to-high transition may appear to be
an example of Miller feedback. Because of the extremely low Miller capacitance of the casacode
switch, this is not actually the case. The voltage transient is due to di/dt in the small, but non-zero,
source inductance. The internal VGS actually changes very little during the transient, and there is
therefore no concern for false turn-on.

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CH1: Q2 PWM; CH2 VO; CH3 SW_NODE; CH4 Iin)

Fig. 14. Start-up of the bridgeless totem-pole PFC with 360 W load

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Fig. 15. Waveforms of VGS and VDS of Q2 at IL = 22 A

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8. Dead-time control
The required form of the gate-drive signals is shown in Fig. 16. The times marked A are the dead-
times when neither GaN FET is driven on. The dead-time must be greater than zero to avoid shoot-
through currents. The dead-times are set by resistors R3 and R5 on the daughterboard – the
values specified in the Bill of Materials correspond to approximately 200 ns.
VGS 1
VGS 2
A B A
Fig. 16. Non-overlapping gate pulses
Nexperia GaN FETs can switch at dV/dt of 50 V/ns or higher to enable the lowest possible
switching loss. At this level of operation, even the layout becomes a significant contributor to
performance. As shown in Fig. 8, the recommended PCB layout keeps a minimum gate drive loop;
it also keeps the traces between the switching nodes very short, with the shortest practical return
trace to the power bus and ground. The power ground plane provides a large cross-sectional area
to achieve an even ground potential throughout the circuit.
For further information, the different layers of the Nexperia Analogue Totem-Pole PFC evaluation
board design are shown in Section 5.2.

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9. Probing
As shown in Fig. 17 below, there are probing positions to allow measurement of VGS Fig. 17 (a) and
VDS Fig. 17 (b) of the low-side fast switching GaN FET.
(a) (b)
Fig. 17. VGS and VDS probing positions of low-side fast switching GaN FET
As shown in Fig. 18 below, there is also a probing position to allow measurement of VGS of the low-
side slow switching GaN FET.
Fig. 18. VGS probing positions of low-side slow switching GaN FET

Nexperia UM90024
As shown in Fig. 19 below, there are also probing positions to allow measurement of high-side VGS
of both the fast switching and slow switching GaN FETs. For these signals to be measured during
operation, it is recommended that optical probes, such as Tektronix IsoVu, are utilised.
Fig. 19. VGS probing positions of high-side fast and slow switching GaN FET
By removing the jumpers shown in Fig. 20 below and using a short loop of thick gauge wire for the
current probe to be clamped around, the PFC inductor current can also be measured.
Fig. 20. Jumpers to be removed when measuring the inductor current

Nexperia UM90024
10. Efficiency sweeps

For the efficiency calculations, the input/output voltages and currents are measured using a power
analyzer to obtain the input/output power values. Efficiency has been measured with either 115
VAC or 230 VAC input and 385 VDC output using a calibrated PPA5530 precision power analyzer
from Newtons 4th. The efficiency results for the totem-Pole PFC board are shown in Fig. 21.
The extremely high efficiency of > 98.8% at 230 VAC input and > 97.6% at 115 VAC input will
enable customers to reach peak system efficiency to meet and exceed Titanium standards.
aaa-037731
99.5
Efficiency
(%)
98.5
97.5
96.5
0 1000 2000 3000 4000 5000
Output power (W)
Highline (230 VAC input)
Lowline (115 VAC input)
Fig. 21. Efficiency as a function of output power for bridgeless totem-pole PFC evaluation board
11. Revision history

Table 5. Revision history
Revision Date Description
number
1.0 2023-11-21 Initial version.

Nexperia UM90024
12. Legal information
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.

Nexperia UM90024
List of Tables
Table 1. 4 kW Analogue Totem-pole PFC evaluation
board Input/Output specifications.........................................5
Table 2. GaN FET and equivalent CoolMOS MOSFET
key parameter comparison.................................................. 6
Table 3. Mainboard Bill of Material.................................... 21
Table 4. Daughterboard Bill of Material..............................26
Table 5. Revision history....................................................36

Nexperia UM90024
List of Figures
Fig. 1. Example of a safety enclosure in the Nexperia lab... 2
Fig. 2. Example of a probe positioner..................................3
Fig. 3. 4 kW analogue totem-pole PFC evaluation
board; top view with control card and heatsink fitted........... 4
Fig. 4. 4 kW analogue totem-pole PFC evaluation
board; top view of GaN FETs (heatsink removed)............... 4
Fig. 5. Totem-pole bridgeless PFC converter based on
GaN FET.............................................................................. 6
Fig. 6. GaN FET totem-pole bridgeless PFC converter........7
Fig. 7. Hard-switched waveform of a pair of GaN FET
switches................................................................................8
Fig. 8. Mainboard PCB top layer........................................12
Fig. 9. Mainboard PCB bottom layer..................................13
Fig. 10. Mainboard PCB inner layers 2 (ground place)
and 3 (power and ground planes)......................................14
Fig. 11. Daughterboard PCB top layer............................... 18
Fig. 12. Daughterboard PCB bottom layer.........................19
Fig. 13. Daughterboard PCB inner layers 2 (ground
place) and 3 (power and ground planes)........................... 20
Fig. 14. Start-up of the bridgeless totem-pole PFC with
360 W load.........................................................................31
Fig. 15. Waveforms of VGS and VDS of Q2 at IL = 22 A... 32
Fig. 16. Non-overlapping gate pulses................................ 33
Fig. 17. VGS and VDS probing positions of low-side
fast switching GaN FET..................................................... 34
Fig. 18. VGS probing positions of low-side slow
switching GaN FET............................................................ 34
Fig. 19. VGS probing positions of high-side fast and
slow switching GaN FET....................................................35
Fig. 20. Jumpers to be removed when measuring the
inductor current.................................................................. 35
Fig. 21. Efficiency as a function of output power for
bridgeless totem-pole PFC evaluation board..................... 36

Nexperia UM90024
Contents
1. EVALUATION BOARD TERMS OF USE.......................2
2. High Voltage Safety Precautions.................................2
3. Introduction................................................................... 4
3.1. Warnings......................................................................5
3.2. Quick reference information........................................ 5
4. Circuit description........................................................ 6
5. Design details............................................................... 9
5.1. Mainboard schematics...............................................10
5.2. Mainboard PCB layout...............................................12
5.3. Daughterboard schematics........................................ 15
5.4. Daughterboard PCB Layout.......................................18
5.5. Mainboard Bill of Materials........................................ 21
5.6. Daughterboard Bill of Materials................................. 26
6. Using the board.......................................................... 30
6.1. Turn on sequence......................................................30
6.2. Turn off sequence......................................................30
7. Operational waveforms.............................................. 30
8. Dead-time control....................................................... 33
9. Probing........................................................................ 34
10. Efficiency sweeps.....................................................36
11. Revision history........................................................ 36
12. Legal information......................................................37
© Nexperia B.V. 2023. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: [email protected]
Date of release: 21 November 2023

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UM90024

4 kW analogue bridgeless totem-pole PFC evaluation board

1. EVALUATION BOARD TERMS OF USE

2. High Voltage Safety Precautions

Fig. 1. Example of a safety enclosure in the Nexperia lab

user manual Rev. 1.0 — 21 November 2023 2 / 40

Fig. 2. Example of a probe positioner

Always use an oscilloscope with protective earth connected.

user manual Rev. 1.0 — 21 November 2023 3 / 40

user manual Rev. 1.0 — 21 November 2023 4 / 40

3.2. Quick reference information

user manual Rev. 1.0 — 21 November 2023 5 / 40

Fig. 5. Totem-pole bridgeless PFC converter based on GaN FET

user manual Rev. 1.0 — 21 November 2023 6 / 40

(b) Positive AC half-cycle (c) Negative AC half-cycle

Fig. 6. GaN FET totem-pole bridgeless PFC converter

user manual Rev. 1.0 — 21 November 2023 7 / 40

user manual Rev. 1.0 — 21 November 2023 8 / 40

user manual Rev. 1.0 — 21 November 2023 9 / 40

5.1. Mainboard schematics

user manual Rev. 1.0 — 21 November 2023 10 / 40

user manual Rev. 1.0 — 21 November 2023 11 / 40

5.2. Mainboard PCB layout

Fig. 8. Mainboard PCB top layer

user manual Rev. 1.0 — 21 November 2023 12 / 40

Fig. 9. Mainboard PCB bottom layer

user manual Rev. 1.0 — 21 November 2023 13 / 40

user manual Rev. 1.0 — 21 November 2023 14 / 40

5.3. Daughterboard schematics

user manual Rev. 1.0 — 21 November 2023 15 / 40

user manual Rev. 1.0 — 21 November 2023 16 / 40

user manual Rev. 1.0 — 21 November 2023 17 / 40

5.4. Daughterboard PCB Layout

Fig. 11. Daughterboard PCB top layer

user manual Rev. 1.0 — 21 November 2023 18 / 40

Fig. 12. Daughterboard PCB bottom layer

user manual Rev. 1.0 — 21 November 2023 19 / 40

user manual Rev. 1.0 — 21 November 2023 20 / 40

5.5. Mainboard Bill of Materials

user manual Rev. 1.0 — 21 November 2023 21 / 40

Part Value Voltage Package Description Supplier Supplier P/N

user manual Rev. 1.0 — 21 November 2023 22 / 40

Part Value Voltage Package Description Supplier Supplier P/N

user manual Rev. 1.0 — 21 November 2023 23 / 40

Part Value Voltage Package Description Supplier Supplier P/N

user manual Rev. 1.0 — 21 November 2023 24 / 40

Part Value Voltage Package Description Supplier Supplier P/N

user manual Rev. 1.0 — 21 November 2023 25 / 40

5.6. Daughterboard Bill of Materials

user manual Rev. 1.0 — 21 November 2023 26 / 40

Part Value Voltage Package Description Supplier Supplier P/N

user manual Rev. 1.0 — 21 November 2023 27 / 40

Part Value Voltage Package Description Supplier Supplier P/N

user manual Rev. 1.0 — 21 November 2023 28 / 40

Part Value Voltage Package Description Supplier Supplier P/N

user manual Rev. 1.0 — 21 November 2023 29 / 40

6. Using the board

6.1. Turn on sequence

6.2. Turn off sequence

user manual Rev. 1.0 — 21 November 2023 30 / 40