Proceedings of Technical Program of 2012 VLSI Technology, System and Application, 2012
As CMOS technology continues scaling down, especially to the nano-device regime, different stress... more As CMOS technology continues scaling down, especially to the nano-device regime, different stress elements, such as dual stress liner (DSL) and eSiGe, have been introduced to the standard process flow as the must-have performance boosters [1][2]. Recently, distinct layout effects have been reported for eSiGe technology, such as gatepitch, STI interaction and Source/Drain (S/D) length effects [3][4][5]. The layout effects could be dramatically degraded when aggressive pitch scaling happens. For example, as shown in , the drive current loss due to PFET active area scaling in 45/65nm node is less than 5%. However, this number could easily exceed 15% in 32/28nm as technology scales. In the following discussions, we will present the device impacts from eSiGe layout with PC-bounded and STIbounded eSiGe growth for both Box-profile and Sigma-profile in 32/28nm technology node.
Technical Digest - International Electron Devices Meeting, IEDM, 2011
Abstract Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH) in p-cha... more Abstract Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for ...
Proceedings of Technical Program of 2012 VLSI Technology, System and Application, 2012
As CMOS technology continues scaling down, especially to the nano-device regime, different stress... more As CMOS technology continues scaling down, especially to the nano-device regime, different stress elements, such as dual stress liner (DSL) and eSiGe, have been introduced to the standard process flow as the must-have performance boosters [1][2]. Recently, distinct layout effects have been reported for eSiGe technology, such as gatepitch, STI interaction and Source/Drain (S/D) length effects [3][4][5]. The layout effects could be dramatically degraded when aggressive pitch scaling happens. For example, as shown in , the drive current loss due to PFET active area scaling in 45/65nm node is less than 5%. However, this number could easily exceed 15% in 32/28nm as technology scales. In the following discussions, we will present the device impacts from eSiGe layout with PC-bounded and STIbounded eSiGe growth for both Box-profile and Sigma-profile in 32/28nm technology node.
Technical Digest - International Electron Devices Meeting, IEDM, 2011
Abstract Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH) in p-cha... more Abstract Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for ...
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Papers by T. Wallner