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Momme Allalen

Leibniz Supercomputing Centre, User & HPC Application Support, Faculty Member

Universität Osnabrück, Theoretical physics, Graduate Student

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Momme Allalen received his Ph.D in theoretical Physics from the University of Osnabrück in 2006. He worked in the field of molecular magnetics through modelling techniques such as the exact numerical diagonalisation of the Heisenberg model. He joined the Leibniz Computing Centre (LRZ) in 2007 working in the High Performance Computing group. His tasks include user support, optimisation and parallelisation of scientific application codes, and benchmarking for characterising and evaluating the performance of high-end supercomputers. His research interests are various aspects of parallel computing and new programming languages and paradigms.

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Papers by Momme Allalen

Best Practice Guide - GPGPU

Graphics Processing Units (GPUs) were originally developed for computer gaming and other graphica... more Graphics Processing Units (GPUs) were originally developed for computer gaming and other graphical tasks,<br> but for many years have been exploited for general purpose computing across a number of areas. They offer<br> advantages over traditional CPUs because they have greater computational capability, and use high-bandwidth<br> memory systems (where memory bandwidth is the main bottleneck for many scientific applications).<br> This Best Practice Guide describes GPUs: it includes information on how to get started with programming GPUs,<br> which cannot be used in isolation but as "accelerators" in conjunction with CPUs, and how to get good performance.<br> Focus is given to NVIDIA GPUs, which are most widespread today.<br> In Section 2, "The GPU Architecture", the GPU architecture is described, with a focus on the latest "Pascal"<br> generation of NVIDIA GPUs, and attention is given to the architectural r...

Deploying Containerized QuanEX Quantum Simulation Software on HPC Systems

2021 3rd International Workshop on Containers and New Orchestration Paradigms for Isolated Environments in HPC (CANOPIE-HPC), 2021

The simulation of quantum circuits using the tensor network method is very computationally demand... more The simulation of quantum circuits using the tensor network method is very computationally demanding and requires significant High Performance Computing (HPC) resources to find an efficient contraction order and to perform the contraction of the large tensor networks. In addition, the researchers want a workflow that is easy to customize, reproduce and migrate to different HPC systems. In this paper, we discuss the issues associated with the deployment of the QuantEX quantum computing simulation software within containers on different HPC systems. Also, we compare the performance of the containerized software with the software running on "bare metal".

Deploying Containerized QuanEX Quantum Simulation Software on HPC Systems

2021 3rd International Workshop on Containers and New Orchestration Paradigms for Isolated Environments in HPC (CANOPIE-HPC), 2021

The simulation of quantum circuits using the tensor network method is very computationally demand... more The simulation of quantum circuits using the tensor network method is very computationally demanding and requires significant High Performance Computing (HPC) resources to find an efficient contraction order and to perform the contraction of the large tensor networks. In addition, the researchers want a workflow that is easy to customize, reproduce and migrate to different HPC systems. In this paper, we discuss the issues associated with the deployment of the QuantEX quantum computing simulation software within containers on different HPC systems. Also, we compare the performance of the containerized software with the software running on “bare metal”.

QXTools: A Julia framework for distributed quantum circuit simulation

Journal of Open Source Software, 2022

QXTools is a framework for simulating quantum circuits using tensor network methods. Weak simulat... more QXTools is a framework for simulating quantum circuits using tensor network methods. Weak simulation is the primary use case where given a quantum circuit and input state QXTools will efficiently calculate the probability amplitude of a given output configuration or set of configurations. Given this ability one can sample from the output distribution using random sampling approaches. QXTools is intended to be used by researchers interested in simulating circuits larger than those possible with full wave-function simulators or those interested in research and development of tensor network circuit simulation methods. See Brennan et al. (2021) for more complete background and scaling results and Brayford et al. (2021) for details about deploying in containerised environments.

SuperMUC Phase 2: Challenges of Peta-scale applications

First experiences with the Intel MIC architecture at LRZ

ArXiv, 2013

With the rapidly growing demand for computing power new accelerator based architectures have ente... more With the rapidly growing demand for computing power new accelerator based architectures have entered the world of high performance computing since around 5 years. In particular GPGPUs have recently become very popular, however programming GPGPUs using programming languages like CUDA or OpenCL is cumbersome and error-prone. Trying to overcome these difficulties, Intel developed their own Many Integrated Core (MIC) architecture which can be programmed using standard parallel programming techniques like OpenMP and MPI. In the beginning of 2013, the first production-level cards named Intel Xeon Phi came on the market. LRZ has been considered by Intel as a leading research centre for evaluating coprocessors based on the MIC architecture since 2010 under strict NDA. Since the Intel Xeon Phi is now generally available, we can share our experience on programming Intel's new MIC architecture.

Node-Level optimization of a 3D Block-Based Multiresolution Compressible Flow Solver with Emphasis on Performance Portability

2019 International Conference on High Performance Computing & Simulation (HPCS), 2019

Despite the enormous increase in computational power in the last decades, the numerical study of ... more Despite the enormous increase in computational power in the last decades, the numerical study of complex flows remains challenging. State-of-the-art techniques to simulate hyperbolic flows with discontinuities rely on computationally demanding nonlinear schemes, such as Riemann solvers with weighted essentially non-oscillatory (WENO) stencils and characteristic decompositioning. To handle this complexity the numerical load can be reduced via a multiresolution (MR) algorithm with local time stepping (LTS) running on modern high-performance computing (HPC) systems. Eventually, the main challenge lies in an efficitent utilization of the available HPC hardware. In this work, we evaluate the performance improvement for a Message Passing Interface (MPI)-parallelized MR solver using single instruction multiple data (SIMD) optimizations. We present straight-forward code modifications that allow for auto-vectorization by the compiler, while maintaining the modularity of the code at comparabl...

Improving scalability for the CFD software package MGLET

Fast Matrix-Free Discontinuous Galerkin Kernels on Modern Computer Architectures

Lecture Notes in Computer Science

This study compares the performance of high-order discontinuous Galerkin finite elements on moder... more This study compares the performance of high-order discontinuous Galerkin finite elements on modern hardware. The main computational kernel is the matrix-free evaluation of differential operators by sum factorization, exemplified on the symmetric interior penalty discretization of the Laplacian as a metric for a complex application code in fluid dynamics. State-of-the-art implementations of these kernels stress both arithmetics and memory transfer. The implementations of SIMD vectorization and shared-memory parallelization are detailed. Computational results are presented for dual-socket Intel Haswell CPUs at 28 cores, a 64-core Intel Knights Landing, and a 16-core IBM Power8 processor. Up to polynomial degree six, Knights Landing is approximately twice as fast as Haswell. Power8 performs similarly to Haswell, trading a higher frequency for narrower SIMD units. The performance comparison shows that simple ways to express parallelism through for loops perform better on medium and high core counts than a more elaborate task-based parallelization with dynamic scheduling according to dependency graphs, despite less memory transfer in the latter algorithm.

Accurate and efficient QM / MM molecular dynamics on 86 , 016 cores of SuperMUC Phase 2

Ferdinand Jamitzky Leibniz Supercomputing Centre (LRZ) Boltzmannstrasse 1 85748 Garching, Germany... more Ferdinand Jamitzky Leibniz Supercomputing Centre (LRZ) Boltzmannstrasse 1 85748 Garching, Germany [email protected] Helmut Satzger Leibniz Supercomputing Centre (LRZ) Boltzmannstrasse 1 85748 Garching, Germany [email protected] Gerald Mathias Ludwig-MaximiliansUniversität München, Lehrstuhl für BioMolekulare Optik Oettingenstrasse 67 80538 München, Germany [email protected]

Extreme Scale-out SuperMUC Phase 2 - lessons learned

In spring 2015, the Leibniz Supercomputing Centre (Leibniz-Rechenzentrum, LRZ), installed their n... more In spring 2015, the Leibniz Supercomputing Centre (Leibniz-Rechenzentrum, LRZ), installed their new Peta-Scale System SuperMUC Phase2. Selected users were invited for a 28 day extreme scale-out block operation during which they were allowed to use the full system for their applications. The following projects participated in the extreme scale-out workshop: BQCD (Quantum Physics), SeisSol (Geophysics, Seismics), GPI-2/GASPI (Toolkit for HPC), Seven-League Hydro (Astrophysics), ILBDC (Lattice Boltzmann CFD), Iphigenie (Molecular Dynamic), FLASH (Astrophysics), GADGET (Cosmological Dynamics), PSC (Plasma Physics), waLBerla (Lattice Boltzmann CFD), Musubi (Lattice Boltzmann CFD), Vertex3D (Stellar Astrophysics), CIAO (Combustion CFD), and LS1-Mardyn (Material Science). The projects were allowed to use the machine exclusively during the 28 day period, which corresponds to a total of 63.4 million core-hours, of which 43.8 million core-hours were used by the applications, resulting in a ut...

The Mont-Blanc Project: First Phase Successfully Finished

ArXiv, 2015

Running from October 2011 to June 2015, the aim of the European project Mont-Blanc has been to de... more Running from October 2011 to June 2015, the aim of the European project Mont-Blanc has been to develop an approach to Exascale computing based on embedded power-efficient technology. The main goals of the project were to i) build an HPC prototype using currently available energy-efficient embedded technology, ii) design a Next Generation system to overcome the limitations of the built prototype and iii) port a set of representative Exascale applications to the system. This article summarises the contributions from the Leibniz Supercomputing Centre (LRZ) and the Juelich Supercomputing Centre (JSC), Germany, to the Mont-Blanc project.

Efficient High-Order Discontinuous Galerkin Finite Elements with Matrix-Free Implementations

This work presents high-order discontinuous Galerkin finite element kernels optimized for node-le... more This work presents high-order discontinuous Galerkin finite element kernels optimized for node-level performance on a series of Intel architectures ranging from Sandy Bridge to Skylake. The kernels implement matrix-free evaluation of integrals with sum factorization techniques. In order to increase performance and thus to help to achieve higher energy efficiency, this work proposes an element-based shared-memory parallelization option and compares it to a well-established shared-memory parallelization with global face data. The new algorithm is supported by the relevant metrics in terms of arithmetics and memory transfer. On a single node with \(2\times 24\) cores of Intel Skylake Scalable, we report more than 1,200 GFLOPs/s in double precision for the full operator evaluation and up to 175 GB/s of memory throughput. Finally, we also show that merging the more arithmetically heavy operator evaluation with vector operations in application code allows to more than double efficiency on...

Tensor Network Circuit Simulation at Exascale

Tensor network methods are incredibly effective for simulating quantum circuits. This is due to t... more Tensor network methods are incredibly effective for simulating quantum circuits. This is due to their ability to efficiently represent and manipulate the wave-functions of large interacting quantum systems. We describe the challenges faced when scaling tensor network simulation approaches to Exascale compute platforms and introduce QuantEx, a framework for tensor network circuit simulation at Exascale.

Report on Application Enabling for Capability Science in the MIC Architecture Final

Best Practice Guide - Modern Interconnects

Performance Optimisation of the Parallel CFD Code MGLET across Different HPC Platforms

Proceedings of the Platform for Advanced Scientific Computing Conference, Jun 12, 2019

This paper presents the optimisation techniques implemented to run across four HPC platforms the ... more This paper presents the optimisation techniques implemented to run across four HPC platforms the finite-volume computational fluid dynamics (CFD) code MGLET (Multi Grid Large Eddy Turbulence). We analysed and applied refactoring to the parallel communication routines, and reduced the memory footprint significantly, resulting in a substantial improvement of the parallel-scaling capability and in an increase of the maximum number of degrees of freedom for applications. Data structures and files layout were redesigned for implementing parallel I/O in HDF5. The new parallel I/O strategy results in a considerable increase in the average data transfer rate compared with the former serial implementation. An I/O pattern analysis and detailed I/O profiling of the new implementation were then conducted and further performance improvement was achieved by increasing the size of I/O requests and reducing the number of I/O processes. We compare the improved parallel-scaling capability of MGLET on different architectures using representative CFD application test cases.

Best Practice Guide - GPGPU

This Best Practice Guide describes general purpose computation on Graphics Processing Units (GPUs... more This Best Practice Guide describes general purpose computation on Graphics Processing Units (GPUs). GPUs were originally developed for computer gaming and other graphical tasks, but for many years have been exploited for general purpose computing across a number of areas. They offer advantages over traditional CPUs because they have greater computational capability and use high-bandwidth memory systems (with memory bandwidth being the main bottleneck for many scientific applications). The guide includes information on how to get started with programming GPUs, which cannot be used in isolation but only as "accelerators" in conjunction with CPUs, and how to get good performance. Focus is given to NVIDIA GPUs, which are most widespread today. The GPGPU Best Practice Guide is based on the PRACE-2IP GPGPU Best Practice Mini-Guide. The following new topics were added: GPU architecture especially highlighting new features of NVIDIA Pascal, OpenCL Programming, OpenMP 4.x Offloadin...

A next-generation discontinuous galerkin fluid dynamics solver with application to high-resolution lung airflow simulations

Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis

We present a novel, highly scalable and optimized solver for turbulent flows based on high-order ... more We present a novel, highly scalable and optimized solver for turbulent flows based on high-order discontinuous Galerkin discretizations of the incompressible Navier-Stokes equations aimed to minimize time-to-solution. The solver uses explicit-implicit time integration with variable step size. The central algorithmic component is the matrix-free evaluation of discretized finite element operators. The node-level performance is optimized by sum-factorization kernels for tensor-product elements with unique algorithmic choices that reduce the number of arithmetic operations, improve cache usage, and vectorize the arithmetic work across elements and faces. These ingredients are integrated into a framework scalable to the massive parallelism of supercomputers by the use of optimal-complexity linear solvers, such as mixed-precision, hybrid geometric-polynomial-algebraic multigrid solvers for the pressure Poisson problem. The application problem under consideration are fluid dynamical simulations of the human respiratory system under mechanical ventilation conditions, using unstructured/structured

The Mont-Blanc Prototype: An Alternative Approach for HPC Systems

SC16: International Conference for High Performance Computing, Networking, Storage and Analysis

High-performance computing (HPC) is recognized as one of the pillars for further advance of scien... more High-performance computing (HPC) is recognized as one of the pillars for further advance of science, industry, medicine, and education. Current HPC systems are being developed to overcome emerging challenges in order to reach Exascale level of performance, which is expected by the year 2020. The much larger embedded and mobile market allows for rapid development of IP blocks, and provides more flexibility in designing an application-specific SoC, un turn giving possibility in balancing performance, energy-efficiency and cost. In the Mont-Blanc project, we advocate for HPC systems be built from such commodity IP blocks, currently used in embedded and mobile SoCs. As a first demonstrator of such approach, we present the Mont-Blanc prototype; the first HPC system built with commodity SoCs, memories, and NICs from the embedded and mobile domain, and offthe-shelf HPC networking, storage, cooling and integration solutions. We present the system's architecture, and evaluation including both performance and energy efficiency. Further, we compare the system's abilities against a production level supercomputer. At the end, we discuss parallel scalability, and estimate the maximum scalability point of this approach across a set of applications.

Best Practice Guide - GPGPU

Graphics Processing Units (GPUs) were originally developed for computer gaming and other graphica... more Graphics Processing Units (GPUs) were originally developed for computer gaming and other graphical tasks,<br> but for many years have been exploited for general purpose computing across a number of areas. They offer<br> advantages over traditional CPUs because they have greater computational capability, and use high-bandwidth<br> memory systems (where memory bandwidth is the main bottleneck for many scientific applications).<br> This Best Practice Guide describes GPUs: it includes information on how to get started with programming GPUs,<br> which cannot be used in isolation but as "accelerators" in conjunction with CPUs, and how to get good performance.<br> Focus is given to NVIDIA GPUs, which are most widespread today.<br> In Section 2, "The GPU Architecture", the GPU architecture is described, with a focus on the latest "Pascal"<br> generation of NVIDIA GPUs, and attention is given to the architectural r...

Deploying Containerized QuanEX Quantum Simulation Software on HPC Systems

2021 3rd International Workshop on Containers and New Orchestration Paradigms for Isolated Environments in HPC (CANOPIE-HPC), 2021

The simulation of quantum circuits using the tensor network method is very computationally demand... more The simulation of quantum circuits using the tensor network method is very computationally demanding and requires significant High Performance Computing (HPC) resources to find an efficient contraction order and to perform the contraction of the large tensor networks. In addition, the researchers want a workflow that is easy to customize, reproduce and migrate to different HPC systems. In this paper, we discuss the issues associated with the deployment of the QuantEX quantum computing simulation software within containers on different HPC systems. Also, we compare the performance of the containerized software with the software running on "bare metal".

Deploying Containerized QuanEX Quantum Simulation Software on HPC Systems

2021 3rd International Workshop on Containers and New Orchestration Paradigms for Isolated Environments in HPC (CANOPIE-HPC), 2021

The simulation of quantum circuits using the tensor network method is very computationally demand... more The simulation of quantum circuits using the tensor network method is very computationally demanding and requires significant High Performance Computing (HPC) resources to find an efficient contraction order and to perform the contraction of the large tensor networks. In addition, the researchers want a workflow that is easy to customize, reproduce and migrate to different HPC systems. In this paper, we discuss the issues associated with the deployment of the QuantEX quantum computing simulation software within containers on different HPC systems. Also, we compare the performance of the containerized software with the software running on “bare metal”.

QXTools: A Julia framework for distributed quantum circuit simulation

Journal of Open Source Software, 2022

QXTools is a framework for simulating quantum circuits using tensor network methods. Weak simulat... more QXTools is a framework for simulating quantum circuits using tensor network methods. Weak simulation is the primary use case where given a quantum circuit and input state QXTools will efficiently calculate the probability amplitude of a given output configuration or set of configurations. Given this ability one can sample from the output distribution using random sampling approaches. QXTools is intended to be used by researchers interested in simulating circuits larger than those possible with full wave-function simulators or those interested in research and development of tensor network circuit simulation methods. See Brennan et al. (2021) for more complete background and scaling results and Brayford et al. (2021) for details about deploying in containerised environments.

SuperMUC Phase 2: Challenges of Peta-scale applications

First experiences with the Intel MIC architecture at LRZ

ArXiv, 2013

With the rapidly growing demand for computing power new accelerator based architectures have ente... more With the rapidly growing demand for computing power new accelerator based architectures have entered the world of high performance computing since around 5 years. In particular GPGPUs have recently become very popular, however programming GPGPUs using programming languages like CUDA or OpenCL is cumbersome and error-prone. Trying to overcome these difficulties, Intel developed their own Many Integrated Core (MIC) architecture which can be programmed using standard parallel programming techniques like OpenMP and MPI. In the beginning of 2013, the first production-level cards named Intel Xeon Phi came on the market. LRZ has been considered by Intel as a leading research centre for evaluating coprocessors based on the MIC architecture since 2010 under strict NDA. Since the Intel Xeon Phi is now generally available, we can share our experience on programming Intel's new MIC architecture.

Node-Level optimization of a 3D Block-Based Multiresolution Compressible Flow Solver with Emphasis on Performance Portability

2019 International Conference on High Performance Computing & Simulation (HPCS), 2019

Despite the enormous increase in computational power in the last decades, the numerical study of ... more Despite the enormous increase in computational power in the last decades, the numerical study of complex flows remains challenging. State-of-the-art techniques to simulate hyperbolic flows with discontinuities rely on computationally demanding nonlinear schemes, such as Riemann solvers with weighted essentially non-oscillatory (WENO) stencils and characteristic decompositioning. To handle this complexity the numerical load can be reduced via a multiresolution (MR) algorithm with local time stepping (LTS) running on modern high-performance computing (HPC) systems. Eventually, the main challenge lies in an efficitent utilization of the available HPC hardware. In this work, we evaluate the performance improvement for a Message Passing Interface (MPI)-parallelized MR solver using single instruction multiple data (SIMD) optimizations. We present straight-forward code modifications that allow for auto-vectorization by the compiler, while maintaining the modularity of the code at comparabl...

Improving scalability for the CFD software package MGLET

Fast Matrix-Free Discontinuous Galerkin Kernels on Modern Computer Architectures

Lecture Notes in Computer Science

This study compares the performance of high-order discontinuous Galerkin finite elements on moder... more This study compares the performance of high-order discontinuous Galerkin finite elements on modern hardware. The main computational kernel is the matrix-free evaluation of differential operators by sum factorization, exemplified on the symmetric interior penalty discretization of the Laplacian as a metric for a complex application code in fluid dynamics. State-of-the-art implementations of these kernels stress both arithmetics and memory transfer. The implementations of SIMD vectorization and shared-memory parallelization are detailed. Computational results are presented for dual-socket Intel Haswell CPUs at 28 cores, a 64-core Intel Knights Landing, and a 16-core IBM Power8 processor. Up to polynomial degree six, Knights Landing is approximately twice as fast as Haswell. Power8 performs similarly to Haswell, trading a higher frequency for narrower SIMD units. The performance comparison shows that simple ways to express parallelism through for loops perform better on medium and high core counts than a more elaborate task-based parallelization with dynamic scheduling according to dependency graphs, despite less memory transfer in the latter algorithm.

Accurate and efficient QM / MM molecular dynamics on 86 , 016 cores of SuperMUC Phase 2

Ferdinand Jamitzky Leibniz Supercomputing Centre (LRZ) Boltzmannstrasse 1 85748 Garching, Germany... more Ferdinand Jamitzky Leibniz Supercomputing Centre (LRZ) Boltzmannstrasse 1 85748 Garching, Germany [email protected] Helmut Satzger Leibniz Supercomputing Centre (LRZ) Boltzmannstrasse 1 85748 Garching, Germany [email protected] Gerald Mathias Ludwig-MaximiliansUniversität München, Lehrstuhl für BioMolekulare Optik Oettingenstrasse 67 80538 München, Germany [email protected]

Extreme Scale-out SuperMUC Phase 2 - lessons learned

In spring 2015, the Leibniz Supercomputing Centre (Leibniz-Rechenzentrum, LRZ), installed their n... more In spring 2015, the Leibniz Supercomputing Centre (Leibniz-Rechenzentrum, LRZ), installed their new Peta-Scale System SuperMUC Phase2. Selected users were invited for a 28 day extreme scale-out block operation during which they were allowed to use the full system for their applications. The following projects participated in the extreme scale-out workshop: BQCD (Quantum Physics), SeisSol (Geophysics, Seismics), GPI-2/GASPI (Toolkit for HPC), Seven-League Hydro (Astrophysics), ILBDC (Lattice Boltzmann CFD), Iphigenie (Molecular Dynamic), FLASH (Astrophysics), GADGET (Cosmological Dynamics), PSC (Plasma Physics), waLBerla (Lattice Boltzmann CFD), Musubi (Lattice Boltzmann CFD), Vertex3D (Stellar Astrophysics), CIAO (Combustion CFD), and LS1-Mardyn (Material Science). The projects were allowed to use the machine exclusively during the 28 day period, which corresponds to a total of 63.4 million core-hours, of which 43.8 million core-hours were used by the applications, resulting in a ut...

The Mont-Blanc Project: First Phase Successfully Finished

ArXiv, 2015

Running from October 2011 to June 2015, the aim of the European project Mont-Blanc has been to de... more Running from October 2011 to June 2015, the aim of the European project Mont-Blanc has been to develop an approach to Exascale computing based on embedded power-efficient technology. The main goals of the project were to i) build an HPC prototype using currently available energy-efficient embedded technology, ii) design a Next Generation system to overcome the limitations of the built prototype and iii) port a set of representative Exascale applications to the system. This article summarises the contributions from the Leibniz Supercomputing Centre (LRZ) and the Juelich Supercomputing Centre (JSC), Germany, to the Mont-Blanc project.

Efficient High-Order Discontinuous Galerkin Finite Elements with Matrix-Free Implementations

This work presents high-order discontinuous Galerkin finite element kernels optimized for node-le... more This work presents high-order discontinuous Galerkin finite element kernels optimized for node-level performance on a series of Intel architectures ranging from Sandy Bridge to Skylake. The kernels implement matrix-free evaluation of integrals with sum factorization techniques. In order to increase performance and thus to help to achieve higher energy efficiency, this work proposes an element-based shared-memory parallelization option and compares it to a well-established shared-memory parallelization with global face data. The new algorithm is supported by the relevant metrics in terms of arithmetics and memory transfer. On a single node with \(2\times 24\) cores of Intel Skylake Scalable, we report more than 1,200 GFLOPs/s in double precision for the full operator evaluation and up to 175 GB/s of memory throughput. Finally, we also show that merging the more arithmetically heavy operator evaluation with vector operations in application code allows to more than double efficiency on...

Tensor Network Circuit Simulation at Exascale

Tensor network methods are incredibly effective for simulating quantum circuits. This is due to t... more Tensor network methods are incredibly effective for simulating quantum circuits. This is due to their ability to efficiently represent and manipulate the wave-functions of large interacting quantum systems. We describe the challenges faced when scaling tensor network simulation approaches to Exascale compute platforms and introduce QuantEx, a framework for tensor network circuit simulation at Exascale.

Report on Application Enabling for Capability Science in the MIC Architecture Final

Best Practice Guide - Modern Interconnects

Performance Optimisation of the Parallel CFD Code MGLET across Different HPC Platforms

Proceedings of the Platform for Advanced Scientific Computing Conference, Jun 12, 2019

This paper presents the optimisation techniques implemented to run across four HPC platforms the ... more This paper presents the optimisation techniques implemented to run across four HPC platforms the finite-volume computational fluid dynamics (CFD) code MGLET (Multi Grid Large Eddy Turbulence). We analysed and applied refactoring to the parallel communication routines, and reduced the memory footprint significantly, resulting in a substantial improvement of the parallel-scaling capability and in an increase of the maximum number of degrees of freedom for applications. Data structures and files layout were redesigned for implementing parallel I/O in HDF5. The new parallel I/O strategy results in a considerable increase in the average data transfer rate compared with the former serial implementation. An I/O pattern analysis and detailed I/O profiling of the new implementation were then conducted and further performance improvement was achieved by increasing the size of I/O requests and reducing the number of I/O processes. We compare the improved parallel-scaling capability of MGLET on different architectures using representative CFD application test cases.

Best Practice Guide - GPGPU

This Best Practice Guide describes general purpose computation on Graphics Processing Units (GPUs... more This Best Practice Guide describes general purpose computation on Graphics Processing Units (GPUs). GPUs were originally developed for computer gaming and other graphical tasks, but for many years have been exploited for general purpose computing across a number of areas. They offer advantages over traditional CPUs because they have greater computational capability and use high-bandwidth memory systems (with memory bandwidth being the main bottleneck for many scientific applications). The guide includes information on how to get started with programming GPUs, which cannot be used in isolation but only as "accelerators" in conjunction with CPUs, and how to get good performance. Focus is given to NVIDIA GPUs, which are most widespread today. The GPGPU Best Practice Guide is based on the PRACE-2IP GPGPU Best Practice Mini-Guide. The following new topics were added: GPU architecture especially highlighting new features of NVIDIA Pascal, OpenCL Programming, OpenMP 4.x Offloadin...

A next-generation discontinuous galerkin fluid dynamics solver with application to high-resolution lung airflow simulations

Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis

We present a novel, highly scalable and optimized solver for turbulent flows based on high-order ... more We present a novel, highly scalable and optimized solver for turbulent flows based on high-order discontinuous Galerkin discretizations of the incompressible Navier-Stokes equations aimed to minimize time-to-solution. The solver uses explicit-implicit time integration with variable step size. The central algorithmic component is the matrix-free evaluation of discretized finite element operators. The node-level performance is optimized by sum-factorization kernels for tensor-product elements with unique algorithmic choices that reduce the number of arithmetic operations, improve cache usage, and vectorize the arithmetic work across elements and faces. These ingredients are integrated into a framework scalable to the massive parallelism of supercomputers by the use of optimal-complexity linear solvers, such as mixed-precision, hybrid geometric-polynomial-algebraic multigrid solvers for the pressure Poisson problem. The application problem under consideration are fluid dynamical simulations of the human respiratory system under mechanical ventilation conditions, using unstructured/structured

The Mont-Blanc Prototype: An Alternative Approach for HPC Systems

SC16: International Conference for High Performance Computing, Networking, Storage and Analysis

High-performance computing (HPC) is recognized as one of the pillars for further advance of scien... more High-performance computing (HPC) is recognized as one of the pillars for further advance of science, industry, medicine, and education. Current HPC systems are being developed to overcome emerging challenges in order to reach Exascale level of performance, which is expected by the year 2020. The much larger embedded and mobile market allows for rapid development of IP blocks, and provides more flexibility in designing an application-specific SoC, un turn giving possibility in balancing performance, energy-efficiency and cost. In the Mont-Blanc project, we advocate for HPC systems be built from such commodity IP blocks, currently used in embedded and mobile SoCs. As a first demonstrator of such approach, we present the Mont-Blanc prototype; the first HPC system built with commodity SoCs, memories, and NICs from the embedded and mobile domain, and offthe-shelf HPC networking, storage, cooling and integration solutions. We present the system's architecture, and evaluation including both performance and energy efficiency. Further, we compare the system's abilities against a production level supercomputer. At the end, we discuss parallel scalability, and estimate the maximum scalability point of this approach across a set of applications.

Report on Applications Enabling for Capability Science in the MIC Architecture, PRACE-1IP D7.1.3

by Volker Weinberg and Momme Allalen