Books by Volker Weinberg
PRACE Best Practice Guides, 2019
PRACE Best Practice Guides, 2019
PRACE Best Practice Guides, 2019
PRACE Best Practie Guides, 2019
Advances and New Trends in Environmental Informatics - Managing Disruption, Big Data and Open Science, Oct 1, 2018
This book presents the latest findings and ongoing research in the field of environmental informa... more This book presents the latest findings and ongoing research in the field of environmental informatics. It addresses a wide range of cross-cutting activities, such as efficient computing, virtual reality, disruption management, big data, open science and the internet of things, and showcases how these green information & communication technologies (ICT) can be used to effectively address environmental and societal challenges. Presenting a selection of extended contributions to the 32nd edition of the International Conference EnviroInfo 2018, at the Leibniz Supercomputing Centre in Garching near Munich, it is essential reading for anyone looking to expand their expertise in the area.
Environmental Informatics, Techniques and Trends, 2018
This book presents the latest findings and ongoing research in the field of environmental informa... more This book presents the latest findings and ongoing research in the field of environmental informatics. It addresses a wide range of cross-cutting activities such as recent advances in environmental informatics, Internet of Things technologies, challenges in ICT-technologies, disaster management, energy aware software-engineering and development, environmental health informatics, environmental information systems, machine learning, open science and sustainable mobility. The book contains selected short and work in progress papers of the 32nd International Conference EnviroInfo 2018 at the Leibniz Supercomputing Centre of the Bavarian Academy of Sciences and Humanities (LRZ) in Garching near Munich.
This Best Practice Guide written from scratch provides information about Intel's Haswell/Broadwel... more This Best Practice Guide written from scratch provides information about Intel's Haswell/Broadwell architecture in order to enable programmers to achieve good performance of their applications. The guide covers a wide range of topics from the description and comparison of the hardware of the Haswell/Broadwell processor, through information about the compiler usage as well as information about porting programs up to tools and strategies how to analyse and improve the performance of applications. With the introduction of extra vector instructions with these processors (fused multiply add etc.) stronger focus is placed on vectorisation. In the tuning context several of the tuning tools provided by Intel are demonstrated and examples are given on how to use command line tools to collect data in batch mode. Furthermore, the guide provides information about the following European Intel Haswell/Broadwell based European systems: Hazel Hen @ HLRS, Germany, Minotauro @ BSC, Spain, Salomon @ IT4Innovations, Czech Republic, SuperMUC Phase 2 @ LRZ, Germany.
This Best Practice Guide describes general purpose computation on Graphics Processing Units (GPUs... more This Best Practice Guide describes general purpose computation on Graphics Processing Units (GPUs). GPUs were originally developed for computer gaming and other graphical tasks, but for many years have been exploited for general purpose computing across a number of areas. They offer advantages over traditional CPUs because they have greater computational capability and use high-bandwidth memory systems (with memory bandwidth being the main bottleneck for many scientific applications). The guide includes information on how to get started with programming GPUs, which cannot be used in isolation but only as "accelerators" in conjunction with CPUs, and how to get good performance. Focus is given to NVIDIA GPUs, which are most widespread today. The GPGPU Best Practice Guide is based on the PRACE-2IP GPGPU Best Practice Mini-Guide. The following new topics were added: GPU architecture especially highlighting new features of NVIDIA Pascal, OpenCL Programming, OpenMP 4.x Offloading. Several existing sections have been updated to reflect recent changes.
This Best Practice Guide provides information about Intel’s MIC architecture and programming mode... more This Best Practice Guide provides information about Intel’s MIC architecture and programming models for the first generation Intel® Xeon Phi™ coprocessor named Knights Corner (KNC) in order to enable programmers to achieve good performance out of their applications. The guide covers a wide range of topics from the description of the hardware of the Intel® Xeon Phi™ coprocessor through information about the basic programming models as well as information about porting programs up to tools and strategies how to analyse and improve the performance of applications. The guide was created based on the PRACE-3IP Intel® Xeon Phi™ Best Practice Guide. New is the inclusion of information about European Intel® Xeon Phi™ based systems. The following systems are now described: •Avitohol @ IICT-BAS, Bulgary, MareNostrum @ BSC, Spain, Salomon @ IT4Innovations, Czech Republic, SuperMIC @ LRZ, Germany. Furthermore, the following new sections are included: OpenMP 4.x Offloading, OpenCL, Intel Cilk Plus / MYO, Information about some selected applications ported to Intel® Xeon Phi™, Benchmark results using e.g. the PRACE Accelerator Benchmark Suite. Several existing sections have been updated to reflect recent changes.
This best practice guide provides information about Intel's MIC architecture and programming ... more This best practice guide provides information about Intel's MIC architecture and programming models for the Intel Xeon Phi coprocessor in order to enable programmers to achieve good performance of their pplications. The guide covers a wide range of topics from the description of the hardware of the Intel Xeon Phi coprocessor through information about the basic programming models as well as information about porting programs up to tools and strategies how to analyze and improve the performance of applications.
This best practice guide provides information about SuperMUC in order to enable users of the syst... more This best practice guide provides information about SuperMUC in order to enable users of the system to achieve good performance of their applications. The guide covers a wide range of topics from the detailed description of the hardware through information about the basic production environment including how to login and the accounting procedure as well as information about porting and submitting jobs, up to tools and strategies on how to analyze and improve the performance of applications. The guide includes contributions from LRZ, Nikos Anastopoulos (NTUA/GRNET) and Petri Nikunen (CSC).
Papers by Volker Weinberg
Three complementary views on the QCD vacuum structure, all based on eigenmodes of the overlap ope... more Three complementary views on the QCD vacuum structure, all based on eigenmodes of the overlap operator, are reported in their interrelation: (i) spectral density, localization and chiral properties of the modes, (ii) the possibility of filtering the field strength with the aim to detect selfdual and antiselfdual domains and (iii) the various faces of the topological charge density, with and without a cutoff λ cut = O(Λ QCD). The techniques are tested on quenched SU(3) configurations.
As code optimisation techniques are getting more and more important in HPC, LRZ @ GCS as one of t... more As code optimisation techniques are getting more and more important in HPC, LRZ @ GCS as one of the six European PRACE Advanced Training Centres (PATC) has extended its curriculum by a new PATC course " HPC code optimisation workshop " , which took place at LRZ on May 4, 2017 for the first time.
For the fourth time the Czech-Bavarian Competence Centre for Supercomputing Applications, CzeBaCC... more For the fourth time the Czech-Bavarian Competence Centre for Supercomputing Applications, CzeBaCCA, has organised a technical Intel Many Integrated Core (MIC) programming workshop combined with a scientific workshop about HPC simulations in the field of environmental sciences. The Czech-Bavarian Competence Centre was established in 2016 by the Leibniz Supercomputing Centre (LRZ), the Department of Informatics of the Technical University of Munich (TUM) and the IT4Innovations National Supercomputing Centre of the Czech Republic to foster the Czech-German collaboration in high performance computing. One of the main objectives of the Competence Centre is to organise a series of Intel Xeon Phi specific technical workshops combined with scientific symposia on topics like optimisation of simulation codes in environmental science.
The Leibniz Supercomputing Centre publishes in this booklet the complete material of the Intel MI... more The Leibniz Supercomputing Centre publishes in this booklet the complete material of the Intel MIC programming workshop that took place at LRZ on June 26 – 28, 2017. The workshop discussed Intel’s Many Integrated Core (MIC) architecture and various programming models for Intel Xeon Phi co-/processors. The workshop covered a wide range of topics from the description of the hardware of the Intel Xeon Phi co-/processors through information about the basic programming models as well as information about vectorisation and MCDRAM usage up to tools and strategies how to analyse and improve the performance of applications. The workshop mainly concentrated on techniques relevant for Knights Landing (KNL) based systems. During a plenary session on the last day 8 invited speakers from IPCC@LRZ, IPCC@TUM, IPCC@IT4Innovations, Intel, RRZE, the University of Regensburg, IPP and MPCDF talked about Intel Xeon Phi experience and best practice recommendations. Hands-on sessions were done on the Knights Corner (KNC) based system SuperMIC and two KNL test systems at LRZ.
For the third time the Czech-Bavarian Competence Centre for Supercomputing Applications, CzeBaCCA... more For the third time the Czech-Bavarian Competence Centre for Supercomputing Applications, CzeBaCCA, has organised a technical Intel Many Integrated Core (MIC) programming workshop combined with a scientific workshop about HPC simulations in the field of geo- and environmental sciences. The Czech-Bavarian Competence Centre was established in 2016 by the Leibniz Supercomputing Centre (LRZ), the Department of Informatics of the Technical University of Munich (TUM) and the IT4Innovations National Supercomputing Centre of the Czech Republic to foster the Czech-German collaboration in high performance computing. One of the main objectives of the Competence Centre is to trigger new collaborations between Germans and Czech via scientific workshops and many-core architecture specific technical trainings.
To foster the Czech-German collaboration in high performance computing, the Leibniz Supercomputin... more To foster the Czech-German collaboration in high performance computing, the Leibniz Supercomputing Centre (LRZ), the Department of Informatics of TUM and the National Supercomputing Centre of the Czech Republic, IT4Innovations, recently joined forces and established the Czech-Bavarian Competence Centre for Supercomputing Applications (CzeBaCCA). Besides their joint research program around simulation software and tools for Salomon, one of the main objectives of the new Competence Centre is to organise a series of scientific workshops and Intel MIC (Many Integrated Core) architecture specific trainings. The article reports on the second series of workshops that took place at LRZ in Garching in June 2016 and combined a three-day “Intel MIC Programming Workshop” (June 27 – 29, 2016) with a three-day scientific workshop on “High Performance Computing for Water Related Hazards” (June 29 – July 1, 2016).
On 18-22 April 2016 the Leibniz Supercomputing Centre hosted the 21st VI-HPS Tuning Workshop in a... more On 18-22 April 2016 the Leibniz Supercomputing Centre hosted the 21st VI-HPS Tuning Workshop in a very fruitful cooperation with the Jülich Supercomputing Centre (JSC) and the VI-HPS consortium. This series of tuning workshops gives an overview of the VI-HPS performance analysis and tuning tools suite, explains the functionality of individual tools and how to use them effectively, and offers hands-on experience and expert assistance using these tools on participants' own applications.
Most HPC systems are clusters of shared memory nodes. These SMP nodes can be small multi-core CPU... more Most HPC systems are clusters of shared memory nodes. These SMP nodes can be small multi-core CPUs up to large many-core CPUs. Parallel programming may combine the distributed memory parallelisation on the node interconnect (e.g., using MPI) with the shared memory parallelisation inside of each node (e.g., using OpenMP or MPI-3.0 shared memory). As such hybrid programming techniques are getting more and more important in HPC, GCS as one of the 6 European PRACE Advanced Training Centres (PATC) has extended its curriculum by a new PATC course on hybrid programming techniques, which took place at LRZ on January 14, 2016 for the first time.
To foster the Czech-German collaboration in high performance computing, the Leibniz Supercomputin... more To foster the Czech-German collaboration in high performance computing, the Leibniz Supercomputing Centre (LRZ), the Department of Informatics of TUM and the National Supercomputing Centre of the Czech Republic, IT4Innovations, recently joined forces and established the Czech-Bavarian Competence Centre for Supercomputing Applications (CzeBaCCA).
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Books by Volker Weinberg
Papers by Volker Weinberg
This document aims to provide an overview of these requirements by assessing the needs of user communities and of HPC centres in terms of technologies and architectures for next generation HPC systems evolving towards Exascale. For this purpose, surveys have been conducted among recently started Centres of Excellences (CoEs) in Europe for collecting the requirements from HPC user communities. A different survey has been distributed to all PRACE Tier-0/Tier-1 HPC sites to understand how these requirements differ from the current state of the art, to determine the requirements of HPC centres, and possibly motivate related prototyping efforts.
PRACE-5IP continued the training activities of PRACE-4IP starting from February 2017. Between February 2017 and April 2018, the six PATCs delivered 103 courses, 290 course-days with 2,396 participants, while the four PTCs delivered 12 courses, 21 course-days with 351 participants. The feedback responses received have been overwhelmingly positive (8.5/10 average overall rating for PATC courses).
Similarly, the PRACE Seasonal Schools in PRACE-5IP have been carefully selected via a formal selection process. The Seasonal Schools scheduled for this reporting period, namely the Autumn School 2017 in Gdańsk, Poland and the Winter Seasonal School 2018 in Bratislava, Slovak Republic, attracted 39 attendees in total, and obtained high overall ratings.
In addition, WP4 continued the collaboration with the Centres of Excellence (CoEs) where a number of On-demand events were organised. Finally, WP4 co-organised the 2017 International Summer School on HPC Challenges in Computational Sciences in Boulder, Colorado, United States of America, from 25-30June 2017.
All forms of face-to-face and online training are complementary. They contribute to the success of the PRACE training programme, and should be continued in future PRACE HPC training activities. In accordance with the PRACE-5IP goals, the majority of training events also address industrial users, and motivate them by showing the importance and benefits of HPC for the practice.