Papers by Richard Hagelauer
An adaptive DCO (Digital Controlled Oscillator) gain tracking algorithm for an ADPLL (All Digital... more An adaptive DCO (Digital Controlled Oscillator) gain tracking algorithm for an ADPLL (All Digital Phase Locked Loops), which is working as a frequency synthesizer, is presented in this paper. By using this DCO gain real-time tracking method, the requirement of DCO linearity and the complexity of the circuits can be highly decreased. The result shows that with introducing a small amount of training signal the actual DCO gain can be accurately estimated in short time with a fine resolution and the EVM (Error Vector Magnitude) performance is improved significantly.
2005 IEEE 16th International Symposium on Personal, Indoor and Mobile Radio Communications
This paper describes the concept of a highly reconfigurable digital-front-end (DFE) enabling mult... more This paper describes the concept of a highly reconfigurable digital-front-end (DFE) enabling multi-mode capable RF receivers for cellular applications, based on the well known direct conversion receiver (DCR) architecture. Its main functionality includes sample-rate-conversion, channel selection filtering, dynamic range control, imbalance correction and matched filtering. The described partitioning shifts some of the functionality, normally located in the analog-front-end (channel filtering,
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)
Abstract - Driven by the recent advances in VLSI technology long-standing controller architecture... more Abstract - Driven by the recent advances in VLSI technology long-standing controller architectures exper-ience a revival. The fast emerging IP (IntefZectuul Property) market is demanding for embedded soft cores of well-established microcontrollers such as the 8051 and 68HC1 12, ,,System ...
2015 IEEE 13th International Symposium on Intelligent Systems and Informatics (SISY), 2015
In the modern verification environment the FPGA-based prototyping has become an important part of... more In the modern verification environment the FPGA-based prototyping has become an important part of the whole verification flow. The ability to simulate real time application in the more realistic speeds allows much higher coverage than traditional HDL logic simulators. The main disadvantage of FPGA prototyping is inability to inspect and observe internal FPGA signals. Currently the only commercial solution for this problem is using embedded trace-buffers to record subsets of internal signals. This requires that the problem is first detected and then designer can implement additional trace-buffers and make new synthesis. This paper, presents an automatic debug circuit which allows easy access and extraction of all internal signals. The debug circuit is built on a remaining FPGA resources so it's important that this does not have a negative effect on the FPGA performance. The experiments showed that the automatic debug circuit does not significantly reduces FPGA performance and that it can be used for FPGA rapid prototyping.
2015 25th International Conference on Field Programmable Logic and Applications (FPL), 2015
In the modern verification environment an FPGA-based prototyping has become an important part of ... more In the modern verification environment an FPGA-based prototyping has become an important part of the whole verification flow. The ability to simulate real time application in more realistic speeds allows much higher coverage than traditional HDL logic simulators. The main disadvantage of FPGA prototyping is inability to inspect and observe internal FPGA signals. Currently there are two traditional solutions for this problem. The first solution is using embedded trace-buffers to record a subset of internal signals and the second solution captures a snapshot of the current FPGA state. Both of these techniques have certain benefits and shortcomings. In this paper, we present an idea of merging these two techniques into a new hybrid approach. Using this idea we created a hybrid circuit and during our experiments showed that it preserves all good sides from both traditional approaches.
2007 European Conference on Wireless Technologies, 2007
The polar transmitter concept promises significant higher power efficiency utilizing nonlinear po... more The polar transmitter concept promises significant higher power efficiency utilizing nonlinear power amplifiers. RF transmitters using polar transmitter technique are currently available for EDGE systems and are under development for UMTS. The UMTS extensions HSDPA and HSUPA provide a number of additional physical uplink channels which can lead to a variety of constellations incorporating constellation points at the I/Q origin.
Proceedings on Bipolar Circuits and Technology Meeting
A monolithic comparator with sample rates up to 1.9 Gbit/s integrated on an analog array is prese... more A monolithic comparator with sample rates up to 1.9 Gbit/s integrated on an analog array is presented. The circuit has been implemented on an analog array in a standard bipolar process. A parallel circuit structure doubles the maximum sampling rate. The analog array has been customized with two metal layers. Performance data such as the maximum data rate of 1.9
Proceedings Design, Automation and Test in Europe, 1998
This paper discusses issues of graphical modelling of Finite State Machines with Datapath (FSMDs)... more This paper discusses issues of graphical modelling of Finite State Machines with Datapath (FSMDs). Tools supporting the graphical entry of state based systems are usable by intuition, but need to be based on an exact definition of semantics of graphical elements. This paper proposes to define semantics of graphical models based on the hardware description language VHDL.
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
Fully digital frequency synthesizers are increasingly used in radio frequency (RF) transceivers. ... more Fully digital frequency synthesizers are increasingly used in radio frequency (RF) transceivers. The estimation and calibration of the gain for digital controlled oscillator (DCO) and time-to-digital converter (TDC) which is subject to process, voltage and temperature (PVT) variations are important area of research since they can increase the performance and reduce the complexity of the all digital phase locked loops (ADPLL). Normally these two calibration algorithms are implemented separately. In this paper, an overall gain (including DCO gain and TDC gain) tracking algorithm for an ADPLL is presented. The algorithm is based on correlation analysis used in system identification to estimate the unknown impulse response from DCO input to TDC output by applying a training signal. The result shows that with a sufficiently long training sequence, the accuracy of the estimation result will be within a very fine resolution.
A high performance latched comparator is implemented in a 0.5 μm GaAs HEMT technology. Measuremen... more A high performance latched comparator is implemented in a 0.5 μm GaAs HEMT technology. Measurement results verify the comparator is able to operate up to 4 Gs/s and has a 10 mV sensitivity.
Lecture Notes in Computer Science, 2014
Advances in Radio Science, 2004
Die Verifikation von digitalen Schaltungen nimmt heutzutage einen bedeutenden Stellenwert ein. In... more Die Verifikation von digitalen Schaltungen nimmt heutzutage einen bedeutenden Stellenwert ein. In diesem Paper wird ein Weg beschrieben, der die Erstellung und Wartung von funktionalen Testbenches für digitale Designs unterstützt. Für viele Projekte übersteigt der zeitliche Aufwand für das Testen den Aufwand für die Implementierung der Schaltung. In vielen Fällen beträgt der Aufwand für das Testen bereits 70% des Entwicklungsaufwands
IEEE Transactions on Industrial Electronics, 2000
Proceedings of the 8th ACM workshop on Performance monitoring and measurement of heterogeneous wireless and wired networks - PM2HW2N '13, 2013
ABSTRACT After a decade of research in the field of wireless sensor networks the energy consumpti... more ABSTRACT After a decade of research in the field of wireless sensor networks the energy consumption remains the dominating constraint. Complex algorithms with non-negligible runtimes must be processed by resource-limited nodes, and therefore require in-depth knowledge of the temporal behavior of the software and hardware components. However, state-of-the-art simulators provide either accuracy or scalability and therefore somehow limit the development of such networks. We present a novel and unique methodology for energy-aware, time-accurate, and scalable simulation of wireless sensor networks that considers software, hardware, and network components. Algorithms implemented in C are annotated with binary runtime information and are executed natively on the host cpu, i.e., the cpu where the simulation is run. Arbitrary hardware can be modeled at various levels of abstraction and is simulated together with the software. Important effects such as interrupt processing are simulated accurately. As a proof of concept we implemented the proposed methodology and present STEAM-Sim, a novel simulation environment. We evaluated STEAM-Sim by means of a proprietary networking scenario typically used in industrial wireless sensor networks. Preliminary results regarding scalability and accuracy are presented.
Proceedings of the 13th ACM international conference on Modeling, analysis, and simulation of wireless and mobile systems - MSWIM '10, 2010
In this paper, we present a methodology to establish an accurate and power-aware simulation of wi... more In this paper, we present a methodology to establish an accurate and power-aware simulation of wireless sensor networks. As the design of software applications running on resource-constrained sensor nodes mainly influences both timing and power consumption in the network, it is crucial to include these components in the simulation. Besides considering the software aspect in the network, it is also important to obtain a detailed and accurate power consumption profile of every hardware module present in the network. Our methodology extends the PAWiS framework, which builds upon the well known discrete event network simulator OMNeT++. The framework was extended to include natively executing real-life application code written in the C language. Using a time-annotation process brings the timing aspect of application code execution into the simulation, and therefore increases simulation accuracy. Moreover, the presented partitioning of the application code into software layers provides easy porting of the simulated code to real sensor nodes. This concept does not impose any restrictions with respect to the target platform used or the OS running on it. To demonstrate the functionality of this approach, the methodology was applied to a real-world networking test scenario, and the achieved simulation results were compared to real-world measurements. The performance of the simulation environment was evaluated and is presented.
2003 IEEE International Symposium on Electromagnetic Compatibility, 2003. EMC '03., 2003
In this paper we present two test-chips, which were used to characterize the influence of the pla... more In this paper we present two test-chips, which were used to characterize the influence of the placement of on-chip decoupling capacitor blocks on the electromagnetic emission of integrated circuits. In general the electromagnetic emission could be reduced by the use of on-chip capacitors, but also an increase of the emission is possible, when these capacitors are not optimally placed
2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers, 2000
A singlechip, fully-integrated 3G UMTSm-CDMA tnnxdvcr hsJ k e n implemented ii a sOndard 75-GHfl3... more A singlechip, fully-integrated 3G UMTSm-CDMA tnnxdvcr hsJ k e n implemented ii a sOndard 75-GHfl35-pm SiGe BiCMOS p r a s s for we in FDD mobile terminals. The d c sign comprker two inqer-NKrsetional-N synthsizen wilh fully integrated CMOS VCO's, -hie tuning and PLL, a z-IF receiver and a did-mnrersion transmiller. The I P I~F receiver include a dflerential-input biplar, low-nohe amplifier (2nd LNA), a down-mnwrter wilh CMOS Gilkrt lype mixers followed by a lownoise buffer amplifier, an analog acliw bareband filler d Sthurdcr with automatie on-chip filler calibration and interleaved wilh a p m grammsblr gain amplifier, and a pmgrammable bareband output buffer. The dimt-conversion IranSmithr indudes a 41th-order analog active baseband filler, a bipolsr d i d rnodulstion up-conierler, and a variable gain RF amplifier m'lh >WdB gain eontml range, and B 3dBm power amplifier driver. The I n~c~i v e r is fully-pmgrammable via two serial Prim-bus inlrrfams. The device operate al2.7-3.OV supply and mssume 3SmA and SP7SmA, in Ihe receive mode and in +he tranwait mode, cespeetiwly. Thr tramdyer ir mounted in a $mall outline, 40-pin, kadles, 55x6.5mmz surface mount package and fully mmplies with ARlB W-CDMA and UMTS standards.
WCC 2000 - ICSP 2000. 2000 5th International Conference on Signal Processing Proceedings. 16th World Computer Congress 2000, 2000
... This paper describes an alternative new approach for the use of an ultrasonic measurement uni... more ... This paper describes an alternative new approach for the use of an ultrasonic measurement unitbased on a continuous signal technique implemented in an au-tonomous robot vehicle. The measured results shown in this paper fit the exact distance data very well and ...
E I Elektrotechnik Und Informationstechnik, Nov 1, 2002
In this paper we report on the design and architecture of a single chip baseband processor IC for... more In this paper we report on the design and architecture of a single chip baseband processor IC for GSM/GPRS/EDGE cellular phone applications. S-GOLD is a mixed signal IC containing all analog and digital baseband functionality of a cellular radio. It is designed as a single chip solution, integrating the digital and mixed signal portions of the baseband in a leading
The software-defined-radio concept received increasing attention due to necessity of multi-mode/m... more The software-defined-radio concept received increasing attention due to necessity of multi-mode/multi-system capable terminals for next generation communication systems. This paper summarizes the requirements of a multi-mode compliant digital-front-end (DFE) and describes concepts for cellular terminal implementations on silicon. A partitioning is proposed wherein functionality, normally located in the analog-front-end, is shifted to the digital-front-end. This work concentrates on the receiver part of the digital-front-end.
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Papers by Richard Hagelauer