In this paper, we present an advanced RF modeling work for our state-of-the-art 45nm low-power CM... more In this paper, we present an advanced RF modeling work for our state-of-the-art 45nm low-power CMOS technology. Based on carefully designed structures, we extracted a rigorous, hardware-based wiring capacitance model that accurately computes each component of the wirecap network on top of the intrinsic FET. A novel, scalable substrate resistance model was created to well fit relevant hardware data. To obtain accurate on-wafer sparameter data for the modeling structures at high frequencies (up to 110GHz), we adopted sophisticated deembedding techniques such as Pad-Open-Short and COMPLETE. The results clearly show that our models well match various RF characteristics for devices with a broad range of sizes and measured at different voltage biases. Undoubtedly, these high-quality RF FET models offer circuit designers an indispensable and powerful tool to best utilize our advanced RFCMOS technology.
We report on a study of asymmetric, traveling patterns which develop at a driven fluid-air interf... more We report on a study of asymmetric, traveling patterns which develop at a driven fluid-air interface in the experimental system known as the printer's instability. We find that the traveling pattern appears via a supercritical parity-breaking transition, at which the pattern loses its reflection symmetry and begins to drift with constant speed. From measurements of the degree of asymmetry of the drifting pattern as a function of the experimental control parameter, we find that the asymmetry increases with the square root of the control parameter, and that the drift velocity is linear in the asymmetry. This behavior is in accord with recent theoretical predictions. Our results do not agree, however, with the predictions of a model of the parity-breaking transition involving the coupling of spatial modes with wave numbers q and 2q.
2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2007
We describe the measurement and extraction of high-frequency compact model parameters of MOSFETs ... more We describe the measurement and extraction of high-frequency compact model parameters of MOSFETs for use in design of RF applications
... 2 , Hans van Meer 8 , Jewel Liang 1 , Martin Ostermayr 1 , Jenny Lian 1 , Muhsin Celik 4 , Ri... more ... 2 , Hans van Meer 8 , Jewel Liang 1 , Martin Ostermayr 1 , Jenny Lian 1 , Muhsin Celik 4 , Ricardo Donaton 3 , Kathy Barla 4 , MyungHee Na 3 , Yoshiro Goto 2 , Melanie Sherony 3 , Frank S. Johnson 8 , Richard Wachnik 3 , John Sudijono 6 , Ed Kaste 3 , Ron Sampson 4 , Ja ...
Transistor mismatch data and analysis from poly/ SiON and high-k/metal-gate (HKMG) bulk CMOS tech... more Transistor mismatch data and analysis from poly/ SiON and high-k/metal-gate (HKMG) bulk CMOS technologies are presented. It is found that the traditional mismatch figure of merit from the Pelgrom plot (A VT ) continuously scales down as technology advances. Furthermore, the A VT values for both nFET and pFET in the HKMG technology are significantly reduced from poly/SiON technologies. By normalizing the mismatch data against electrical oxide thickness (T INV ), threshold voltage (V TH ), and effective work function, a direct comparison of the mismatch data from various technologies is made. The differences in nFET and pFET mismatch behaviors in both poly/SiON and HKMG technologies are discussed in detail. Correlation between transistor V TH mismatch and flicker noise variation is observed in both poly/SiON and HKMG technologies. Finally, it is quantitatively demonstrated that effective work function variation does not generate significant V TH variability in the present HKMG technology. Index Terms-Bulk CMOS technology, effective work function, flicker noise variation, high-k/metal gate (HKMG), Pelgrom mismatch slope (A VT ), poly/SiON, random dopant fluctuation (RDF), Takeuchi normalization method, threshold voltage (V TH ) variability.
In this paper, we present an advanced RF modeling work for our state-of-the-art 45nm low-power CM... more In this paper, we present an advanced RF modeling work for our state-of-the-art 45nm low-power CMOS technology. Based on carefully designed structures, we extracted a rigorous, hardware-based wiring capacitance model that accurately computes each component of the wirecap network on top of the intrinsic FET. A novel, scalable substrate resistance model was created to well fit relevant hardware data. To obtain accurate on-wafer sparameter data for the modeling structures at high frequencies (up to 110GHz), we adopted sophisticated deembedding techniques such as Pad-Open-Short and COMPLETE. The results clearly show that our models well match various RF characteristics for devices with a broad range of sizes and measured at different voltage biases. Undoubtedly, these high-quality RF FET models offer circuit designers an indispensable and powerful tool to best utilize our advanced RFCMOS technology.
We report on a study of asymmetric, traveling patterns which develop at a driven fluid-air interf... more We report on a study of asymmetric, traveling patterns which develop at a driven fluid-air interface in the experimental system known as the printer's instability. We find that the traveling pattern appears via a supercritical parity-breaking transition, at which the pattern loses its reflection symmetry and begins to drift with constant speed. From measurements of the degree of asymmetry of the drifting pattern as a function of the experimental control parameter, we find that the asymmetry increases with the square root of the control parameter, and that the drift velocity is linear in the asymmetry. This behavior is in accord with recent theoretical predictions. Our results do not agree, however, with the predictions of a model of the parity-breaking transition involving the coupling of spatial modes with wave numbers q and 2q.
2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2007
We describe the measurement and extraction of high-frequency compact model parameters of MOSFETs ... more We describe the measurement and extraction of high-frequency compact model parameters of MOSFETs for use in design of RF applications
... 2 , Hans van Meer 8 , Jewel Liang 1 , Martin Ostermayr 1 , Jenny Lian 1 , Muhsin Celik 4 , Ri... more ... 2 , Hans van Meer 8 , Jewel Liang 1 , Martin Ostermayr 1 , Jenny Lian 1 , Muhsin Celik 4 , Ricardo Donaton 3 , Kathy Barla 4 , MyungHee Na 3 , Yoshiro Goto 2 , Melanie Sherony 3 , Frank S. Johnson 8 , Richard Wachnik 3 , John Sudijono 6 , Ed Kaste 3 , Ron Sampson 4 , Ja ...
Transistor mismatch data and analysis from poly/ SiON and high-k/metal-gate (HKMG) bulk CMOS tech... more Transistor mismatch data and analysis from poly/ SiON and high-k/metal-gate (HKMG) bulk CMOS technologies are presented. It is found that the traditional mismatch figure of merit from the Pelgrom plot (A VT ) continuously scales down as technology advances. Furthermore, the A VT values for both nFET and pFET in the HKMG technology are significantly reduced from poly/SiON technologies. By normalizing the mismatch data against electrical oxide thickness (T INV ), threshold voltage (V TH ), and effective work function, a direct comparison of the mismatch data from various technologies is made. The differences in nFET and pFET mismatch behaviors in both poly/SiON and HKMG technologies are discussed in detail. Correlation between transistor V TH mismatch and flicker noise variation is observed in both poly/SiON and HKMG technologies. Finally, it is quantitatively demonstrated that effective work function variation does not generate significant V TH variability in the present HKMG technology. Index Terms-Bulk CMOS technology, effective work function, flicker noise variation, high-k/metal gate (HKMG), Pelgrom mismatch slope (A VT ), poly/SiON, random dopant fluctuation (RDF), Takeuchi normalization method, threshold voltage (V TH ) variability.
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Papers by Li-Hong Pan