Systems and Control

The Dielectrophoretic (DEP) force arises as a result of the interaction between a nonuniform electric field and a neutrally charged particle. As the effect of the electric field is more dominant than other forces at the micro/nano scale, this force can be effectively used to manipulate and control particles on this scale. We consider the motion of a particle on an invariant line with the suspending medium being a fluid with low Reynolds number. The system is described by a set of ordinary differential equations with a quadratic term in the control variable (control being the applied voltage on the electrodes which induces the electric field) making the system non-affine. For this system, we address certain aspects of existence and uniqueness of the time-optimal trajectories.

A dielectrophoretic (DEP) force is a result of the interaction between a nonuniform electric field and a polarizable particle. As the electric field is dominant at the micro/nano scale, this force can be effectively used to manipulate and control particles on this scale. We consider the motion of a particle on an invariant line with the suspending medium being a fluid with a low Reynolds number. This DEP system has two states and two parameters: the two states are indicative of the particle's position and the induced dipole moment and the two parameters are α and c which depend upon the electric properties of the particle and the medium. The system is described by a set of ordinary differential equations with a quadratic term in the control variable (control being the applied voltage on the electrodes which induces the electric field) making the system non-affine in control. In the existing literature, the controllability studies of the DEP system have been restricted to reachability issues in the context of the time-optimal control problem. Here we present a comprehensive study of reachability, accessibility and controllability.

This article describes the design and development of INSPIRE-0, a payload on the spent stage of the ISROs PSLV. Recently, the Indian Space Research Organisation (ISRO) released an announcement of opportunity inviting proposals to develop payloads that can be tested on the PS4-Orbital Platform (PS4-OP). This platform is a novel idea formulated by ISRO to use the spent fourth/final stage of the Polar Satellite Launch Vehicle (PSLV), called the PS4, to conduct in-orbit scientific experiments and technology demonstration of small-satellite subsystems. INSPIRE-0 is a PS4-OP payload, jointly developed by the Laboratory for Atmospheric and Space Physics (LASP) at the University of Colorado Boulder, the Indian Institute of Space Science and Technology (IIST), and the Nanyang Technological University (NTU) in Singapore. This payload has two main objectives. Firstly, the scientific objective is to characterize the solar spectrum using a novel sensor, developed by NTU, that has a wide frequenc...

On-Board Computers (OBCs) for Small-satellite missions are typically required to be designed using industrial grade Commercial-of-the-shelf (COTS) components due to budget constraints and short mission duration. The OBC must provide a variety of interfaces due to the diverse nature of COTS subsystems having different interface definitions. Traditional OBC designs with standard microcontrollers have fixed interfaces that require modification of the motherboard circuit/layout when the external interfaces require changes. Thus, a possible solution is to have an FPGA in-addition to the micro-controller thereby providing a configurable interface capability. System-on-Chip (SoC) devices that integrate a microcontroller with FPGA fabric provide an ideal solution for reducing the development time. Additionally, the limited availability of power in small satellite missions makes it essential to use power-efficient devices. Furthermore, single event upsets (SEUs) and single event latch-up (SELs) are a major problem for OBCs designed for Low Earth Orbit (LEO) small-satellite missions. Flash memory-based FPGAs provide the benefit of low power consumption and they are more also fault-tolerant due to their intrinsic robustness against induced single event upsets compared to SRAM-based FPGAs. This article describes the OBC developed using the flash-based Microsemi SmartFusion2 SoC FPGA as its key component, for the INSPIRESat-1 and INSPIRESat-2 small-satellite missions. The OBC is designed in two form factors one with 13cm x 10cm dimensions for INSPIRESat-1 and the other with 10cm x 10cm dimensions for INSPIRESat-2. The OBC uses a COTS System-on-Module (SoM) developed by Emcraft containing the SmartFusion2 SoC, which is mounted on a custom-designed motherboard containing other peripherals including flash memory, SD Cards, and an external watchdog timer. The OBC has a total power consumption of approximately 1 W, in the final flight configuration. The article here describes the architecture of the OBC in detail, the key features of which include multiple on-board memories, a multi-level reset methodology, and reconfigurable input/output interfaces. The article concludes with the details of comprehensive performance tests conducted on the INSPIRESat-1 OBC, which has qualified TRL-8 (technology readiness level) status after completing required environmental tests such as the Thermal Vacuum Test (TVAC) and vibration test as a part of the integrated satellite. INSPIRESat-2 was launched in January 2021 and due to the successful working of the OBC in fight it has achieved TRL-9 status through this mission. The OBC developed for INSPIRESat-1 is planned to achieve TRL-9 status after its launch in the third quarter of 2021.