UNIVERSIDAD NACIONAL DE LOJA

Facultad de la Energía, las Industrias y los Recursos

Naturales No Renovables

INGENIERÍA EN COMPUTACIÓN

ARQUITECTURA DE ORDENADORES

INTEGRANTE: PABLO LÓPEZ

TEMA: REPLICA DE EJERCICOS

Ciclo: 3 “A”

2022

LOJA- ECUADOR
1. Ejercicio 1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity latch is
Port ( x, control : in STD_LOGIC;
z : out STD_LOGIC);
end latch;

architecture ejemplo of latch is

begin

z<=x when ( control='1');

end ejemplo;

Ilustración 1Descripción de un latch mediante una declaración

concurrente.

2. Ejercicio 2

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity latch1 is
Port ( dato, control : in STD_LOGIC;
salida : out STD_LOGIC);
end latch1;

architecture Ejemplo of latch1 is

process ( dato, control)

begin

if control='1' then
salida <= dato
end if
end process
end Ejemplo;
 Ilustración 2Creación de un latch dentro de un proceso.

3. Ejercicio 3

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ffd is
Port ( D, clk : in STD_LOGIC;
Q : out STD_LOGIC);
end ffd;

architecture arq_ffd of ffd is

begin
process (clk) begin
if (clk' event and clk='1') then
Q <= D;
end if;
end process;
end arq_ffd;

Ilustración 3Descripción de un Flip-Flop D disparado en transición de bajo a alto.

4. Ejercicio 4

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FLIP is
Port ( D , clk, RESET : in STD_LOGIC;
Q : out STD_LOGIC);
end FLIP;

architecture Behavioral of FLIP is

begin
process (clk,D,RESET) begin
if RESET='1' then
Q<= '0';
elsif (clk' event and clk ='1') then
Q <= D;
end if;
end process;

end Behavioral;

Ilustración 4Flip-Flop lipo D.

5. Ejercicio 5

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.std_arith.all;

entity FLIP1 is
Port ( clk, RESET, EN ,D : in STD_LOGIC;
Q : inout STD_LOGIC);
end FLIP1;

architecture FLOP of FLIP1 is

signal q_aux:std_logic; ·

begin
process (clk, RESET, EN)
begin
if reset='l' then q_ aux<='0'
elsif (clk' event and clk' l') then
if ( EN=' l' ) then
q_aux<= D;
else
q_aux<=q;
end if;
end if;
end process;
q<=q_aux;
end FLOP;
 Ilustración 5Flip-flop D con uso de señales

6. Ejercicio 6

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ffsr is
Port ( S,R,clk : in STD_LOGIC;
Q , Qn : inout STD_LOGIC);
end ffsr;

architecture a_ffsr of ffsr is

begin
process (clk, S, R)
begin
if (clk'event and clk 'l') then
if (S = 'O'and R = '1') then
Q <= '0';
Qn <= '1';
elsif (S = 'l' and R '0') then
Q <= '1' ;
Qn <= '0';
elsif (S = '0' and R '0') then
Q <= Q;
Qn <= Qn;
else
Q <= '-';
Qn <= '-';
end if;
end if;
end process;
end a_ffsr;
 Ilustración 6 Listado 3.3

7. Ejercicio 7

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity registro is
Port ( d, clk : in STD_LOGIC;
q : out STD_LOGIC);
end registro;

architecture serie of registro is

signal a,b: in std_logic;
begin
process (clk)
begin
if ( clk'event and clk='l' ) then
a<=d;
b<=a;
q<=d;
end if;
end serie;
 Ilustración 7 Registro serie

8. Ejercicio 8

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity registro2 is
Port ( d, clk : in STD_LOGIC;
q : out STD_LOGIC);
end registro2;

architecture serie2 of registro2 is

begin
process (clk);
variable a,b,: std_logic;
begin
if ( clk' event and clk='l' ) then
a<=d;
b<=a;
q<=d;
end if;
end process;
end serie2;

Ilustración 8 Uso Variables

9. Ejercicio 9

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity reg is
Port ( D : in STD_LOGIC_VECTOR(0 to 7);
clk : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(0 to 7));
end reg;

architecture arqreg of reg is

begin
process (clk) begin
if(clk' event and clk='1' ) then
Q <= D;
end if;
end process;
end arqreg;

Ilustración 9 Registro Paralelo

10. Ejercicio 10

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity reg4 is
Port ( D : in STD_LOGIC_VECTOR(3 downto 0);
clk, CLR : in STD_LOGIC;
Q, Qn : inout STD_LOGIC_VECTOR(3 downto 0));
end reg4;

architecture a_reg4 of reg4 is

begin
process (clk, CLR) begin
if(clk' event and clk = '1' ) the
if(CLR = '1') then
Q<=D;
Qn <= not Q;
else
Q<= "0000";
Qn<= "1111";
end if;
end if;
end process;
end a_reg4;
 Ilustración 10 Lista 3.4

11. Ejercicio 11

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity contador is
Port ( clk : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR(3 downto 0));
end contador;

architecture cuenta of contador is

begin
process (clk)
begin
if(clk' event and clk='1') then
q <= q+1;
end if;
end process;
end cuenta;

Ilustración 11 Contador binario de 4 bits

12. Ejercicio 12

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity contador2 is
Port ( clk : in STD_LOGIC;
Q : inout STD_LOGIC_VECTOR(3 downto 0));
attribute pin_numbers of contador: entity is
" clk:1 Q(3):14 Q(2):15 Q(1):16 Q(0): 17";
end contador2;

architecture pins of contador2 is

begin
process (clk)
begin
if(clk' event and clk='1') then
q <= q+1;
end if;
end process;
end pins;

Ilustración 12 Asignando pins

13. Ejercicio 13

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity contador3 is
Port ( clk, reset : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR(3 downto 0));
end contador3;

architecture modulo of contador3 is

begin
process (clk, reset)
begin
if(clk' event and clk='1') then
if(reset='1' or q="1001") then
q<="0000";
else
q<=q+1;
end if;
end if;
end process;
end modulo;

Ilustración 13 Contador binario

14. Ejercicio 14

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cont is
Port ( clk, reset : in STD_LOGIC;
Q : inout integer range 0 to 15);
end cont;

architecture arq_cont of cont is

begin
process(clk, reset)
begin
if(clk' event and clk='1')then
if(reset='1' or Q=9)then
Q<=0;
else
Q<=Q+1;
end if;
end if;
end process;
end arq_cont;

Ilustración 14 Contadores usando integer

15. Ejercicio 15
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity contador4 is
Port ( clk : in STD_LOGIC;
UP : in STD_LOGIC;
Q : inout STD_LOGIC_VECTOR(3 downto 0));
end contador4;

architecture a_contador of contador4 is

begin
process (UP, clk) begin
if(clk' event and clk ='1')then
if(UP = '0')then
Q<= Q+1;
else
Q<= Q-1;
end if;
end if;
end process;
end a_contador;

Ilustración 15 Contador Ascendente y Descendente

16. Ejercicio 16
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity contador5 is
Port ( clk, LD, UP : in STD_LOGIC;
D : in STD_LOGIC_VECTOR(2 downto 0);
Q : inout STD_LOGIC_VECTOR(2 downto 0));
end contador5;

architecture modulo of contador5 is

begin

process(clk, LD, D, UP)

begin
if(clk' event and clk='1') then
if(LD = '0') then
Q<=D;
elsif UP='1' THEN
Q<= Q+1;
else
Q<=Q-1;
end if;
end if;
end process;
end modulo;

Ilustración 16 Contador con carga en paralelo

17. Ejercicio 17

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cont1 is
Port ( P : in STD_LOGIC_VECTOR(3 downto 0);
clk, LOAD, ENP, RESET : in STD_LOGIC;
Q : inout STD_LOGIC_VECTOR(3 downto 0));
end cont1;

architecture arq_cont1 of cont1 is

begin
process(clk, RESET, LOAD, ENP) begin
if(RESET = '1') then
Q <= "0000";
elsif( clk' event and clk='1')then
if(LOAD = '0' and ENP = '-')then
Q <= P;
elsif( LOAD= '1' and ENP = '0') then
Q <= Q;
elsif (LOAD = '1' AND ENP = '1')then
Q <= Q + 1;
end if;
end if;
end process;
end arq_cont1;

Ilustración 17 Contador binario de 4 bits

18. Ejercicio 18

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ejemplogen is
Generic (contador_valor: integer:=511);
Port ( clk, ld, clr, en : in STD_LOGIC;
data : in integer range 0 to contador_valor;
Q : inout integer range 0 to contador_valor);

end ejemplogen;

architecture pins of ejemplogen is

signal contador_signal: integer range 0 to contador_valor;
begin
process(clk, en, ld, clr)
begin
if(clr= '0') then
contador_signal<=0;
elsif clk' event and clk='1' then
if en= '1' then
if ld='0' then
contador_signal <= data;
else
contador_signal<= data;
end if;
end if;
end if;
end process;
end pins;

Ilustración 18 Mega funciones a través de GENERIC

19. Ejercicio 19

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity diagrama is
Port ( clk, x : in STD_LOGIC;
z : out STD_LOGIC);
end diagrama;

architecture arq_diagrama of diagrama is

type estados is (d0, d1, d2, d3);
signal edo_presente, edo_futuro: estados;

begin
proceso1: process(edo_presente, x)begin
case edo_presente is
when d0 => z <='0';
if x='1' then
edo_futuro <=d1;
else
edo_futuro <=d0;
end if;
when d1 => z <='0';
if x='1' then
edo_futuro <=d2;
else
edo_futuro <=d1;
end if;
when d2 => z <='0';
if x='1' then
edo_futuro <=d3;
else
edo_futuro <=d0;
end if;
when d3 =>
if x='1' then
edo_futuro <=d0;
z<='1';
else
edo_futuro <=d3;
z<= '0';
end if;
end case;
end process proceso1;

proceso2: process(clk) begin

if(clk' event and clk='1')then
edo_presente <= edo_futuro;
end if;
end process proceso2;
end arq_diagrama;
Ilustración 19 Diseño de un diagrama de estados
20. Ejercicio 20

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity diag is
Port ( clk,x : in STD_LOGIC;
z : out STD_LOGIC);
end diag;

architecture arq_diag of diag is

type estados is (q0, q1, q2, q3, q4);
signal edo_pres, edo_fut: estados;
begin
proceso1: process (edo_pres,x) begin
case edo_pres is
when q0 => z <= '0';
if x='0' then
edo_fut <= q4;
else
edo_fut <= q1;
end if;
when q1 => z <= '0';
if x='0' then
edo_fut <= q4;
else
edo_fut <= q2;
end if;
when q2 =>
if x='0' then
edo_fut <= q4;
z<='0';
else
edo_fut <= q3;
z<='1';
end if;
when q3 => z <= '0';
if x='0' then
edo_fut <= q3;
else
edo_fut <= q3;
end if;
when q4 => z <= '0';
if x='0' then
edo_fut <= q4;
else
edo_fut <= q1;
end if;
end case;
end process proceso1;
proceso2: process (clk)begin
if(clk' event and clk='1')then
edo_pres <= edo_fut;
end if;
end process proceso2;
end arq_diag;
 Ilustración 20 Diagrama de estados

EJERCICIOS EN GITHUB: https://github.com/PabloLopez7/EjerciciosReplicas