Thome CMOSAIC Zurich April 2012 Lecture

3D Stacked Architectures with Interlayer Cooling - CMOSAIC
Prof. John R. Thome, LTCM-EPFL, Project Coordinator

Prof. Yusuf Leblebici, LSM-EPFL Prof. Dimos Poulikakos, LTNT-ETHZ Prof. Wendelin Stark, FML-ETHZ Prof. David Atienza Alonso, ESL-EPFL Dr. Bruno Michel, IBM Zrich Research Laboratory
CMOSAIC: Technological Aims

CMOSAIC aims to make an important contribution to the development of the first 3D computer chip with interlayer cooling for extremely high computational power with reduced power consumption. This is a very ambitious project that combines significant research efforts not only for the microchannel cooling but also for the micro-fabrication of such stacks with TSVs, interconnects, bonding, etc.
10 0000 0
10 0000
Wire Count
10 000
10 00
10 0 0 2 4 Wire Length (mm) 6 8
Two-Phase Cooling of 3D Stacked Microprocessors: 3D Test Vehicle

PhD student: Yassir Madhour
Fluid outlet Fluid inlet Cu TSV Si IC die
DRIE microchannels
Test vehicle
Flip-chip bonded (sequential) Force-controlled reflow process Total Force on chip: 12.6 [N] at 265C (2.2MPa) Force on individual joint: 0.6g
Cross section polished sample Contact area: 70% of initial plated surface
Individual joint after reflow
Two-Phase Cooling of 3D Stacked Microprocessors: 3D Test Vehicle

Electrical yield IBM: Thomas Brunschwiler, Ute Drechsler and Gerd Schlottig
24x48 50m bumps, pitch = 200m No shorted connection: 100% yield No sealing structures TC st. : reflow first, force then TC new: force first, reflow then After bonding: ramp reflow 260C + cooling down 4x no change in R
Mechanical testing initial shear testing
sample
Wafer-level TSV Process Compatible with Interlayer Cooling

Deep TSV Fabrication process
Histogram of the TSV resistance
PhD student: Michael Zervas
Ctsv
Ccoupling
Ctsv
TSV
Si
Cooling channel
Si
TSV coupling capacitance simulations in the presence of liquid channels.
Coupling capacitance [fF]
A deep TSV process, where the wafer thickness is greater than 50m, is needed to accommodate cooling channels with depth greater than 50m. Aspect ratio of the TSV is more than 1:6.
TSV coupling capacintace over the cooling liquid 70

liquid = 1 liquid = 3 liquid = 5 liquid = 7 liquid = 9 liquid = 11
60
50
40
30
20
10
0 80
4
100 120 140 160 180 200 TSV Distance [m] 220 240 260 280 300
Average TSV resistance below 1, with a peak at 13. Parasitic MOS capacitance Ctsv 0.8pF (Cu SiO2- Si) Parasitic coupling capacitance Ccoupling over the dielectric cooling liquid up to 60fF
TSV
CMOS-Compatible Chip-to-Chip Integration

Chip-level 3D integration platform based on wafer reconstitution, bonding, and TSV fabrication
PhD student: Yuksel Temiz

Microprocessor post-CMOS processing and stacking Top chip thinning and etching Bottom chip passivation and redistribution layer patterning Bonding and TSV fabrication
Bottom Chip
Two 50m thick chips are bonded and electrically connected by Cu TSVs. Daisy-chain measurements demonstrate 0.5 resistance with 99% yield for 1280 TSVs.
Top Chip
2D Flow Boiling Tests for Characterizing 3D-ICs

Ph.D.: Sylwia Szczukiewicz With and Without Micro-Orifices
Flow direction
High-speed visualization of the two-phase flow boiling of R245fa without any inlet restrictions (top), and with the 50 m-wide, 100 m-deep, and 100 m-long inlet micro-orifices (bottom). Gch=2035 kg/m2s and qb=36.5 W/cm2. The flow is from left to right. Recorded @2000fps. Slow motion @30fps.
2D Flow Boiling Tests for Characterizing 3D-ICs

Ph.D.: Sylwia Szczukiewicz
Video
Heat Transfer: Uniform Heat Flux Boundary Condition

10 8
y [mm]
In Out
49 48 47
IR View
6 4 2 2 4 6 8 10
46 45 44 43
z [mm]
Footprint temperature maps of the test sections base provided IR camera for two-phase flow boiling of R236fa for Gch=2299 kg/m2s, qb=48.6 W/cm2 calculated with one-dimensional conduction (left-hand side) and local width-avg. heat transfer coefficients from inlet to outlet (right-hand side).
600000 temperature pixels per second using inhouse IR camera calibration.
3D ALE-FEM for Microscale Two Phase Flows

Ph.D.: Gustavo Rabello dos Anjos
su r f ace
standard approach
surf ace
Lagrangian approach
Development: [1] Comparison of surface representations; [2] Arbitrary Lagrangian-Eulerian Technique; [3] Test case: 3D microchannel
[1]
Goals: 3D Arbitrary Lagrangian-Eulerian Finite Element code; Coupled heat transfer and two-phase flow Predict flows in microscale complex geometries;
[2]
mesh velocity
surface tension gravity
Lagrangian Eulerian
[3]
cross section d d
Integrated Water Cooled 3D Electronic Chips - Experiments PhD student: Adrian Renfer
High frequency flow fluctuations
a) Single cavity out of a 3D chip stack
Visualization of flow vortices

Top view of the cooling structure
flow
b) Dynamic pressure measurements Pressure fluctuation inside chip
time c) Frequency analysis FFT spectra at different flow rates Increasing vortex shedding frequency
FFT spectra
Benefits of enhanced flow fluctuations for liquid cooling

Higher heat transfer and better hot-spot cooling
Planned: measure and evaluate

Increasing flow rate Impact on cooling performance in 3D chips Detailed heat transfer study including fluid temperature maps
Renfer et al., Vortex shedding from confined micropin fin arrays, Microfluidics and Nanofluidics , to be submitted (2012)
frequency (kHz)
Publications
Integrated Water Cooled 3D Electronic Chips - Modeling PhD student: Fabio Alfieri
We investigate next generation interlayer integrated water cooled 3D chips
a) Cooling cavities with microstructures are approximated as ultrathin porous medium c) Our modeling results show good agreement with the experimental data in different layers
Temperature difference
x*
x Lchip
b) We specifically account for hydrothermal entrance region
d) Pin-fin structures are better at cooling than microchannels
Undergoing investigation
Hydrodynamic entrance length
Heat transfer enhancement induced by vortex shedding

Pclet number 3
Impact on the performance of non-homogeneous micro pin-fin density and heat fluxes
4
Pe RePr
Publications
Alfieri et al., On the Significance of Developing Boundary Layers in Integrated Water Cooled 3D Chip Stacks, International Journal of Heat and Mass Transfer, accepted for publication (2012)
A Faster 3D-ICE for a Faster Processor

Find us at http://esl.epfl.ch/3D-ICE
Ph.D.: Arvind Sridhar
Since we released the first transient thermal simulator for liquidcooled ICs, 3D-ICE has seen >100 downloads and >40 citations from all over the world in one year!!!
Now we have made it even faster! 100X Faster!
Parallelize 3D-ICE using Neural
Networks
Run it on Graphics
Processors
Sridhar et al. Neural Network-based thermal simulation of ICs on GPUs, IEEE TCAD 2011
Demo: Simulation of IC Temperatures
Ph.D.: Arvind Sridhar

Simulated using 3D-ICE for 400ms
Heat Dissipation pattern changes every 100ms
Test case: 2 dies containing Sun Niagara Multicore processors stacked in a liquid-cooled 3D IC
Heat Dissipation Map

Darker More Heat
Coolant Flow
Temperature Map
Red Higher Temperature
Hierarchical Thermal Management of Liquid Cooled 3D-MPSoCs

Run-time Thermal Management Objectives
Minimize the energy consumption Maintain thermal and performance constraints
PhD student: Mohamed M. Sabry
Clear Benefits of Hierarchical Thermal Control

Centralized Liquid flow controller (slow) Distributed Processing controllers (fast) Periodic interaction Results 60% less pumping energy, and 25% energy savings (with respect to worst case estimate) Thermal violation 0% (Tmax<85C) Thermal variation <10C Performance loss <2%
Processing controllers
Core 0 Core 1 Core 3 Core 5 Core 2 Core 4
Liquid flow controller
Zanini, Sabry et al. Hierarchical Thermal Management Policy for High-Performance 3D Systems with Liquid Cooling, IEEE JETCAS 2011
Superhydrophobic surfaces
Ph.D. Student: Michael Rossier
Goals Production of a highly hydrophobic surface to reduce the pressure drop in microchannel with application for water cooling systems
Crater-like silicon etching
Approach
3
(1) Creation of a nanostructure4(silicon etching) (2) Surface modification of the created structure (fluorosiloxane)
Contact angle measurement of a water droplet on functionalized crater-like silicon structures: contact angle: 155
3D Test Vehicle Fabrication Schedule

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3D Stacked Architectures with Interlayer Cooling - CMOSAIC

Prof. John R. Thome, LTCM-EPFL, Project Coordinator

CMOSAIC: Technological Aims

10 0 0 2 4 Wire Length (mm) 6 8

Two-Phase Cooling of 3D Stacked Microprocessors: 3D Test Vehicle

Individual joint after reflow

Two-Phase Cooling of 3D Stacked Microprocessors: 3D Test Vehicle

Mechanical testing initial shear testing

Wafer-level TSV Process Compatible with Interlayer Cooling

PhD student: Michael Zervas

TSV coupling capacitance simulations in the presence of liquid channels.

Coupling capacitance [fF]

TSV coupling capacintace over the cooling liquid 70

CMOS-Compatible Chip-to-Chip Integration

PhD student: Yuksel Temiz

2D Flow Boiling Tests for Characterizing 3D-ICs

2D Flow Boiling Tests for Characterizing 3D-ICs

Heat Transfer: Uniform Heat Flux Boundary Condition

3D ALE-FEM for Microscale Two Phase Flows

surface tension gravity

Visualization of flow vortices

b) Dynamic pressure measurements Pressure fluctuation inside chip

Benefits of enhanced flow fluctuations for liquid cooling

Planned: measure and evaluate

b) We specifically account for hydrothermal entrance region

d) Pin-fin structures are better at cooling than microchannels

Heat transfer enhancement induced by vortex shedding

A Faster 3D-ICE for a Faster Processor

Ph.D.: Arvind Sridhar

Now we have made it even faster! 100X Faster!

Parallelize 3D-ICE using Neural

Demo: Simulation of IC Temperatures

Ph.D.: Arvind Sridhar

Heat Dissipation Map

Hierarchical Thermal Management of Liquid Cooled 3D-MPSoCs

PhD student: Mohamed M. Sabry

Clear Benefits of Hierarchical Thermal Control

Liquid flow controller

Crater-like silicon etching

3D Test Vehicle Fabrication Schedule

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