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Interfacing Peripherals (I/O) and
Applications Interrupt: • Interrupt is a process where an external device can get the attention of the microprocessor.
• The process is asynchronous, means can occur at any time during execution of program.
• In order to communicate with μP & I/O devices Interrupt method is used.
• An interrupt is considered to be an emergency signal. The Microprocessor should respond to it as
soon as possible.
• Interrupt is signal send by an external device to the microprocessor to request the processor to perform a particular task or work.
• It is a simple routine program that keeps a check for the occurrence of the interrupt.
• If the μP accept the interrupt and send the INTA (active low) signal to the peripheral.
• When interrupt is received, μP suspends its current activity and upon completion, it resumes the suspended activity.
• The processor executes an interrupt service routine (ISR) addressed in program counter.
• It returned to main program by RET instruction.
Software Interrupt • That means programmer can use this instruction to execute interrupt in main program.
• There are eight software interrupt available in μP that are RST0 to RST7.
• The vector address for these interrupts can be calculate as Interrupt number * 8 = vector address.
• These instruction allow transfer of program control from the main program to predefined service routine is also referred to as ISR. Hardware Interrupt This interrupt is caused by sending a signal on one of the interrupt pins of the microprocessor.
An external device initiates the hardware interrupts and placing an appropriate
signal at the interrupt pin of the processor.
If the interrupt is accepted, then the process or executes an interrupt service
routine (ISR).
The 8085 has five hardware interrupts (1)TRAP (2)RST7.5 (3)RST6.5 (4)RST5.5 (5)INTR (address is supplied externally) The hardware interrupts are classified Two types– Maskable Interrupts (Can be delayed or Rejected) : An interrupt which can be disabled by software that means we can disable the interrupt by sending appropriate instruction, is called a maskable interrupt. RST 7.5, RST 6.5, RST 5.5 , INTR are the example of Maskable Interrupt.
Non-Maskable Interrupts (Can not be delayed or Rejected):
Cannot disable the interrupt by sending any instruction is called Non Maskable Interrupt. TRAP interrupt is the non-maskable interrupt for 8085. It means that if an interrupt comes via TRAP, 8085 will have to recognize the interrupt we cannot mask it. Interrupts can also be classified into: Vectored (address of the service routine is hard-wired): In vectored interrupts, the processor automatically branches to the specific address in response to an interrupt. In vectored interrupts, the manufacturer fixes the address of the ISR to which the program control is to be transferred. The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts.
Non-Vectored (address of the service routine needs to be supplied externally by the device): In non-vectored interrupts the interrupted device should give the address of the interrupt service routine(ISR). The INTR is a non-vectored interrupt. Hence when a device interrupts through INTR, it has to supply the address of ISR after receiving interrupt acknowledge signal.
• When a device interrupts, it actually wants the MP to give a service which is equivalent to asking the MP to call a subroutine. This subroutine is called ISR (Interrupt Service Routine). • This interrupts can be enable and disable by using EI (enable interrupt) & DI (disable interrupt) instructions. • The ‘EI’ instruction is a one-byte instruction and is used to Enable interrupts. • The ‘DI’ instruction is a one-byte instruction and is used to Disable interrupts. TRAP
This interrupt is a Non-Maskable interrupt.
It is unaffected by any mask or interrupt enable. TRAP is the highest priority and vectored interrupt (as vector address is fixed i.e. memory location where to transfer control). TRAP interrupt is edge and level triggered. This means that the TRAP must go high and remain high until it SIM (Set Interrupt Mask) for • Interrupt 8085 provide the additional masking facility for RST 7.5, RST 6.5 and RST 5.5 using SIM instruction.
• The status of these interrupts can be read by executing RIM instruction.
• The masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can be performed by moving an 8-bit data to accumulator and then executing SIM instruction.
• The format of the 8 bit data is shown below
Example RIM (Read Interrupt Mask) for Interrupt The status of pending interrupts can be read from accumulator after executing RIM instruction.
When RIM instruction is executed an 8-bit data is loaded in accumulator, which can be interpreted as shown in fig. Practice problem
If the 8085 microprocessor is interrupted while executing a 3-byte instruction (assuming the interrupt is enabled), the processor will acknowledge the interrupt request immediately, even before the completion of the instruction.
b. When an 8085 system is Reset, all the interrupts including the TRAP are disabled.
