Addressing Modes in 8085

These are the instructions used to transfer the data from one register to another register, from the
memory to the register, and from the register to the memory without any alteration in the content.
Addressing modes in 8085 is classified into 5 groups −

1. Immediate addressing mode

In this mode, the 8/16-bit data is specified in the instruction itself as one of its operands.
For example: MVI K, 20F: means 20F is copied into register K.

2. Register addressing mode

In this mode, the data is copied from one register to another.
For example: MOV K, B: means data in register B is copied to register K.

3. Direct addressing mode

In this mode, the data is directly copied from the given address to the register.
For example: LDB 5000K: means the data at address 5000K is copied to register B.

4. Indirect addressing mode

In this mode, the data is transferred from one register to another by using the address pointed by
the register.
For example: MOV K, B: means data is transferred from the memory address pointed by the
register to the register K.

5. Implied addressing mode

This mode doesn’t require any operand; the data is specified by the opcode itself.
For example: CMP.

Interrupts in 8085
Interrupts are the signals generated by the external devices to request the microprocessor to
perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
Interrupt are classified into following groups based on their parameter –

Types of Interrupts
1. Vector interrupt − In this type of interrupt, the interrupt address is known to the processor.
For example: RST7.5, RST6.5, RST5.5, TRAP.
Vectored interrupts are those interrupts whose service routine address is known to be a
processor. So, once a vectored interrupt is generated then the processor automatically
suspends its main program and switches to the vector location.

2. Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to the
processor so, the interrupt address needs to be sent externally by the device to perform
interrupts. For example: INTR.
3. Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing
some instructions into the program. For example: RST7.5, RST6.5, RST5.5.
4. Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt by
writing some instructions into the program. For example: TRAP.
5. Software interrupt − In this type of interrupt, the programmer has to add the instructions
into the program to execute the interrupt. There are 8 software interrupts in 8085, i.e. RST0,
RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
Sometimes the execution of an instruction generates interrupt in the microprocessor. So, in
case of the internally generated interrupt, the processor suspends the current execution and
switches to handle the interrupt. But once the ISR is executed the processor returns to the
main program.
There is total 8 software interrupts present in 8085 i.e., from RST 0 to RST 7:
Basically, whenever a software interrupt is generated then its vector address is calculated
by:
Vector Address = Interrupt number × 8
Suppose we have to calculate vector address of RST 4 then, it will be
4 × 8 = 32 = 20H
Thus, 0020H will be the vector address of RST 4

INTERRUPT VECTOR ADDRESS

RST 0 00 H

RST 1 08 H

RST 2 10 H

RST 3 18 H

RST 4 20 H

RST 5 28 H
 RST 6 30 H

RST 7 38 H

Figure: Interrupt priority

Hardware interrupt –
There are 5 interrupt pins in 8085 used as hardware interrupts, i.e. TRAP, RST7.5, RST6.5,
RST5.5, INTA.
These interrupts are basically associated with peripheral devices generated at the time of data
transfer between I/O device and microprocessor. An external device generates interrupt by placing
an interrupt signal over the pins of the microprocessor.
The 8085 microprocessor holds some pin, which gets enabled whenever the peripheral devices
interrupt the main program for an I/O operation.

Out of the 5 hardware interrupts, only INTR is a non-vectored interrupt rest other are vectored
interrupt. While the INTR is non-vectored interrupt that means the processor is unknown about
the memory location from where the interrupt is generated and is needed to be serviced. So, in
such a case the interrupt generating device sends the address of the location where the interrupt is
to be serviced.

INTA is not an interrupt; it is used by the microprocessor for sending acknowledgement. TRAP
has the highest priority, then RST7.5 and so on.
The different hardware interrupts:

TRAP:
TRAP is the highest priority interrupt and is non-maskable in nature. As this interrupt is non-
maskable thus cannot be masked (i.e., rejected or delayed) under software control by the processor.
This interrupt is edge and level triggered. Thus, the signal at this pin must be high and remain
enabled until it is acknowledged by the processor.

Due to non-maskable nature, a TRAP signal at the pin can be cleared only in two ways:

● The first is resetting of the processor by providing a low signal at the RESET pin.
● The second is acknowledging the high TRAP signal.

So, basically whenever a high signal is received at the TRAP pin of 8085 then the processor
generates an acknowledging signal by clearing the flip flops. So, after this interrupt is
acknowledged then the processor stores the return address of the program in current execution in
the stack. Also at the same time, the Program counter is loaded with the fixed vectored address of
the TRAP interrupt in order to execute the ISR operation.

By default, it is enabled until it gets acknowledged. In case of failure, it executes as ISR and sends
the data to backup memory. This interrupt transfers the control to the location 0024H.
A non-maskable interrupt is a Trap Interrupt which implies that whenever this pin gets activated,
the 8085 always gets interrupted even if the state of 8085 is in DI. The input of Trap input is level
sensitive and edge sensitive. Hence the Trap line always makes a transition from 0 to 1, and
remains in state 1 until the end of the execution of an instruction for the interruption of 8085.
A vectored-interrupt in 8085 is a TRAP. The starting address of 8085 is known by itself the of
the ISS as 4.5 * 8 = 0024H. Non-maskable interrupt is TRAP whereas maskable is interrupt. At
location 4.5 * 8, we do not have the ISS. As an example, in the ALS kit we have instruction JMP
0182H in the 3 bytes starting at 4.5 * 8 = 0024H.

RST 7.5:
This interrupt holds the second-highest priority among these interrupts and is maskable in nature.
If the mask bit of the interrupt is low, then this shows that the processor is not masking the
interrupt. So further the processor loads the address of the current operation in the stack and loads
the vector address of RST 7.5 i.e., 003CH onto the PC. Thus, 8085 starts executing the instruction
in the memory location in order to service the routine.

RST 6.5 and RST 5.5:

These two are level-triggered interrupts and can be masked by the processor. The RST 6.5 and
RST 5.5 holds a third and fourth level of priority respectively. Like the above-discussed interrupts,
whenever these two interrupts are generated then the processor loads the PC with the respective
vector address after suspending the current execution.
INTR:
It is maskable interrupt but we have already discussed that it is a non-vectored interrupt. And so,
whenever an INTR signal is received by the processor then the acknowledgement INTA is sent by
the processor to the requesting device by which it asks for the address for the interrupt service
routine. Once the external device provides the address of ISR to the processor then it loads the
address in stack after it suspends the main program. Among all the hardware interrupts, INTR is
the lowest priority interrupt.
When INTR signal goes high, the following events can occur −
● The microprocessor checks the status of INTR signal during the execution of each
instruction.
● When the INTR signal is high, then the microprocessor completes its current instruction
and sends active low interrupt acknowledge signal.
● When instructions are received, then the microprocessor saves the address of the next
instruction on stack and executes the received instruction.

Interrupts are the signals that are generally produced by the devices externally connected to the
microprocessor, requesting for the services. Whenever an interrupt request is generated in the
system then it must not be neglected and be acknowledged as soon as possible.

Basically, whenever an interrupt is generated then the microprocessor suspends its current
execution and switches to service the interrupt that is requested by the external device. In order to
service the interrupt, the processor executes a routine which is called the interrupt service routine.
So, after the execution of interrupt service routine (ISR) the processor, resumes the original
program that was under operation before the generation of the interrupt. Sometimes some special
instructions inside the processor generate interrupts. Those are handled by the processor internally.

Suppose the processor is executing an instruction and a keyboard key is pressed. Then at this time,
the processor gets to know that the external device keyword is requesting its services.

So, if the processor checks for the priority of the generated interrupt and if the generated interrupt
holds high priority, then the processor switches to execute the ISR by storing the address of the
current program in the stack. This is done so that after the execution of ISR, the processor can
switch back to the main program.

NMI :
It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt
request pin (INTR)and it is of type 2 interrupt.
When this interrupt is activated, these actions take place −
Completes the current instruction that is in progress.
Pushes the Flag register values on to the stack.
Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on to
the stack.
IP is loaded from the contents of the word location 00008H.
CS is loaded from the contents of the next word location 0000AH.
Interrupt flag and trap flag are reset to 0.

Instruction for Interrupts –

1. Enable Interrupt (EI) – The interrupt enable flip-flop is set and all interrupts are
enabled following the execution of next instruction followed by EI. No flags are
affected. After a system reset, the interrupt enable flip-flop is reset, thus disabling the
interrupts. This instruction is necessary to enable the interrupts again (except TRAP).
2. Disable Interrupt (DI) – This instruction is used to reset the value of enable flip-flop
hence disabling all the interrupts. No flags are affected by this instruction.
3. Set Interrupt Mask (SIM) – It is used to implement the hardware interrupts (RST 7.5,
RST 6.5, RST 5.5) by setting various bits to form masks or generate output data via the
Serial Output Data (SOD) line. First the required value is loaded in accumulator then
SIM will take the bit pattern from it.

4. Read Interrupt Mask (RIM) – This instruction is used to read the status of the
hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by loading into the A register a byte
which defines the condition of the mask bits for the interrupts. It also reads the
condition of SID (Serial Input Data) bit on the microprocessor.
Interrupt Service Routine (ISR)
A small program or a routine that when executed, services the corresponding
interrupting source is called an ISR.

Interrupt Structure of 8085 Microprocessor

Polling
Initially, there was an approach called polling used in the microprocessor.

In polling or polled approach, the software inside the microprocessor checks each peripheral
device according to the priority that whether any one of them needs the processor services.

In polling, a program inside the processor checks the I/O ports A, B and C for the need of service.
As we have already said that the ports are sequentially checked on the basis of priority. So, one
after the other each of the peripheral devices are checked. But the priority assigned to each of the
I/O devices can be changed and thus the polling routine.

However, this will lead to unnecessary processor utilization when no external request for the
processor is generated. Thereby causing a great reduction in the overall throughput of the system.
So, to have an efficient system, another desirable technique was taken into consideration by which
whenever a device needs service of the processor, then it will send a signal to it in order to request
for its services. These signals are nothing but the interrupts.