SYSTEM SOFTWARE

TCS 501
UNIT I INTRODUCTION

UNIT II ASSEMBLERS

UNIT III LOADERS AND LINKERS

UNIT IV MACRO PROCESSORS

UNIT V SYSTEM SOFTWARE TOOLS

INTRODUCTION
 System software and machine
architecture
 The Simplified Instructional Computer
(SIC)
 Machine architecture
 Data and instruction formats
 Addressing modes
 Instruction sets
 I/O and programming
 SYSTEM SOFTWARE
 The subject introduces the design and
implementation of system software
 System software consists of a variety of
programs that support the operation of a
computer
 Operating system, compiler, assembler,
macro processor, loader or linker,
debugger, text editor, database management
systems, software engineering tools, ….
 SOFTWARE ITS CLASSIFICATION
 Software is a set of instructions or
programs written to carry out specific
tasks on digital computers
 Classified into system software and
application software
 System software consists of a variety of
programs that support the operation of a
computer
 Application software focuses on an
application or problem to be solved
THIS CHAPTER GIVES YOU…

 System Software & Machine

Architecture
 The Simplified Instructional Computer
SIC and SIC/XE
 Traditional (CISC) Machines
 Complex Instruction Set Computers
 RISC Machines
 Reduced Instruction Set Computers
 SYSTEM SOFTWARE & MACHINE
ARCHITECTURE

Machine Dependent
Machine Independent
MACHINE INDEPENDENT

There are aspects of system software

that do not directly depend upon the
type of computing system
general design and logic of an
assembler
general design and logic of a compiler
code optimization techniques
MACHINE DEPENDENT

System software – support operation

and use of computer
Application software - solution to a
problem
Assembler translates mnemonic
instructions into machine code
Compilers must generate machine
language code
THE SIMPLIFIED INSTRUCTIONAL
COMPUTER (SIC)
 SIC is a hypothetical computer that
includes the hardware features most often
found on real machines
 Two versions of SIC
standard model (SIC)
extension version (SIC/XE)
(extra equipment or extra expensive)
SIC MACHINE ARCHITECTURE
Memory and Registers
Data Formats
Instruction Formats
Addressing Modes
Instruction Set
Input and Output
MEMORY

◦ 2 15 bytes in the computer memory

◦ 32,768 bytes
◦ Uses Little Endian
◦ 3 consecutive bytes form a word
◦ 8-bit bytes
Registers - Five registers each 24 bits in
length (3 bytes)

Mnemonic Number Use

A 0 Accumulator; used for arithmetic o
X 1 Index register; used for addressing
L 2 Linkage register; JSUB
PC 8 Program counter
SW 9 Status word, including CC
Mnemonic Number Use
A 0 Accumulator; used for arithmetic operations
X 1 Index register; used for addressing
L 2 Linkage register; JSUB
PC 8 Program counter
SW 9 Status word, including CC
Mnemonic Number Use
A 0 Accumulator; used for arithmetic operations
X 1 Index register; used for addressing
L 2 Linkage register; JSUB
PC 8 Program counter
SW 9 Status word, including CC
DATA FORMATS

◦ Integers are stored as 24-bit binary

numbers
◦ 2’s complement representation is used
for negative values
◦ No floating-point hardware
 INSTRUCTION FORMATS

opcode (8) x address (15)

Mode IndicationTarget address calculation

Direct x=0 TA=address
Indexed x=1 TA=address+(X)
 opcode (8) x address (15)

Mode Indication Target address calculation

Direct x=0 TA=address
Indexedx=1 TA=address+(X)
 INSTRUCTION SET

◦ load and store:

◦ LDA, LDX, STA, STX, etc.
◦ integer arithmetic operations:
◦ ADD, SUB, MUL, DIV, etc.
 All arithmetic operations involve
register A and a word in memory, with
the result being left in the register
INSTRUCTION SET

◦ comparison:
 COMP - compares the value in
register A with a word in memory,
this instruction sets a condition code
CC to indicate the result
INSTRUCTION SET

◦ Conditional jump instructions:

◦ JLT, JEQ, JGT
 These instructions test the setting of
CC and jump accordingly
INSTRUCTION SET

◦ subroutine linkage: JSUB, RSUB

 JSUB jumps to the subroutine, placing
the return address in register L
 RSUB returns by jumping to the
address contained in register L
INPUT AND OUTPUT

◦ Input and Output are performed by

transferring 1 byte at a time to or from
the rightmost 8 bits of register A
(accumulator)
◦ The Test Device (TD) instruction tests
whether the addressed device is ready to
send or receive a byte of data
◦ Read Data (RD), Write Data (WD)
DATA MOVEMENT
3-byte word:
◦ LDA, STA, LDL, STL, LDX, STX
◦ A- Accumulator, L – Linkage
Register, X – Index Register
1-byte: LDCH, STCH
No memory-memory move instruction
STORAGE DEFINITION

◦ WORD - ONE-WORD CONSTANT

◦ RESW - ONE-WORD VARIABLE
◦ BYTE - ONE-BYTE CONSTANT
◦ RESB - ONE-BYTE VARIABLE
EXAMPLE PROGRAMS (SIC)
BYTE0 BYTE1 BYTE2
ALPH
A
BYTE0 BYTE1 BYTE2
FIVE 00 00 05

BYTE0
CHARZ 5A Hexadecimal 0f Z

BYTE0
C1
EXAMPLE PROGRAMS (SIC)
BYTE0 BYTE1 BYTE2
ALPH
A
BYTE0 BYTE1 BYTE2
FIVE 00 00 05

BYTE0
CHARZ 5A Hexadecimal 0f Z

BYTE0
C1

BYTE0 BYTE1 BYTE2

A 00 00 05
EXAMPLE PROGRAMS (SIC)
BYTE0 BYTE1 BYTE2
ALPH 00 00 05
A
BYTE0 BYTE1 BYTE2
FIVE 00 00 05

BYTE0
CHARZ 5A Hexadecimal 0f Z

BYTE0
C1

BYTE0 BYTE1 BYTE2

A 00 00 05
EXAMPLE PROGRAMS (SIC)
BYTE0 BYTE1 BYTE2
ALPH 00 00 05
A
BYTE0 BYTE1 BYTE2
FIVE 00 00 05

BYTE0
CHARZ 5A Hexadecimal 0f Z

BYTE0
C1

BYTE0 BYTE1 BYTE2

A XX XX 5A
EXAMPLE PROGRAMS (SIC)
BYTE0 BYTE1 BYTE2
ALPH 00 00 05
A
BYTE0 BYTE1 BYTE2
FIVE 00 00 05

BYTE0
CHARZ 5A Hexadecimal 0f Z

BYTE0
C1 5A

BYTE0 BYTE1 BYTE2

A XX XX 5A
ADD M 18
AND M 40
COMP M 28
DIV M 24
J M 3C
JEQ M 30
JGT M 34
JLT M 38
JSUB M 48
LDA M 00
LDCH M 50
LDL M 08
LDX M 04
MUL M 20
OR M 44
RD M D8
RSUB 4C
STA M 0C
STCH M 54
STL M 14
STX M 10
SUB M 1C
TD M E0
TIX M 2C
EXAMPLE PROGRAMS (SIC) Example 2
Label Mnemoni Operand
cs
1000 LDX ZERO
1001 MOVECH LDCH STR1, X

1002 STCH STR2, X

1003 TIX ELEVEN
1004 JLT MOVECH
- - -
- - -
1010 STR1 BYTE C TEST
STRING
1011 STR2 RESB 11
1012 ZERO WORD 0

1014 ELEVEN WORD 11

- - - -
EXAMPLE PROGRAMS (SIC) Example 2
Label Mnemoni Operand
cs
1000 LDX ZERO
1001 MOVECH LDCH STR1, X
0101 0000 1 001 0000 0001 0000
1002 STCH STR2, X
1003 TIX ELEVEN
1004 JLT MOVECH
- - -
- - -
1010 STR1 BYTE C TEST
STRING
1011 STR2 RESB 11
1012 ZERO WORD 0

1014 ELEVEN WORD 11

- - - -
EXAMPLE PROGRAMS (SIC) Example 2
Label Mnemoni Operand
cs
1000 LDX ZERO
1001 MOVECH LDCH STR1, X
0101 0000 1 001 0000 0001 0000
1002 STCH STR2, X
0101 0100 1 001 0000 0001 0001
1003 TIX ELEVEN
1004 JLT MOVECH
- - -
- - -
1010 STR1 BYTE C TEST
STRING
1011 STR2 RESB 11
1012 ZERO WORD 0

1014 ELEVEN WORD 11

- - - -
EXAMPLE PROGRAMS (SIC) Example 2
Label Mnemoni Operand
cs
1000 LDX ZERO
1001 MOVECH LDCH STR1, X 0101 0000 1 001 0000 0001 0000

1002 STCH STR2, X

0101 0100 1 001 0000 0001 0001

1003 TIX ELEVEN

0100 0100 0 001 0000 0001 0100
1004 JLT MOVECH
- - -
- - -
1010 STR1 BYTE C TEST
STRING
1011 STR2 RESB 11
1012 ZERO WORD 0

1014 ELEVEN WORD 11

- - - -
EXAMPLE PROGRAMS (SIC) Example 2
Label Mnemoni Operand
cs
1000 LDX ZERO
1001 MOVECH LDCH STR1, X 0101 0000 1 001 0000 0001 0000

1002 STCH STR2, X

0101 0100 1 001 0000 0001 0001

1003 TIX ELEVEN

0100 0100 0 001 0000 0001 0100
1004 JLT MOVECH
0011 1000 0 001 0000 0000 0001
- - -
- - -
1010 STR1 BYTE C TEST
STRING
1011 STR2 RESB 11
1012 ZERO WORD 0

1014 ELEVEN WORD 11

- - - -
EXAMPLE PROGRAMS (SIC) Example 2
T E S T S T R I N G

Label Mnemon Operand STR1 54 45 53 54 20 53 54 52 49 4E 47

ics
LDX ZERO
MOVECH LDCH STR1, X 0 1 2 3 4 5 6 7 8 9 10

STCH STR2, X STR2

TIX ELEVEN
JLT MOVECH 0 1 2 MEMORY ZERO
- - ZERO 00 00 00
- -
0 1 2 MEMORY- ELEVEN
STR1 BYTE C TEST ELEVEN 00 00 0B
STRING
STR2 RESB 11
ZERO WORD 0
ELEVEN WORD 11
 0 1 2 3 4 5 6 7 8 9 10
T E S T S T R I N G
STR1 54 45 53 54 20 53 54 52 49 4E 47

0 1 2 3 4 5 6 7 8 9 10

STR2

0 1 2
ELEVEN
ELEVEN- MEMORY
00 00 0B

0 1 2 ZERO- MEMORY
ZERO 00 00 00

0 1 2
Load in Index register of content ZERO
X 00 00 00
 0 1 2 3 4 5 6 7 8 9 10
T E S T S T R I N G
STR1 54 45 53 54 20 53 54 52 49 4E 47

0 1 2 3 4 5 6 7 8 9 10

STR2

0 1 2 0 1 2
ELEVEN 00 00 0B ZERO 00 00 00
ZERO- MEMORY
ELEVEN- MEMORY
0 1 2
X 00 00 00

LOAD the CHARACTER in ACCUMULATOR

FROM STR1 (place) by performing indexed
addressing mode.

Loaded (STR1(0)+X)=54

0 1 2
A 00 00 54
 0 1 2 3 4 5 6 7 8 9 10
T E S T S T R I N G
STR1 54 45 53 54 20 53 54 52 49 4E 47

0 1 2 3 4 5 6 7 8 9 10

STR2 54

0 1 2 0 1 2
ELEVEN 00 00 0B ZERO 00 00 00
ZERO- MEMORY
ELEVEN- MEMORY
0 1 2
X 00 00 00

store character from the accumulator to STR2

by performing indexed addressing mode.

0 1 2
A 00 00 54
 0 1 2 3 4 5 6 7 8 9 10
T E S T S T R I N G
STR1 54 45 53 54 20 53 54 52 49 4E 47

0 1 2 3 4 5 6 7 8 9 10

STR2 54

0 1 2 0 1 2
ELEVEN 00 00 0B ZERO 00 00 00
ZERO- MEMORY
ELEVEN- MEMORY
0 1 2
X 00 00 01

0 1 2
A 00 00 54
Increment the value of X by 1 and
compare the value of X with ELEVEN
IF X<ELEVEN
Set the value of CC=JLT
 0 1 2 3 4 5 6 7 8 9 10
T E S T S T R I N G
STR1 54 45 53 54 20 53 54 52 49 4E 47

0 1 2 3 4 5 6 7 8 9 10

STR2 54

0 1 2 0 1 2
ELEVEN 00 00 0B ZERO 00 00 00
ZERO- MEMORY
ELEVEN- MEMORY
0 1 2
X 00 00 01

0 1 2
A 00 00 45
 0 1 2 3 4 5 6 7 8 9 10
T E S T S T R I N G
STR1 54 45 53 54 20 53 54 52 49 4E 47

0 1 2 3 4 5 6 7 8 9 10

STR2 54 45

0 1 2 0 1 2
ELEVEN 00 00 0B ZERO 00 00 00
ZERO- MEMORY
ELEVEN- MEMORY
0 1 2
X 00 00 01

0 1 2
A 00 00 45
Example 3
LDA APLHA
ADD INCR
SUB ONE
STA BEETA
ONE WORD 1
ALPHA RESW 1
BEETA RESW 1
INCR RESW 1
 JSUB READ
INDEV F1
-
-
.
READ LDX ZERO
TD INDEV
JEQ RLOOP
RD INDEV
STCH RECORD, X
TIX K100
JLT RLOOP
RSUB
-
-
INDEV BYTE X’F1’
RECORD RESB 100
.
ZERO WORD 0
K100 WORD 100
 JSUB READ
INDEV F1
-
B0 B1.........................B99
-
RECORD
.
READ LDX ZERO
TD INDEV
JEQ RLOOP
RD INDEV
STCH RECORD, X
TIX K100
JLT RLOOP
RSUB
-
-
INDEV BYTE X’F1’
RECORD RESB 100
ZERO WORD 0
K100 WORD 100
 JSUB READ
INDEV F1
-
B0 B1.........................B99
-
RECORD
.
READ LDX ZERO B0 B1 B2
TD INDEV ZERO 00 00 00
JEQ RLOOP
RD INDEV
STCH RECORD, X
TIX K100
JLT RLOOP
RSUB
-
-
INDEV BYTE X’F1’
RECORD RESB 100
ZERO WORD 0
K100 WORD 100
 JSUB READ
INDEV F1
-
B0 B1.........................B99
-
RECORD
.
READ LDX ZERO B0 B1 B2
TD INDEV ZERO 00 00 00
JEQ RLOOP B0 B1 B2
RD INDEV K100 00 00 64
STCH RECORD, X
TIX K100
JLT RLOOP
RSUB
-
-
INDEV BYTE X’F1’
RECORD RESB 100
ZERO WORD 0
K100 WORD 100
 JSUB READ INDEV F1
-
B0 B1.........................B99
- RECORD

. B0 B1 B2
READ LDX ZERO ZERO 00 00 00
TD INDEV
B0 B1 B2
JEQ RLOOP K100 00 00 64
RD INDEV B0 B1 B2
STCH RECORD, X X 00 00 00
TIX K100
JLT RLOOP
RSUB
-
-
INDEV BYTE X’F1’
RECORD RESB 100
ZERO WORD 0
K100 WORD 100
 JSUB READ TEST DEVICE FOR READY
INDEV F1
IF YES CC= JLT
- ELSE CC= JEQ
B0 B1.........................B99
- RECORD

. B0 B1 B2
READ LDX ZERO ZERO 00 00 00
RLOOP TD INDEV
B0 B1 B2
JEQ RLOOP K100 00 00 64
RD INDEV B0 B1 B2
STCH RECORD, X X 00 00 00
TIX K100
JLT RLOOP
RSUB
-
-
INDEV BYTE X’F1’
RECORD RESB 100
ZERO WORD 0
K100 WORD 100
 JSUB READ INDEV F1
-
B0 B1.........................B99
- RECORD

. B0 B1 B2
READ LDX ZERO ZERO 00 00 00
RLOOP TD INDEV
B0 B1 B2
JEQ RLOOP K100 00 00 64
RD INDEV B0 B1 B2
STCH RECORD, X X 00 00 00
TIX K100
JLT RLOOP
RSUB
-
-
INDEV BYTE X’F1’
RECORD RESB 100
ZERO WORD 0
K100 WORD 100
 JSUB READ INDEV F1
- INPUT DEVICE
B0 B1.........................B99
- RECORD

. B0 B1 B2
READ LDX ZERO ZERO 00 00 00
RLOOP TD INDEV
B0 B1 B2
JEQ RLOOP K100 00 00 64
RD INDEV B0 B1 B2
STCH RECORD, X X 00 00 00
TIX K100
JLT RLOOP NOW LEST ASSUME THAT THE DEVICE IS
RSUB READY.
-
-
INDEV BYTE X’F1’
RECORD RESB 100
ZERO WORD 0
K100 WORD 100
 JSUB READ
-
B0 B1.........................B99
- RECORD 71

. B0 B1 B2
READ LDX ZERO ZERO 00 00 00
RLOOP TD INDEV
B0 B1 B2
JEQ RLOOP K100 00 00 64
LET THE
RD INDEV B0 B1 B2 CHARACTER
STCH RECORD, X X 00 00 00 READ BY THE
TIX K100 DEVICE IS
INDEV F1 'GEU’
JLT RLOOP
RSUB Read the character from INDEV and store
- into accumulator A
-
A xx xx 71
INDEV BYTE X’F1’
RECORD RESB 100
ZERO WORD 0
K100 WORD 100
 JSUB READ INDEV F1
-
B0 B1.........................B99
- RECORD 71

. B0 B1 B2
READ LDX ZERO ZERO 00 00 00 LET THE
RLOOP TD INDEV
B0 B1 B2 CHARACTER
JEQ RLOOP READ BY THE
K100 00 00 64
DEVICE IS
RD INDEV B0 B1 B2 'GEU'
STCH RECORD, X X 00 00 00
TIX K100
JLT RLOOP
A xx xx 71
RSUB
-
- STORE THE CONTENT OF THE Accumulator in
RECORD BY PERFORMING THE INDEXED (X)
INDEV BYTE X’F1’
ADDRESSING MODE.
RECORD RESB 100
ZERO WORD 0
K100 WORD 100
 JSUB READ INDEV F1
-
B0 B1.........................B99
- RECORD 71

. B0 B1 B2
READ LDX ZERO ZERO 00 00 00 LET THE
RLOOP TD INDEV
B0 B1 B2 CHARACTER
JEQ RLOOP READ BY THE
K100 00 00 64
DEVICE IS
RD INDEV B0 B1 B2 'GEU'
STCH RECORD, X X 00 00 01
TIX K100
A xx xx 71
JLT RLOOP
RSUB
COMPARE THE VALUE OF X WITH K100,
- AFTER INCREMENT IN X.
- 64>1
SET CC=JLT
INDEV BYTE X’F1’
RECORD RESB 100
ZERO WORD 0
K100 WORD 100
 JSUB READ INDEV F1
-
B0 B1.........................B99
- RECORD 71

. B0 B1 B2
READ LDX ZERO ZERO 00 00 00 LET THE
RLOOP TD INDEV
B0 B1 B2 CHARACTER
JEQ RLOOP READ BY THE
K100 00 00 64
DEVICE IS
RD INDEV B0 B1 B2 'GEU'
STCH RECORD, X X 00 00 01
TIX K100
A 00 00 71
JLT RLOOP
RSUB
COMPARE THE VALUE OF X WITH K100,
- AFTER INCREMENT IN X.
- 64>1
SET CC=JLT
INDEV BYTE X’F1’
RECORD RESB 100
ZERO WORD 0
K100 WORD 100
 JSUB READ INDEV F1
-
B0 B1.........................B99
- RECORD 71

. B0 B1 B2
READ LDX ZERO ZERO 00 00 00 LET THE
RLOOP TD INDEV
B0 B1 B2 CHARACTER
JEQ RLOOP READ BY THE
K100 00 00 64
DEVICE IS
RD INDEV B0 B1 B2 'GEU'
STCH RECORD, X X 00 00 01
TIX K100
A 00 00 64
JLT RLOOP
RSUB
-
-
INDEV BYTE X’F1’
RECORD RESB 100
ZERO WORD 0
K100 WORD 100
 JSUB READ INDEV F1
-
B0 B1.........................B99
- RECORD 71 69

. B0 B1 B2
READ LDX ZERO ZERO 00 00 00 LET THE
RLOOP TD INDEV
B0 B1 B2 CHARACTER
JEQ RLOOP READ BY THE
K100 00 00 64
DEVICE IS
RD INDEV B0 B1 B2 'GEU'
STCH RECORD, X X 00 00 01
TIX K100
A 00 00 64
JLT RLOOP
RSUB
-
-
INDEV BYTE X’F1’
RECORD RESB 100
ZERO WORD 0
K100 WORD 100
Cont…………….. JSUB READ
-
-
.
READ LDX ZERO
RLOOP TD INDEV
JEQ RLOOP
RD INDEV
STCH RECORD, X
TIX K100
JLT RLOOP
RSUB
-
-
INDEV BYTE X’F1’
RECORD RESB 100
ZERO WORD 0
K100 WORD 100
 SIC/XE MACHINE ARCHITECTURE

•Memory
Maximum memory available on a SIC/XE
system is 1 Megabyte (220 bytes)

•Registers
Additional B, S, T, and F registers are
provided by SIC/XE, as compared to SIC.
REGISTERS

Mnemonic Number Special use

B 3 Base register
S 4 General working register
T 5 General working register
F 6 Floating-point accumulator (48
bits)
FLOATING-POINT DATA TYPE
• Same as SIC.
• There is a 48-bit floating-point data type

1 11 36
s exponent fraction

F*2(e-1024)
 INSTRUCTION FORMATS

Format 1 (1 byte) 8
op
Eg-RSUB
8 4 4
Format 2 (2 bytes)
op r1 r2
Formats 1 and 2 are instructions that do not
reference memory at all
e.g. COMPR A, S
 CONTINUED…
Format 3 (3 bytes)
6 1 11111 12
op n i xbpe disp
Displacement byte
Format 4 (4 bytes)
6 1 11111 20
op n i xbpe address
 ADDRESSING MODES & FLAG BITS

•e - e = 0 means format 3, e = 1
means format 4

•Bits x,b,p: Used to calculate the target address

using relative, direct, and indexed addressing
Modes

•Bits i and n: Says, how to use the target address

FLAG BITS CONTINUED…

Format 3 or 4
 ADDRESSING MODES
Format 3
Mode Indicatio Target address calculation
n
TA=(Base)+ disp
Base relative b=1,p=0 (0disp 4095) (disp can't be
-ve)
TA=(PC)+ disp
Program- (-2048disp 2047) (disp can
b=0,p=1
counter relative be -ve)

(Base)- the content of the base register. Always represents in 3 bits

 FLAG BITS CONTINUED…

•b and p - both set to 0, disp field from

format 3 instruction is taken to be the target
address.
•For a format 4 bits b and p are normally set to
0, a 20-bit address is the target address
•x - x is set to 1, X register value is added
for target address calculation
 INSTRUCTION SET

•Instructions to load and store the new

registers LDB, STB, etc.
•Floating-point arithmetic operations
ADDF, SUBF, MULF, DIVF
•Register move instruction : RMO
•Register-to-register arithmetic operations
ADDR, SUBR, MULR, DIVR
•Supervisor call instruction : SVC
 INPUT AND OUTPUT

•There are I/O channels that can be used to

perform input and output while the CPU is
executing other instructions
•Allows overlap of computing and I/O,
resulting in more efficient system operation
• The instructions SIO, TIO, and HIO are used
 Format 3 Instructions

1. Base relative Addressing Mode Example

STX(10) LENGTH 6 1 1 1 1 1 1 12
(B)=0033 op n i x b p e disp
TA=0033
disp=TA-(B) 00010000 1 1 0 1 0 0 0000 0000 0000
Disp=0033-0033=0000 Direct addressing mode so n, i=1,
there is NO indexed addressing so x=0
0000- We discard the first bit, base relative so b=1, p=0
as we need to represent a total format 3 inst. so e=0
of 12 bits for displacement.

Object code (in HEX)=134000

Note- In SIC/XE there always be opcode in such a way that no effect after
the last two-digit truncation.
2. Base relative Addressing Mode Example
6 1 1 1 1 1 1 12
op n i x b p e disp
STCH(54) BUFFER, X
(B)=0033
0101 0100 1 1 1 1 0 0 0000 0000 0011
TA=0036
disp=TA-(B) Direct addressing mode so n, & i=1,
Disp=0036-0033=0003 there is index addressing so x=1
base relative so b=1, p=0
format 3 inst. so e=0
1. PC relative Addressing Mode Example
6 1 1 1 1 1 1 12
op n i x b p e disp

0001 0100 1 1 0 0 1 0 0000 0000 0011

0000 STL (14) RETADR Direct addressing mode so n, & i=1,
TA=0030 there is no index addressing so x=0
disp=TA-(PC) PC relative so b=0, p=1
PC=0000+3(3Bytes) format 3 inst. so e=0
Disp=0030-0003=000D

Object code (in HEX)=17202D

2. No Addressing Mode Example
6 1 1 1 1 1 1 12
op n i x b p e disp

0000 0000 0 1 0 0 0 0 0000 0000 1001

LDA(00) #9 Immediate addressing mode so n=0, & i=1,
#-immediate addressing there is no index addressing so x=0
No base relative so b=0, p=0
format 3 inst. so e=0

Object code (in HEX)=010009

2. Indirect Addressing Mode Example

6 1 1 1 1 1 1 12
op n i x b p e disp

0010 1100 0 1 0 0 1 0 0000 0000 0011

002A J(2C) @RETADR Indirect addressing mode so n=1, & i=0,
TA=0030 there is no index addressing so x=0
@-indirect addressing mode PC relative so b=0, p=1
Disp=TA-(PC) format 3 inst. so e=0
= 0030-002D
=0003

Object code (in HEX)=2E2003

 Format 4 Instructions
6 1 1 1 1 1 1 20
op n i x b p e address

+ shows that it is format four instruction

+JSUB(48) RDREC
If we have not given + a sign, we apply PC
TA=1036
or base relative addressing mode. Now
check if the resultant displacement is more
New TA=01036
than 12 bits then it will be a format 4
instruction else format 3.
0100 1000 1 1 0 0 0 1 0000 0001 0000 0011 0110
Direct addressing mode so n, i=1,
There is indexed addressing so x=0
No base relative so b=0, p=0
format 4 inst. so e=1
Object code (in HEX)=4D101036
EXAMPLE PROGRAMS (SIC/XE)
Example 1 BYTE0 BYTE1 BYTE3
LDA #5 (immediate) ALPHA
STA ALPHA (Direct)
LDCH #90 (immediate)
STCH C1 (Direct)
.
.
ALPHA RESW 1
C1 RESB 1
EXAMPLE PROGRAMS (SIC/XE)
Example 1 BYTE0 BYTE1 BYTE3
LDA #5 ALPHA
STA ALPHA
LDCH #90 BYTE0
STCH C1 C1
.
.
ALPHA RESW 1
C1 RESB 1
EXAMPLE PROGRAMS (SIC/XE)
Example 1 BYTE0 BYTE1 BYTE3
LDA #5 ALPHA
STA ALPHA
LDACH #90 BYTE0
STCH C1 C1
.
.
A 00 00 05
ALPHA RESW 1
C1 RESB 1

load the immediate value 5 into

accumulator
EXAMPLE PROGRAMS (SIC/XE)
Example 1 BYTE0 BYTE1 BYTE3
LDA #5 ALPHA 00 00 05
STA ALPHA
LDCH #90
STCH C1 store the content of
. BYTE0 the accumulator in
. C1 ALPHA
ALPHA RESW 1
C1 RESB 1

A 00 00 05
EXAMPLE PROGRAMS (SIC/XE)
Example 1 BYTE0 BYTE1 BYTE3
LDA #5 ALPHA 00 00 05
STA ALPHA
LDCH #90
STCH C1
. BYTE0
. C1
ALPHA RESW 1
C1 RESB 1

A xx xx 5A

load the immediate value 90 into the

accumulator
EXAMPLE PROGRAMS (SIC/XE)
Example 1 BYTE0 BYTE1 BYTE3
LDA #5 (immediate) ALPHA 00 00 05
STA ALPHA (Direct)
LDCH #90 (immediate)
STCH C1 (Direct)
. BYTE0
. C1 5A
ALPHA RESW 1
C1 RESB 1

A xx xx 5A
Example 2 STR1
T

54
E

45 53
S T

54 20
S

53
T

54
R

52 49
I N

4E
G

47
LDT #11
LDX #0
MOVCH LDCH STR1, X 0 1 2 3 4 5 6 7 8 9 10

STCH STR2, X STR2

TIXR T
JLT MOVCH 0 1 2
- - ZERO 00 00 00
STR1 BYTE C’ TEST 0 1 2
STRING
T
STR2 RESB 11
0 1 2
X

0 1 2
A
Example 2 STR1
T

54
E

45 53
S T

54 20
S

53
T

54
R

52 49
I N

4E
G

47
LDT #11
LDX #0
MOVCH LDCH STR1, X 0 1 2 3 4 5 6 7 8 9 10

STCH STR2, X STR2

TIXR T
JLT MOVCH 0 1 2
- - ZERO 00 00 00
STR1 BYTE C’ TEST 0 1 2
STRING
T 00 00 0B
STR2 RESB 11
0 1 2
X 00 00 00

0 1 2
A XX XX
Example 2 STR1
T

54
E

45 53
S T

54 20
S

53
T

54
R

52 49
I N

4E
G

47
LDT #11
LDX #0
MOVCH LDCH STR1, X 0 1 2 3 4 5 6 7 8 9 10

STCH STR2, X STR2

TIXR T
JLT MOVCH 0 1 2
- - ZERO 00 00 00
STR1 BYTE C’ TEST 0 1 2
STRING
T 00 00 0B
STR2 RESB 11
0 1 2
X 00 00 00

0 1 2
A XX XX
Example 2 STR1
T

54
E

45 53
S T

54 20
S

53
T

54
R

52
I

49
N

4E
G

47
LDT #11
LDX #0
MOVCH LDCH STR1, X 0 1 2 3 4 5 6 7 8 9 10

STCH STR2, X STR2

TIXR T
JLT MOVCH 0 1 2
- - ZERO 00 00 00
STR1 BYTE C’ TEST 0 1 2
STRING
T 00 00 0B
STR2 RESB 11
0 1 2
X 00 00 00

0 1 2
A XX XX 54
Example 2 STR1
T

54
E

45 53
S T

54 20
S

53
T

54
R

52
I

49
N

4E
G

47
LDT #11
LDX #0
MOVCH LDCH STR1, X 0 1 2 3 4 5 6 7 8 9 10

STCH STR2, X STR2 54

TIXR T
JLT MOVCH 0 1 2
- - ZERO 00 00 00
STR1 BYTE C’ TEST 0 1 2
STRING
T 00 00 0B
STR2 RESB 11
0 1 2
X 00 00 00

0 1 2
A XX XX 54
Example 2 STR1
T

54
E

45 53
S T

54 20
S

53
T

54
R

52
I

49
N

4E
G

47
LDT #11
LDX #0
MOVCH LDCH STR1, X 0 1 2 3 4 5 6 7 8 9 10

STCH STR2, X STR2 54

TIXR T
JLT MOVCH 0 1 2
- - ZERO 00 00 00
STR1 BYTE C’ TEST 0 1 2
STRING
T 00 00 0B
STR2 RESB 11
0 1 2
X 00 00 01

0 1 2
A XX XX 54
Example 2 STR1
T

54
E

45 53
S T

54 20
S

53
T

54
R

52
I

49
N

4E
G

47
LDT #11
LDX #0
MOVCH LDCH STR1, X 0 1 2 3 4 5 6 7 8 9 10

STCH STR2, X STR2 54

TIXR T
JLT MOVCH 0 1 2
- - ZERO 00 00 00
STR1 BYTE C’ TEST 0 1 2
STRING
T 00 00 0B
STR2 RESB 11
0 1 2
X 00 00 01

0 1 2
A XX XX 54
 DIFFERENT ARCHITECTURES

•Traditional (CISC) machines

- VAX (Virtual Address
eXtension) Architecture
- Pentium Pro Architecture
•RISC machines
- UltraSPARC Architecture
- Cray T3E Architecture
 COMPARISON OF THESE

•Memory
•Registers
•Data Formats
•Instruction Formats
•Addressing Modes
•Instruction Set
•Input and Output
 TRADITIONAL (CISC) MACHINES

•Complex Instruction Set Computers

•Has a relatively large and complex instruction set
•Different instruction formats, different lengths,
different addressing modes
•Implementation of hardware is complex
• VAX and Intel x86 processors are examples
 VAX ARCHITECTURE

Memory - The VAX memory consists of 8-bit

bytes.
•Two consecutive bytes form a word, Four
bytes form a long word, eight bytes form a
quadword, and sixteen bytes form an octaword.
•All VAX programs operate in a virtual address
space of 232 bytes, One half is called system
space, other half is process space
 REGISTERS

•16 GPRs, 32 bits each, R0 to R15, PC

(R15), SP (R14), Frame Pointer FP ( R13),
Argument Pointer AP (R12) ,Others available
for general use
•Process status longword (PSL) – for flags
 DATA FORMATS

•Integers are stored as binary numbers in byte,

word, longword, quadword, octaword
•2’s complement for negative numbers
•Characters 8-bit ASCII codes
•Four different floating-point data formats
 INSTRUCTION
FORMATS

•Uses variable-length instruction formats – op

code 1 or 2 bytes, maximum of 6 operand
specifiers depending on type of instruction
•Tabak – Advanced Microprocessors (2 nd
edition) McGraw-Hill, 1995
 ADDRESSING MODES

•VAX provides many addressing modes

•Register mode
•register deferred mode
•Autoincrement
• autodecrement
• base relative
• program-counter relative
• indexed
• indirect
• immediate
 INSTRUCTION SET

• Symmetric with respect to data type - Uses

prefix – type of operation, suffix – type of
operands, a modifier – number of operands
• ADDW2 - add, word length, 2 operands,
MULL3 - multiply, longwords, 3 operands
CVTCL - conversion from word to longword
•VAX provides instructions to load and store
multiple registers
 INPUT AND OUTPUT

• Uses I/O device controllers

• Device control registers are mapped to
separate I/O space
•Software routines and memory management
routines are used
 RISC MACHINES

•Reduced Instruction Set Computers

•Intended to simplify the design of processors.
Greater reliability, faster execution and less
expensive processors
•Standard and fixed instruction length
•Number of machine instructions, instruction
formats, and addressing modes relatively small
 ULTRASPARC ARCHITECTURE

•Introduced by Sun Microsystems

•SPARC – Scalable Processor ARChitecture,
•SPARC, SuperSPARC, UltraSPARC - upward
compatible and share the same basic structure
MEMORY

•Consists of 8-bit bytes, all addresses used

are byte addresses. Two consecutive bytes
form a halfword, four bytes form a word ,
eight bytes form a double word

•Uses virtual address space of 264 bytes,

divided into pages
REGISTERS

•More than 100 GPRs, with 64 bits length

each ( Register file)
•64 double precision floating-point registers,
in a special floating-point unit (FPU)
•PC, condition code registers, and control
registers
 DATA FORMATS

•Integers – 8-, 16-, 32- or 64-bit binary

numbers
•Signed, unsigned for integers and 2’s
complement for negative numbers
•Supports both big-endian and little-endian
byte orderings
•Floating-point data formats – single, double
and quad-precision
•Characters – 8-bit ASCII value
INSTRUCTION FORMATS

•32-bits long, three basic instruction formats

•First two bits identify the format
•Format 1 used for call instruction
•Format 2 used for branch instructions
•Format 3 used for load, store and for
arithmetic operations
 ADDRESSING MODES

•Immediate mode,
•register-direct mode,
•PC-relative,
•Register indirect with displacement,
•Register indirect indexed
 INSTRUCTION SET

•Has fewer than 100 machine instructions

•The only instructions that access memory
are loads and stores. All other instructions
are register-to-register operations
•Instruction execution is pipelined – results
in faster execution, speed increases
 INPUT AND OUTPUT

•Communication through I/O devices is

accomplished through memory
•A range of memory locations is logically
replaced by device registers
•When a load or store instruction refers to this
device register area of memory, the
corresponding device is activated
•There are no special I/O instructions
 MEMORY

•Each PE in T3E has its own local memory

with a capacity of from 64 megabytes to 2
gigabytes

•Consists of 8-bit bytes, all addresses used

are byte addresses. Two consecutive bytes
form a word, four bytes form a longword ,
eight bytes form a quadword
 REGISTERS

•32 GPRs, with 64 bits length each called

R0 through R31, contains value zero always
•32 floating-point registers, 64 bits long
•64-bit PC, stauts , and control registers
 DATA FORMATS

•Integers –long and quad word binary numbers

•2’s complement for negative numbers
•Supports little-endian byte orderings
•Two different floating-point data formats –
VAX and IEEE standard
•Characters – 8-bit ASCII value
 INSTRUCTION FORMATS

•32-bits long, five basic instruction formats

•First six bits always identify the opcode
 ADDRESSING MODES

•Immediate mode,
•register-direct mode,
•PC-relative,
•Register indirect with displacement,
 INSTRUCTION SET

•Has approximately 130 machine

instructions
•There are no byte or word load and store
instructions
•Smith and Weiss – “PowerPC 601 and
Alpha 21064: A Tale of TWO RISCs “ –
Gives more information
 INPUT AND OUTPUT

•Communication through I/O devices is

accomplished through multiple ports and I/O
channels
•Channels are integrated into the network that
interconnects the processing elements
•All channels are accessible and controllable
from all PEs
 EXAMPLE PROGRAMS (SIC)
LDX ZERO
CLOOP TD INDEV
JEQ CLOOP
To transfer two
hundred bytes of
RD INDEV
data from input STCH RECORD, X
device to memory
TIX B200
JLT CLOOP
.
.
INDEV BYTE X ‘F5’
RECORD RESB 200
ZERO WORD 0
B200 WORD 200
 EXAMPLE PROGRAMS (SIC/XE)

LDT #200
LDX #0
CLOOP TD INDEV
JEQ CLOOP
To transfer two RD INDEV
hundred bytes of
data from input STCH RECORD, X
device to memory
TIXR T
JLT CLOOP
.
.
INDEV BYTE X ‘F5’
RECORD RESB 200
 EXAMPLE PROGRAMS (SIC)
JSUB READ
.
READ LDX ZERO
CLOOP TD INDEV
Subroutine to
JEQ CLOOP
transfer two RD INDEV
hundred bytes of STCH RECORD, X
data from input TIX B200 : add 1 to index compare 200 (B200)
device to memory
JLT CLOOP
RSUB
.
INDEV BYTE X ‘F5’
RECORD RESB 200
ZERO WORD 0
B200 WORD 200
 EXAMPLE PROGRAMS (SIC/XE)
JSUB READ
.
.
READ LDT #200
LDX #0
CLOOP TD INDEV
JEQ CLOOP
RD INDEV
Subroutine to STCH RECORD, X
transfer two
hundred bytes of TIXR T : add 1 to index compare T
data from input JLT CLOOP
device to memory RSUB
.
.
INDEV BYTE X ‘F5’
RECORD RESB 200