PCB Designs & Signal Integrity

PCB Designs & Signal Integrity
Packaging and circuit boards

Single IC can not form complete digital system It need packaging for inter IC communications for input/ output displays and other devices IC is bonded into single package which serve several purposes. It protects the IC from moisture and airborne contaminants, provides electrical connections and removes heat Several IC packages with different physical, electrical and thermal properties are available The choice of package depends on the number of connections required and the environment in which the product is to operate, among other factors.
Printed circuit board

The packaged ICs and other components in a system are assembled together on a printed circuit board (PCB). This consists of layers of fiberglass or other insulating material separating layers of metal wiring. The metal is deposited in a layer on a fiberglass sheet, and then etched using a photolithographic process, similar to that used in manufacturing ICs. Several layers are sandwiched together. Small holes are drilled through the layers and coated with metal to form connections, called vias, between the layers. The completed PCB contains all the circuit wiring needed for the product.
Types of PCB
Through hole PCB: Surface mount PCB
Through hole PCB

Includes additional metal-coated holes into which IC package pins are inserted.
Use insertion-type packages, . Dual in-line packages (DIPs) have two rows of pins with 0.1-inch spacing. DIP up to 48 pin configuration 0.1 inch spacing Pin grid array (PGA) 400 and above minimum spacing
Advantage - they can be manually assembled, since the component sizes are manageable. Disadvantage -- Fails if pin count increases
Surface-mount PCB
Components are mounted on the surface rather than being inserted in holes. This has the advantage of reduced manufacturing cost (for higher-volume products), finer feature sizes and increased circuit density. Surface mounting IC packages have pins or connection points that come into contact with a metal pad on the PCB. Solder paste is applied between each pin and pad and subsequently melted, forming the connection. Different surface mounting packages, Quad flat-pack (QFP) -- pins along all four sides, ICs with up to 200 pins. The spacing between pins varies from 1 mm for the packages with fewer pins, < 100 pins 0.65mm for the higher pin-count packages. 200 pin s 0.4mm increased pin count, up to nearly 400 pins, The ball grid array (BGA) package. high pin count -- 1800 pins , multichip modules (MCMs) attach the base chips to a ceramic substrate chip stacking involves -- placing two or more chips in a vertical stack. Connections can be made between adjacent chips by metal contacts, and between chips and the containing package by bond wires.
1. How does flip-chip IC packaging differ from previous packaging technologies? 2. Explain different PCB mount technologies for ICS
Interconnections and Signal Integrity

Signals changes between low and high logic levels instantaneously. an abstraction, In reality signals take time to change and time to propagate along signal wires varies. Consider signal propagation between a source and a destination within a circuit and different IC. problems path may be from the source driver-- through the bond wire-- package lead and from pin of the source IC along the PCB trace,-- through the pin, lead frame and bond wire of the destination IC, -- into the receiver. Along path several influences can cause signal to distort by noise
Signal integrity : It is the degree to which effects along the path are minimized. If we are using off-the-shelf lCs or PLDs, we do not have cntrol over the path within the IC package. We must assume that the designers of the IC and package have done due diligence to maintain signal integrity. Signal integrity is important in implementing a design in an ASIC, Since this is a complex area, A change in a signal value causes a change in the current flowing through the PCB trace. This causes a change in the electric and magnetic fields around the trace. Propagation of those fields determines the speed of propagation of the signal change along the trace. In common PCB materials, the maximum propagation speed is approximately half the speed of light in a vacuum. i.e 150mm per nanosecond as a good rule of thumb for signal propagation along a PCB trace. For low speed designs and small PCBs, this element of total path delay is insignificant.
However, for high-speed designs, particularly for signals on critical timing paths, it is significant. Two cases 1. The routing of clock signals -- . If a clock signal is routed through paths of different lengths to different ICs, we may introduce clock skew 2. Parallel bus signals -- if different signals within a parallel bus are routed along paths of different lengths, changes in elements of the bus may not arrive concurrently, and may be incorrectly sampled at the destination's receiver. In these cases, it may be necessary to tune the timing of the system by adding to the length of some PCB traces to match propagation delays.
Signal integrity issues in PCB
1. Ground bounce 2. High slew rate signals -- Noise
SI issue Ground bounce

It arises when one or more output drivers switch logic levels. During switching, both of the transistors in the driver's output stage are momentarily on, and transient current flows from the power supply to ground. Ideally, the power supply can source the transient current without distortion. In reality, however, there is inductance in both the power and the ground connections, as shown in fig The inductance causes voltage spikes in the power supply and ground on the IC. This can cause voltage spikes on other output drivers, possibly causing false transitions in the receivers to which they are connected. It can also cause transient shifting of the threshold voltage of receivers on the IC causing false transitions at those receivers. The effect is particularly pronounced when multiple drivers switch concurrently.
Reduction in Ground Bounce

. First, we can place bypass capacitors between power and ground at strategic places around a PCB. These capacitors hold a reserve of charge that can quickly supply the needs of switching drivers[ Values of 0.01pF to 0.1pF are common.] Second, we can use separate PCB layers for the ground and power supply. This gives a low-inductance path for the power supply current and its ground return
Third, we can !imit the rate of voltage change (the slew rate) and limit the drive current of the output drivers. These actions limit the rate of change of current, and so limit the inductive effect of the change.
Of course, reducing the slew rate means that a signal takes longer to change from one logic level to the other, as illustrated in Figure Hence, limiting slew rate may increase propagation delay through circuits, consequently requiring a reduction in clack rate. This is a case where a trade-off between speed of operation and noise immunity may be required.
Slew rate
Another signal integrity issue for high-slew rate signals is noise due to transmission-line effects. When the time for a transition between logic levels is similar to or shorter than the propagation delay along a signal path, the transition is affected by reflections at the driving and receiving ends of the path . A full analysis of the effects requires knowledge of the characteristic impedance of the path, as well as the source impedance of the driver and the terminating indepedance of the receiver. Depending on the relationships between these values, the signal may suffer from partial transitions, overshoot, undershoot and ringing shown in Figure
The main design techniques for managing transmission-line effects involve appropriate layout and proper termination of PCB traces. By running a trace of specific dimensions at a controlled distance between two ground or power planes in the PCB, we create a strip/line transmission line with a controlled characteristic impedance Where the transmission line effects are less critical, we can run a trace over just one plane, creating a microstrip transmission line. For critical signals, we can adopt circuit designs and layouts that avoid placing receivers along the PCB trace, or that group them together at the receiving end .. Finally, we can include termination resistors to ensure proper matching of drivers and receivers to the characteristic impedance of the transmission line. In high performance modern components, including FPGAs, the drivers include termination resistors on the IC.. In other cases, we may need to include resistors as discrete components adjacent to IC pins.
Differential Signalling
The techniques for maintaining signal integrity that we have discussed so far are based on reducing the amount of interference induced on signal wires. Another technique, use of differential Signalling, is based on the idea of reducing a system's susceptibility to interference. Rather than transmitting a bit of information as a single signal S, we transmit both the positive signal S_P and its negation S_N. At the receiving end, we sense the voltage difference between the two signals. If S_P - S_N is a positive voltage, then S is received as the value 1; if S_P - S_N is a negative voltage, then S is received as O. The assumption behind the differential signalling approach is that noise is induced equally on the wires for both S_P and S_N. Such common-mode noise is cancelled out when we sense the voltage difference. To show this, suppose a noise voltage VN is induced equally on the two wires. At the receiver, we sense the voltage
Differential Signalling
Signal on B is inverse of A Difference between VA and VB is 2X the amplitude Improved noise rejection, speed, distance and reliability
(A+Vn)-(-B+Vn) = A+B
Differential Cancels Noise

Noise and external interference has equal impact on each wire in the pair A-B differential cancels out noise
Common-mode offset (ground shift) is also cancelled out
Comparison of PROFIBUS and RS-485
Serial Communication Standards

ITU-T V.10 Single Ended electrical circuits for data communication at up to 100 kbps V.11 - Differential electrical circuits for data communication at up to10 Mbps V.28 - electrical characteristics for single ended double-current interchange circuits V.35 - specifications from V.11 for the differential signals, while the control signals remain single ended. V.36 Modems spec. for synchronous data transmission using 60-108 kHz group band circuits X.21 - All signals are balanced.. Electrically the X.21 signals are thesame as RS-422 EIA-530 defines pin out on a 25 pin connector RS-449 defines the pin out on a 37 pins connector

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PCB Designs & Signal Integrity

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PCB Designs & Signal Integrity

Packaging and circuit boards

Printed circuit board

Through hole PCB

Interconnections and Signal Integrity

Signal integrity issues in PCB

1. Ground bounce 2. High slew rate signals -- Noise

SI issue Ground bounce

Reduction in Ground Bounce

Differential Cancels Noise

Common-mode offset (ground shift) is also cancelled out

Comparison of PROFIBUS and RS-485

Serial Communication Standards

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