L2 - Multiprocessor System
L2 - Multiprocessor System
L2 - Multiprocessor System
• Bus contention
– Bus contention is an undesirable state of the bus in which more than
one device on the bus attempts to place values on the bus at the
same time. Most bus architectures require their devices to follow an
arbitration protocol carefully designed to make the likelihood
of contention negligible.
⮚Coprocessor Configuration
⮚Closely Coupled Configuration
⮚Loosely Coupled Configuration
Coprocessor Configuration
⮚Introduction
⮚Characteristics
⮚Interaction between CPU & Coprocessor
Coprocessor configuration
• The configuration in which coprocessor is connected with the main
processor is called coprocessor configuration.
• Main processor and coprocessor work parallely in the system.
• For example, 8087 is a coprocessor for the 8086 processor
• 8087 coprocessor mainly used for numeric calculation.
• After calculation it supplies its result to the main processor .
• Then main processor work with the result supplied by the
coprocessor.
Coprocessor configuration
Characteristics
• Both the dominant processor and coprocessor uses same clock
generator.
• Main processor and the coprocessor shares the bus control logic.
• Dominant processor and coprocessor communicates with some specific
instructions.
Interaction between CPU & Coprocessor
• The host CPU fetch instructions, but coprocessor also receives all
instructions and monitor them.
• An instruction to be executed by the coprocessor is indicated when an
escape (ESC) instruction appears.
• This ESC instruction contains an external operation code.
• Both processor and coprocessor decodes it but coprocessor executes
the instruction.
Interaction between CPU & Coprocessor (Contd.)
• At this point, the host may simply go on the next instruction or it may
fetch the first word of a memory operand for the coprocessor and then
go on next instruction.
• While coprocessor executes an instruction, it sends a busy (high) signal
to host’s TEST pin.
• As the host continues processing instruction stream, the coprocessor
will perform operation indicated by the code in ESC instruction.
• If the host needs result of coprocessor it executes WAIT instruction and
stop parallel operation.
Interaction between CPU & Coprocessor (Contd.)
• The host has to wait until TEST pin of host is activated by coprocessor .
• The WAIT instruction repeatedly checks the test pin to check activation
status of host.
• When coprocessor completes its operation, it activates the TEST pin.
• When the TEST pin is activated. The host executes the next instruction
in sequence.
Synchronization between 8086 and its coprocessor
8086
Coprocessor
Wake up th
ESC e coproces
sor
Monitor the
8086 or
8088
Execute the
8086
instructions Deactivate the
host’s TEST pin &
execute the
specified
WAIT operation.
Wake up
the 8086 or 8
088
Activate the
TEST pin
Closely Coupled Configuration
⮚Introduction
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Closely Coupled Configuration
1. The second configuration is Closely Coupled Configuration.
2. In this configuration, the 8086/8088 supports independent
processor, which unlike a coprocessor, executes its own
instruction stream.
3. Closely coupled multiprocessor system share the same clock and
bus control logic.
4. The independent processor access bus through the CPU’s RQ/GT
lines.
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Loosely Coupled Configurations
Introduction, advantages
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Introduction
❑ In a loosely coupled multi processor system each CPU has its own
bus control logic and bus arbitration is resolved by extending this
logic and adding external logic that is common to all master
modules.
❑ Therefore several CPUs can form a very large system and each CPU
may have independent processors and/or a coprocessor attached
to it.
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Advantages
⮚ High system throughput can be achieved by having more than one CPU.
⮚ A failure in one module normally does not cause a breakdown of the
entire system and the faulty module can be easily detected and
replaced.
⮚ Each bus master may have a local bus to access dedicated memory or
I/O devices so that a greater degree of parallel processing can be
achieved.
⮚ The system can be expanded in a modular from a bus master module
can be added or removed without affecting the other modules in the
system. 23
Thank You