Presented by Dr. Md. Abir Hossain Dept. of ICT Mbstu

80286
Presented by
Dr. Md. Abir Hossain
Dept. of ICT
MBSTU
1
Intel 80286
Salient features of 80286
• High performance microprocessor with
memory management and protection
– 80286 is the first member of the family
of advanced microprocessors with built-
in/on-chip memory management and
protection abilities primarily designed for
multi-user/multitasking systems
• Available in 12.5MHz, 10MHz & 8MHz

clock frequencies
Salient features of 80286(cont…)
ØThe 80286 CPU, with its 24-bit address bus is

able to address 16MB of physical memory.
Ø1GB of virtual memory for each task

Microprocessor Data bus Address bus Memory size
width(Bit) width(Bit)
8086 16 20 1M
80186 16 20 1M
80286 16 24 16M
Salient features of 80286 (cont…)
Ø286 includes special instructions to support
operating system.
Øfor example, one instruction can
Øi) ends the current task
Øii) save its states
Øiii) switch to a new task
Øiv) load its states and
Øv) begin executing the new
task
Øhoused in 68-pin package
80286 Operating Modes
Intel 80286 has 2 operating modes:
Ø Real Address Mode :
Ø 80286 is just a fast 8086 --- up to 6
times faster
Ø All memory management and
protection mechanisms are disabled
Ø 286 is object code compatible with
8086
Ø Protected Virtual Address Mode
Ø 80286 works with all of its memory
management and protection
capabilities with the advanced
instruction set.
Ø it is source code compatible with 8086
Internal Block Diagram of
80286
EU
AU BIU
BIU EU IU
8085
8086 80286
Functional Block diagram 80286
Functional Parts
1. Address unit
2. Bus unit
3. Instruction unit
4. Execution unit
Address Unit (AU)
• Calculate the 20-bit physical addresses based on the 16-

bit contents of a segment register and 16-bit offset.
• 80286 addresses 1 Mbyte of physical memory.
• 80286 has 24 address pins
• In real addressing mode, pins A23-A20 are ignored and
A19-A0 are used.
• In protected virtual address mode, AU operates memory
management unit and utilizes all 24 address lines.
• Physical address computed by the address unit is
handed over to the BUS unit.
Bus Unit
• Performs all memory and I/O read and write

operations.
• Take care of communication between CPU and a
coprocessor.
• Transmit the physical address over address bus A0 –
A23.
• Prefetcher module in the bus unit performs this task
of prefetching.
• Bus controller controls the prefetcher module.
• Fetched instructions are arranged in a 6 – byte
prefetch queue.
Instruction Unit
• Receive arranged instructions from 6 byte

prefetch queue.
• Instruction decoder decodes up to 3

prefetched instruction and are latched them
onto a decoded instruction queue.
• Output of the decoding circuit drives a control

circuit in the Execution unit.
Execution unit (EU)
• EU executes the instructions received from the
decoded instruction queue sequentially.
• Contains a 16-bit ALU, an 8086 flag register, general
purpose registers, pointer registers, index registers
and
• Contains one additional 16-bit special register called
Machine status word (MSW) register --- lower 4
bits are only used.
• ALU is the heart of execution unit.
• After execution, ALU sends the result either over
data bus or back to the register bank.
Register organization of 80286
The 80286 CPU contains the same set of registers, as in

8086.
1. Eight 16-bit general purpose registers.
2. Four 16 bit segment registers.
3. Status and control register.
4. Instruction pointer.
Flag Registers
80286 Flag Registers
Input Output Privilege Level(IOPL)-D12,13
• IOPL is used in protected mode operation

to select the privilege level for I/O devices.
• If the current privilege level is higher or
more trusted than the IOPL, I/O executed
without hindrance.
• If the IOPL is lower than the current
privilege level, an interrupt occurs, causing
execution to suspend. Note that IPOL 00 is
the highest or more trusted; and IOPL 11
is the lowest or least trusted.
Nested task(NT) flag - D14
• When set(NT=1), it indicates that one
system task has invoked another through
a CALL instruction as opposed to a JMP.
• For multitasking this can be manipulated
to our advantage
Machine Status Word
• Consist of four flags. These are – PE, MP,

EM and TS
• LMSW & SMSW instruction are available

in the instruction set of 80286 to write and
read the MSW in real address mode.
Ø PE - Protection enable
Ø Protection enable flag places the 80286 in protected mode, if
set. This can only be cleared by resetting the CPU.
Ø MP – Monitor processor extension

Ø If set, flag allows WAIT instruction to generate a processor
extension not present in the exception.
Ø EM – Emulate processor extension flag,

Ø if set , causes a processor extension absent exception and
permits the emulation of processor extension by CPU.
Ø TS – Task switch
Ø if set this flag indicates the next instruction using extension
will generate exception 7, permitting the CPU to test whether
the current processor extension is for current task.
Additional Instructions of Intel 80286
Sl Instruction Purpose
no
1. CLTS Clear the task – switched bit
2. LDGT Load global descriptor table register
3. SGDT Store global descriptor table register
4. LIDT Load interrupt descriptor table register
5. SIDT Store interrupt descriptor table register
6. LLDT Load local descriptor table register
7. SLDT Store local descriptor table register
8. LMSW Load machine status register
9. SMSW Store machine status register
Sl Instruction Purpose
no
10. LAR Load access rights

11. LSL Load segment limit
12. SAR Store access right
13. ARPL Adjust requested privilege level
14. VERR Verify a read access
15. VERW Verify a write access

Ø CLTS
Ø The clear task – switched flag instruction clears the TS
(Task - switched) flag bit to a logic 0.
Ø LAR
Ø The load access rights Instruction reads the segment
descriptor and place a copy of the access rights byte
into a 16 bit register.
Ø LSL
Ø The load segment limit instruction Loads a user –
specified register with the segment limit.
Ø VERR
Ø The verify for read access instruction verifies that a
segment can de read.
Ø VERW
Ø The verify for write access instruction is used to verify
that a segment can be written.
Ø ARPL
Ø The Adjust request privilege level instruction is used to
test a selector so that the privilege level of the requested
selector is not violated.
28

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80286

• Available in 12.5MHz, 10MHz & 8MHz

ØThe 80286 CPU, with its 24-bit address bus is

Ø1GB of virtual memory for each task

• Calculate the 20-bit physical addresses based on the 16-

• Performs all memory and I/O read and write

• Receive arranged instructions from 6 byte

• Instruction decoder decodes up to 3

• Output of the decoding circuit drives a control

The 80286 CPU contains the same set of registers, as in

1. Eight 16-bit general purpose registers.

2. Four 16 bit segment registers.

3. Status and control register.

• IOPL is used in protected mode operation

• Consist of four flags. These are – PE, MP,

• LMSW & SMSW instruction are available

Ø MP – Monitor processor extension

Ø EM – Emulate processor extension flag,

10. LAR Load access rights

12. SAR Store access right

13. ARPL Adjust requested privilege level

14. VERR Verify a read access

15. VERW Verify a write access

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