Noida Institute of Engineering and

Technology, Greater Noida

Input / Output Unit

Unit: 5

Logic Design & Computer

Swarnima
Architecture (ACSAI 0302)
Assistant Professor
B Tech 3rd Sem NIET, Greater Noida

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 Evaluation scheme

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 Subject Syllabus
Course Contents / Syllabus
UNIT-I Introduction 8 Hours
Basics of Logic Design: Basic of number System, Boolean algebra, Half Adder and Full Adder, Half
Subtractor and Full Subtractor, Multiplexer, Encoder, Decoder.
Computer Organization and Architecture: Functional units of a digital system and their
interconnections, buses, bus architecture, types of buses, and bus arbitration and its types. Register, bus,
and memory transfer. Process or organization, general registers organization, stack organization, and
addressing modes.
UNIT-II ALU Unit 8 Hours
Arithmetic and logic unit: Look ahead carries adders. Multiplication: Signed operand multiplication,
Booth’s algorithm, and array multiplier. Division and logic operations. Floating-point arithmetic
operation, Arithmetic &logic unit design. IEEE Standard for Floating-Point Numbers.
UNIT-III Control Unit 8 hours
Control Unit: Instruction types, formats, instruction cycles and sub-cycles (fetch and execute, etc.),
micro-operations, execution of a complete instruction. Program Control, Reduced Instruction Set
Computer, Complex Instruction Set Computer, Pipelining. Hardwire and microprogrammed control,
Concept of horizontal and vertical microprogramming, Flynn's classification.

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 Subject Syllabus

Course Contents / Syllabus

UNIT-IV Memory Unit 8 hours
Memory: Basic concept and hierarchy, semiconductor RAM memories, 2D & 2 1/2D memory
organization. ROM memories. Cache memories: concept and design issues & performance address
mapping and replacement Auxiliary memories: magnetic disk, magnetic tape, and optical disks
Virtual memory: concept implementation, Memory Latency, Memory Bandwidth, Memory Seek
Time.
UNIT-V Input/Output 8 hours
Peripheral devices: I/O interface, I/O ports, Interrupts: interrupt hardware, types of interrupts and
exceptions. Modes of Data Transfer: Programmed I/O, interrupt initiated I/O and Direct Memory
Access, I/O channels and processors. Serial Communication: Synchronous &asynchronous
communication.

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 Subject Syllabus

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 Subject Syllabus
Course outcome: After completion of this course students will be able to:

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 Branch wise Applications
Computer Science:

Understanding of Logic Design and Computer Architecture is required

for:
• Understanding of Logic on computer
•Performance analysis of practical software
• Parallel Software and its execution
• High performance databases
• Modern Compilers and Code optimization
• High performance game programming

Other applications

• Bio-informatics, Data science using python, Web programming

For high performance computing, we require COA background.

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 Course Objective

• Discuss the basic concepts ,Logics and structure of computers.

• Understand concepts of register transfer logic and arithmetic
operations.
• Explain different types of addressing modes and memory
organization.
• Understand the concepts of memory system and Learn the different
types of memories to store data.
• Explain the various types of interrupts and modes of data transfer.

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 Course Outcomes

Course outcomes : After completion of this course students will be able to

CO 1 Understand the basic structure and operation of a digital K1, K2

computer system
CO 2 Analyze the design of arithmetic & logic unit and understand the K1, K4

fixed point and floating-point arithmetic operations.

CO 3 Implement control unit techniques and the concept of Pipelining K3

CO 4 Understand the hierarchical memory system, cache memories K2

and virtual memory.

CO 5 Understand different ways of communicating with I/O devices K2

and standard I/O interfaces.

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 Program Outcomes
• Program Outcomes are narrow statements that describe what the
students are expected to know and would be able to do upon the
graduation.

• These relate to the skills, knowledge, and behavior that students acquire
through the programmed.
1. Engineering knowledge
2. Problem analysis 9. Individual and team work
3. Design/development of solutions 10. Communication
4. Conduct investigations of complex 11. Project management and
problems finance
5. Modern tool usage 12. Life-long learning
6. The engineer and society
7. Environment and sustainability
8. Ethics

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 CO-PO Mapping

Logic Design & Computer Architecture

(ACSAI 0302)
PO PO PO
CO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 10 11 12
CO1 3 2 1 1 1 1 1 - 1 1 1 2
CO2 2 2 2 2 1 1 - 1 1 1 1 2
CO3 3 2 2 1 2 2 1 1 2 2 1 2
CO4 3 2 2 2 2 1 1 - 1 1 1 2
CO5 2 2 2 1 2 - 1 - 1 2 2 2

Average 2.6 2 1.8 1.4 1.6 1 0.8 0.4 1.2 1.4 1.2 2

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 Program Educational Objectives

PEO1: Solve real-time complex problems and adapt to technological

changes with the ability of lifelong learning.
PEO2: Work as data scientists, entrepreneurs, and bureaucrats for
the goodwill of the society and pursue higher education.
PEO3: Exhibit professional ethics and moral values with good
leadership qualities and effective interpersonal skills.

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 Result Analysis

Department Result Individual Result

Computer 100%
Organization
and Architecture

Renewable 98.57%
Energy
Resources

Universal 90.74%
Human Values

Introduction to 95.61%
Microprocessor

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 End Semester Question Paper Template

Question Paper
Template -100 Marks

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 Prerequisite and Recap

• Basic knowledge of Digital Logic Design

• ALU Unit
• Control Unit
• Memory unit

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 Brief Introduction about Subject

The Logic Design & Computer Architecture is one of the most important and
comprehensive subject that includes many foundational concepts and
knowledge used in design of a computer system. This subject provides in-depth
knowledge of internal working, structuring, and implementation of a computer
system.

The LDCA important topics include all the fundamental concepts such
as computer system functional units , processor micro architecture , program
instructions, instruction formats , addressing modes , instruction pipelining,
memory organization , instruction cycle, interrupts and other important related
topics.

Video link: https://www.youtube.com/watch?v=q6oiRtKTpX4

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 Content

Input/output
Peripheral devices
I/O interface & I/O ports
Interrupts: interrupt hardware, types of interrupts and exceptions.
Modes of Data Transfer:
Programmed I/O, interrupt initiated I/O
Direct Memory Access.,
I/O channels and processors.
Serial Communication: Synchronous & asynchronous communication
standard communication interfaces.

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 Course Objective

• Study the different ways of communicating with I/O devices and

standard I/O interfaces.

• Study of interrupts and exceptions, DMA, I/O channels and

processors,Serial Communication

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 Course Outcome

Understanding the different ways of communicating with I/O devices

and standard I/O interfaces.

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 CO-PO Mapping

Logic Design & Computer Architecture

(ACSAI 0302)

CO.K PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12

KCS-
502.5 2 2 2 1 2 1 1 1 1 2 2 2

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 CO- PSO Mapping

Logic Design & Computer Architecture

(ACSAI 0302)
CO.K PSO1 PSO2 PSO3 PSO4
KCS-502.2 2 3 3 1

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 Prerequisite and Recap

• Basics of Computer
• Control Unit

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 Peripheral devices
A peripheral is a device that can be attached to the computer processor.
• Devices are usually classified as input, output or backing
storage devices.
Peripheral devices can be external or internal.

• Examples of external peripherals

include mouse, keyboard, printer,
monitor, external Zip drive or scanner.

• Examples of internal peripherals

include CD-ROM drive, CD-R drive
or internal modem.

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 Peripheral devices

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 Peripheral devices

• Printers provide a permanent record on paper of computer

output data or text.
• There are three basic types of character printers:
daisywheel, dot matrix, and laser printers.
• The daisywheel printer contains a wheel with the characters
placed along the circumference. To print a character, the
wheel rotates to the proper position and an energized
magnet then presses the letter against the ribbon.
• The dot matrix printer contains a set of dots along the
printing mechanism.
• The laser printer uses a rotating photographic drum that is
used to imprint the character images. The pattern is then
transferred onto paper in the same manner as a copying
machine.
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 Input Output interface
Peripherals connected to a computer need special
communication links for interfacing them with the central
processing unit. The purpose of the communication link is to
resolve the differences that exist between the central computer
and each peripheral.
The major differences are:
1. Peripherals are electromechanical and electromagnetic
devices and their manner of operation is different from the
operation of the CPU and memory, which are electronic
devices. Therefore, a conversion of signal values may be
required.

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 Input Output interface

2. The data transfer rate of peripherals is usually slower than the

transfer rate of the CPU, and consequently, a synchronization
mechanism may be needed.
3. Data codes and formats in peripherals differ from the word format in
the CPU and memory.
4. The operating modes of peripherals are different from each other and
each must be controlled so as not to disturb the operation of other
peripherals connected to the CPU.
To resolve these differences, computer systems include special
hardware components between the CPU and peripherals to supervise
and synchronize all input and output transfers. These components are
called interface units because they interface between the processor
bus and the peripheral device.

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 Input Output bus and interface module

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 Input Output bus and interface module

Each interface decodes the address and control received from the
I/O bus, interprets them for the peripheral, and provides signals
for the peripheral controller. It also synchronizes the data flow
and supervises the transfer between peripheral and processor. Each
peripheral has its own controller that operates the particular
electromechanical device. for example, the printer controller
controls the paper motion, the print timing, and the selection of
printing characters.
Each interface attached to the I/0 bus contains an address decoder
that monitors the address lines.
The processor provides a function code in the control lines. The
function code is referred to as an IO command and is in essence
an instruction that is executed in the interface and its attached
peripheral unit.
There are four types of commands that an interface may receive.
They are classified as control, status, data output, and data input.
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 IO interface

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 IO interface

• In the first method, the computer has independent sets of

data, address, and control buses, one for accessing memory
and the other for I/O.
• This is done in computers that provide a separate I/O
processor (lOP) in addition to the central processing unit
(CPU).
• The purpose of the lOP is to provide an independent
pathway for the transfer of information between external
devices and internal memory.

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 Isolated versus Memory-Mapped I/O

• The distinction between a memory transfer and I/O transfer is

made through separate read and write lines.
• The I/O read and I/O write control lines are enabled during an
I/O transfer.
• The memory read and memory write control lines are
enabled during a memory transfer.
• This configuration isolates all I/O interface addresses from the
addresses assigned to memory and is referred to as the
isolated I/O method for assigning addresses in a common bus.

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 ISOLATED I/O

• When the CPU fetches and decodes the operation code of an

input or output instruction, it places the address associated
with the instruction into the common address lines.
• At the same time, it enables the I/O read (for input) or I/O
write (for output) control line.
• This informs the external components that are attached to
the common bus that the address in the address lines is for an
interface register and not for a memory word.

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 Memory-mapped

• In a memory-mapped l/0 organization there are no specific

input or output instructions. The CPU can manipulate l/0 data
residing in interface registers with the same instructions that
are used to manipulate memory words.

• The advantage is that the load and store instructions used for
reading and writing from memory can be used to input and
output data from l/0 registers. In a typical computer, there are
more memory-reference instructions than l/0 instructions.
With memory mapped l/0 all instructions that refer to memory
are also available for l/0.

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 IO INTERFACE

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 Asynchronous Data Transfer

• If the registers in the interface share a common clock with the CPU
registers, the transfer between the two units is said to be synchronous.
• In most cases, the internal timing in each unit is independent from the
other in that each uses its own private clock for internal registers.
• In that case, the two units are said to be asynchronous to each other.
• One way of achieving this is by means of a strobe pulse supplied by one
of the units to indicate to the other unit when the transfer has to occur.
• Another method commonly used is to accompany each data item being
transferred with a control signal that indicates the presence of data in the
bus.
• The unit receiving the data item responds with another control signal to
acknowledge receipt of the data.
• This type of agreement between two independent units is referred to as
handshaking .

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 Strobe control

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 Handshaking

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 Handshaking

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 Asynchronous serial transmission
A serial asynchronous data transmission technique used in many interactive terminals
employs special bits that are inserted at both ends of the character code. With this technique,
each character consists of three parts: a start bit, the character bits, and stop bits. The
convention is that the transmitter rests at the 1-state when no characters are transmitted. The
first bit, called the start bit, is always a 0 and is used to indicate the beginning of a character.
The last bit called the stop bit is always a 1.
A transmitted character can be detected by the receiver from knowledge of the transmission
rules:
1 . When a character is not being sent, the line is kept in the 1-state.
2. The initiation of a character transmission is detected from the start bit, which is always 0.
3. The character bits always follow the start bit.
4. After the last bit of the character is transmitted, a stop bit is detected when the line returns
to the 1-state for at least one bit time.

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 Asynchronous communication interface

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 Modes of Transfer

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 Programmed I/O
• Programmed I/O operations are the result of I/O instructions
written in the computer program.
• Each data item transfer is initiated by an instruction in the program.
Usually, the transfer is to and from a CPU register and peripheral.
• Other instructions are needed to transfer the data to and from CPU and
memory.
• In the programmed I/0 method, the CPU stays in a program loop until the
I/O unit indicates that it is ready for data transfer.
• It can be avoided by using an interrupt facility and special commands to
inform the interface to issue an interrupt request signal when the data are
available from the device.
• When the interface determines that the device is ready for data transfer, it
generates an interrupt request to the computer. Upon detecting the external
interrupt signal, the CPU momentarily stops the task it is processing,
branches to a service program to process the I/O transfer, and then returns
to the task it was originally performing.

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 DMA
• In direct memory access (DMA), the interface transfers data into and out
of the memory unit through the memory bus.
• When the transfer is made, the DMA requests memory cycles through the
memory bus.
• When the request is granted by the memory controller, the DMA transfers
the data directly into memory. The CPU merely delays its memory access
operation to allow the direct memory I/O transfer.

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 Example of Programmed I/O
• Transfer from an I/O device to memory requires the execution of
several instructions by the CPU, including an input instruction to transfer
the data from the device to the CPU and a store instruction to transfer the data
from the CPU to memory.
• When a byte of data is available, the device places it in the I/O bus and enables
its data valid line.
• The interface accepts the byte into its data register and enables the data accepted
line. The interface sets a bit in the status register that we will refer to as an F or
"flag" bit.
• The device can now disable the data valid line, but it will not transfer another
byte until the data accepted line is disabled by the interface.
• If the flag is equal to 1, the CPU reads the data from the data register. The
flag bit is then cleared to 0 by either the CPU or the interface, depending on
how the interface circuits are designed.
• Once the flag is cleared, the interface disables the data accepted line
and the device can then transfer the next data byte.

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 Modes of Transfer

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 Modes of Transfer

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 Interrupt-Initiated I/O
• While the CPU is running a program, it does not check the flag.
However, when the flag is set, the computer is momentarily interrupted
from proceeding with the current program.
• The CPU responds to the interrupt signal by storing the return address
from the program counter into a memory stack and then control
branches to a service routine that processes the required I/O transfer.
• The way that the processor chooses the branch address of the service
routine varies from one unit to another.

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 Interrupt & Exception
• In computer architecture, an interrupt is a signal to the processor
emitted by hardware or software indicating an event that needs
immediate attention.
• Interrupt is a signal which has highest priority from hardware or
software which processor should process its signal immediately.

TYPES OF INTERRUPTS
Interrupts have highest priority than other signals, there are many type
of interrupts but basic type of interrupts are -
• Hardware Interrupts: If the signal for the processor is from
external device or hardware is called hardware interrupts.

Example: from keyboard we will press the key to do some action this
pressing of key in keyboard will generate a signal which is given to the
processor to do action, such interrupts are called hardware interrupts.

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 Interrupt & Exception
Hardware interrupts can be classified into two types –

Maskable Interrupt: The hardware interrupts which can be

delayed when a much highest priority interrupt has occurred to the
processor.
Non Maskable Interrupt: The hardware which cannot be delayed
and should process by the processor immediately.

•Software Interrupts: Software interrupt can also divided in to two types

they are -
Normal Interrupts: the interrupts which are caused by the
software instructions are called software instructions.

Exception: unplanned interrupts while executing a program is

called Exception.

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 Interrupt & Exception
Based on address:
• Vectored Interrupt: In this type of interrupt, the interrupt address is known
to the processor. For example: TRAP.
• Non Vectored Interrupt: In this type of interrupt, the interrupt address is not
known to the processor so, the interrupt address needs to be sent externally by
the device to perform interrupts. For example: INTR.

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 Trap
•It is non-maskable edge and level triggered interrupt.

•TRAP has the highest priority and vector interrupt.

A trap is an exception in a user process.

•Edge and level triggered means that the TRAP must go high and remain
high until it is acknowledged.

There are two ways to clear TRAP interrupt.

1.By resetting microprocessor (External signal)
2.By giving a high TRAP ACKNOWLEDGE (Internal signal)

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 Interrupt

Interrupt service routine Interrupt Hardware

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 Priority Interrupt

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 Priority Interrupt

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 Priority Interrupt

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 Priority Interrupt

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 Input / Output Subsystem

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 Programmed I/O

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 Interrupt driven I/O

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 Interrupt driven I/O

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 Interrupt Control I/O

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 DMA

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 DMA

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 DMA

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 DMA

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 DMA

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 Serial Communication

Serial communication is a communication technique used in

telecommunications wherein data transfer occurs by transmitting data one
bit at a time in a sequential order over a computer bus or
a communication channel.
It is two types-
1.Synchronous communication 2. Asynchronous communication
Synchronous communication
In synchronous transmission, data moves in a completely paired approach,
in the form of chunks or frames.
Examples of Synchronous Transmission
Chat rooms, Video conferencing, Telephonic conversations
Face-to-face interactions

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 Serial Communication

Asynchronous Transmission
In asynchronous transmission, data moves in a half-paired
approach, 1 byte or 1 character at a time. It sends the data in a constant
current of bytes.

Examples of Asynchronous Transmission

Emails, Forums, Letters, Radios, Televisions

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 Synchronous Vs. Asynchronous

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 Faculty Video Links, You tube Courses
Details

You tube/other Video Links

• https://www.youtube.com/watch?v=Vr8wJdC8jCw
• https://www.youtube.com/watch?v=qgwmHnNsd6M
• https://www.youtube.com/watch?v=UnLww6bH6C4

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 Daily Quiz

• Write down three example of Input & output devices.

• Define I/O Ports.
• Write down full form of DMA.
• What do mean by Exception & TRAP ?
• Write down various types of interrupts

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 Weekly Assignment
 Discuss the various type of Interrupts and Exception in computer
organization with suitable examples.

 Write short notes on-

a) I/O Interface b) I/O channels & Processor

 Explain Modes of data transfer : Programmed I/O, Interrupt initiated

I/O.

 Explain the working of DMA controller with help of suitable diagrams.

 Discuss the Synchronous and Asynchronous communication with

suitable examples.

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 MCQ
1 To avoid loading during read operation, the device used is
a) latch b) flipflop c) buffer d) tristate buffer
2. The device that enables the microprocessor to read data from the
external devices is, a) printer b) joystick c) display d) reader
3. The controller is connected to the ____
a) Processor BUS b) System BUS c) External BUS
4. The DMA transfers are performed by a control circuit called as
5. The DMA controller has _______ registers
a) 4 b) 2 c) 3 d) 1
6. The INTR interrupt may be
a) Maskable b) nonmaskable
7. The INTR interrupt may be masked using the flag
a) direction flag b) overflow flag c) interrupt flag d) sign flag
Solution 1 d. 2b. 3 b. 4 DMA controller . 5 c 6 a 7 c

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 Old Question Papers

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 Old Question Papers

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 Expected Questions for University Exam

Explain the working of DMA controller with help of suitable

diagrams.

Write short notes on-

I/O Ports b) I/O Interface c) I/O channels & Processor

Discuss the Synchronous and Asynchronous communication with

suitable examples.

Discuss the various type of Interrupts and Exception in computer

organization with suitable examples.

Explain Modes of data transfer : Programmed I/O, Interrupt initiated

I/O.

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 Summary

In previous slides we discuss in details

Input/output Unit:
Peripheral devices
I/O interface & I/O ports
Interrupts: interrupt hardware, types of interrupts and
exceptions.
Modes of Data Transfer:
Programmed I/O, interrupt initiated I/O
Direct Memory Access.,
I/O channels and processors.
Serial Communication: Synchronous & asynchronous
communication , standard communication interfaces

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