Operational Amplifiers

o Introduction to Operational Amplifiers

o
Differential and Common-mode Operation
o Practical Op. Amp. Circuits
o DC Offset Parameters
o Frequency Parameters
Comparison of ideal and non-ideal Op-Amp
Non-ideal Op-Amp consideration
o ????
 Op-Amp Introduction
• Op‐amps are linear IC devices
with two input terminals, and
one output terminal. One input
is inverting (‐), and the other is
non-inverting (+).

• An op-amp typically consists

of:
• Input stage: Differential
amplifier of high input resistance
e.g., JFET pair.
• Amplification: two or more
differential amplifier stages or
common-emitter stage with
active load
• Output stage: Emitter follower
with low output resistance
 Operational Amplifier (Op-Amp)
• Very high differential gain +V cc

• Input 1
High input impedance +
• Low output impedance V o

•
V d
Output
Provide voltage changes 
(amplitude and polarity) Input 2
• Used in oscillator, filter and
instrumentation
R ~inf
in -V R ~0
cc out

• Accumulate a very high gain Vo  AdVd

by multiple stages
Ad : differenti al gain normally
very large, say 105
 Introduction to Operational Amplifiers
+Vcc

+Vcc Inverting
Input (-)
output
Non-
ii = 0
Inverting InvInput (+)
Input (-) -
v+ = v - Push-pull
Non Inverting + Emitter
output
Input (+) ii = 0 follower
R0= 0 at the
output
-Vcc -Vcc
Therefore Operational Amplifier has Differential Collector Output
(1) very high input impedance, R i= a Amplifier Constant Impedance
current very low
(or) ii = 0 Op. Amp.
Emitter source
(2) very high voltage gain Av = 105 input
Constant
(or) v+ = v- Impedance
current
Very high Amplifier
(3) very low output impedance R0 = 0 source
voltage
gain very
high
 IC Product
OFFSET
NULL
1 8 N.C. OUTPUT A 1 8 V+

-IN 2 7 V+ -IN A 2  7 OUTPUT B


+
+IN 3 + 6 OUTPUT +IN A 3  6 -IN B
OFFSET +
V 4 5 NULL V 4 5 +IN B

DIP-741 Dual op-amp 1458 device

347 IC Op-Amp
Single-ended input Operational Amplifiers

v-
v- v+
v+
vo
Vs vo
Vs
Inverting
input Non-Inverting
input
Phase of Vo is inverted Phase of Vo is not inverted
(=180degree phase-shifted) (=0degree phase-shifted)
 Distortion

+V =+5V cc

+5V
+
Vo
V d 0

5V

V =5V cc

The output voltage never excess the DC voltage

supply of the Op-Amp
 Common-Mode Operation
• Same voltage source is applied +
at both terminals
Ideally, two input are equally
V o

amplified. Output voltage is ideally 

zero due to differential voltage is
zero. Vi ~
Thus, unwanted signals (noise)
appearing at both input lines
are essentially cancelled by the diff-
amp and do not appear at the outputs Note for differential circuits:
Opposite inputs : highly amplified
• Practically, a small output Common inputs : slightly amplified
signal can still be measured  Common-Mode Rejection
 Common-Mode Rejection Ratio (CMRR)
Ad
Common  Mode Re jection Ratio  CMRR 
Ac
Ad
Common  Mode Re jection Ratio in dB  CMRR dB  20log (dB)
Ac

Vo can be found from CMRR as follows if A d,Vc,and Vd are known

 AV   Vc 
Vo  AdVd  AcVc  AdVd  1  c c   AdVd  1  

 A V
d d  CMRR  Vd

Note:
When Ad >> Ac or CMRR 
ÞVo = AdVd

Ideally, a diff‐amp provides a very high gain for desired

signals (single‐ended or differential), and zero gain for
common‐mode signals
 Differential and Common-mode Operation
• Differential and Common-mode input
voltages
v- Differenti al input voltage  Vd  Vi1  Vi 2
Vi1  Vi 2
v+ Common  mod e input voltage  V c 
2
Vi2 vo Output voltage  Vo  AdVd  AcVc
V
Vi1 Differenti al  mod e gain  Ad  o (if Vc  0) &
Vd
V
Common  mod e gain  Ac  o (if Vd  0)
Vc
Vo is a function of both common-mode
inputs and differential-mode inputs

Example:
Let Vi1  1V and Vi 2  2V
Vd  Vi1  Vi 2  1  (2)  3V
Vi1  Vi 2  1  (2)
Vc    0.5V
2 2
Vo  AdVd  AcVc  Ad (3)  Ac (0.5)
Ad & Ac will be found from circuit configurat ions
 CMRR Example
What is the CMRR?

100V + 100V +
80600V 60700V
20V  40V 

Solution :

Vd 1  100  20  80V Vd 2  100  40  60V

(1) (2)
100  20 100  40
Vc1   60V Vc 2   70V
2 2
From (1) Vo  80 Ad  60 Ac  80600V
From (2) Vo  60 Ad  70 Ac  60700V
 Ad  1000 and Ac  10  CMRR  20 log(1000 / 10)  40dB
NB: This method Does Not work! Why?
Example: Given that when Vi1=0.5V , Vi2=-0.5V we get Vo=8V, and when Vi1=1mV ,
Vi2=1mV we get Vo=12mV. Find Ad , Ac , CMRR(dB) of the given Op. Amp. amplifier

1. In Differential  mod e we put

v- Vi1  0.5mV and Vi2  0.5mV  and get Vo  8V
v+  Vd  Vi1  Vi2  0.5mV  ( 0.5V )  1mV
8V
Vi2 0.5mV   0.5mV 
and Vc   0mV
0.5mV 2
Vi1 Vo  AdVd  AcVc  8V  Ad  1mV  Ac  0
-0.5mV 8V
vo=AdVd+AcVc  Ad   8000
1mV

2. In Common  mod e we put

v- Vi1  1mV and Vi2  1mV  and get Vo  12mV
v+ 12mV  Vd  Vi1  Vi2  1mV  1mV  0mV
Vi2
Vi1  Vi2 1mV  1mV
1mV and Vc    1mV
2 2
Vi1 Vo  AdVd  AcVc  12V  Ad  0mV  Ac  1mV
1mV
vo=AdVd+AcVc  Ac 
12mV
 12
1mV
A 8000
Common  Mode Re jection Ratio  CMRR  d   666.7
Ac 12
Common  Mode Re jection Ratio in dB  CMRR dB  20log 666.7  56.48 dB
Example: The CMRR of an Op. Amp. is 56.48dB. It is found that when V i1=0.5V ,
Vi2=-0.5V we get Vo=8V, Find Ac , and what will be the value of V o if Vi1=Vi2=1mV
of this Op. Amp.

v- 1. In Differential  mod e we put

Vi1  0.5mV and Vi2  0.5mV  and get Vo  8V
v+ 8V
Vi2  Vd  Vi1  Vi2  0.5mV  ( 0.5V )  1mV
0.5mV 0.5mV   0.5mV 
and Vc   0mV
Vi1 2
Vo  AdVd  AcVc  8V  Ad  1mV  Ac  0
-0.5mV
vo=AdVd+AcVc 8V
 Ad   8000
1mV

Ad 56.4
56.48dB  20log CMRR  CMRR   10 20  666.7
Ac
Ad 8000
Ac    12
666.7 666.7
 Vc  12
Vo  AdVd  1    8000  1mV  1  
  12mV

CMRR  Vd   666.7  1mV 

 Op-Amp Properties
(1) Infinite Open Loop gain V1
- +
The gain without feedback Vo
- Equal to differential gain
- Zero common-mode gain
V2 
- Pratically, Ad = 20,000 to 200,000
(2) Infinite Input impedance
i1~0 +
- Input current ii ~0A Vo
- T- in high-grade op-amp i2~0 
- m-A input current in low-grade op-
amp
(3) Zero Output Impedance Rout
- act as perfect internal voltage Vo' +
source Rload
- No internal resistance
- Output impedance in series with
Rload
load Vload  Vo
- Reducing output voltage to the load Rload  Rout
- Practically, Rout ~ 20-100 
 Frequency-Gain Relation
• Ideally, signals are amplified
from DC to the highest AC 20log(0.707)=3dB
frequency
• Practically, bandwidth is
limited
• 741 family op-amp have an
limit bandwidth of few KHz.
• Unity Gain frequency f1: the gain at
unity
• Cutoff frequency fc: the gain drop
by 3dB from dc gain Ad

GB Product : f1 = Ad fc
 GB Product
Example: Determine the cutoff frequency of an op-amp having a unit gain
frequency f1 = 10 MHz and voltage differential gain Ad = 20V/mV

Sol:
Since f1 = 10 MHz
By using GB production equation
f 1 = Ad f c
fc = f1 / Ad = 10 MHz / 20 V/mV
= 10  106 / 20  103
= 500 Hz
 Ideal Vs Practical Op-Amp
Ideal Practical Ideal op-amp
+ AVin
Open Loop gain A  105
Vin ~ Vout
Bandwidth BW  10-100Hz  Zout=0

Input Impedance Zin  >1M

Output Impedance Zout 0 10-100  Practical op-amp
Output Voltage Vout Depends only Depends slightly +
on Vd = on average input Zin Zout
(V+V) Vc = (V++V)/2 Vin Vout
Common-Mode ~
Differential
mode signal signal  AVin
CMRR  10-100dB
(drops when f
increases)
 Analysis Method: Ideal Op-Amp
Two ideal Op-Amp Properties:
(1) The voltage between V+ and V is zero V+ = V
(2) The current into both V+ and V terminals is zero

For ideal Op-Amp circuit: Remove the op-amp from the circuit and
draw two circuits (one for the + and one for the – input terminals of
the op amp). The output acts like a new source. We can replace it
by a source with a voltage equal to Vout.
(3) Write the Kirchhoff node equation at the non-inverting
terminal V+
(4) Write the Kirchhoff node equation at the inverting terminal V
(5) Set V+ = V and solve for the desired closed-loop gain
Warnings for Ideal Op-Amp
Analysis Method: Non-Ideal Op-Amp
(Inverting Amplifier)
Rf Practical op-amp
Ra +
 Zin Zout
V o Vin
~
Vout
Vin ~ +  AVin

 Equivalent Circuit
Rf 3 categories are considered
Ra  Close-Loop Voltage Gain
V in   Input impedance
 R
V R V o  Output impedance
+ +
 -AV
 Analysis Method: Non-Ideal Op-Amp
Close-Loop Gain
Applied KCL at V– terminal,
Rf
Vin  V  V Vo  V
  0 Ra
Ra R Rf V in 
R R V
By using the open loop gain, V o

+ +
 -AV
Vo   AV
 Vin Vo V V V
  o  o  o 0 Ra Rf
Ra ARa AR R f AR f
V in V o
 Vin R R f  Ra R f  Ra R  ARa R
 Vo V R
Ra ARa R R f
The Close-Loop Gain, Av
Vo  AR R f
Av  
Vin R R f  Ra R f  Ra R  ARa R
 Rf
When the open loop gain is very large, the above equation become: Av ~
Ra
Note : The close-loop gain now reduces to the same form as an ideal case
 Analysis Method: Non-Ideal Op-Amp
Input Impedance
Rf
Input Impedance can be regarded as, Ra
Rin  Ra  R // R V
in

V R
R V
o
where R is the equivalent impedance + +
of the red box circuit, that is  -AV
V
R  R'
if
However, with the below circuit,
V  ( AV )  i f ( R f  Ro ) if Rf

V R f  Ro R
 R  
if 1 A V
+
 -AV
 Analysis Method: Non-Ideal Op-Amp
Input Impedance
Finally, we find the input impedance as,
1
1 1 A  R ( R f  Ro )
Rin  Ra      Rin  Ra 
R
  R f  R 
o R f  Ro  (1  A) R
Since, R  R  (1  A) R , Rin become,
f o 

( R f  Ro )
Rin ~ Ra 
(1  A)
Again with R f  Ro  (1  A)
Rin ~ Ra

Note: The op-amp can provide an impedance isolated from

input to output
 Analysis Method: Non-Ideal Op-Amp
Output Impedance
Only source-free output impedance would be considered,
i.e. Vi is assumed to be 0
Rf
Firstly, with figure (a), Ra
V 
Ra // R
Vo  V 
Ra R
Vo R R io
R f  Ra // R Ra R f  Ra R  R f R V
V
o
+
By using KCL, io = i1+ i2  -AV
Vo V  ( AV )
io   o
R f  Ra // R f Ro
By substitute the equation from Fig. (a),
The output impedance, Rout is
V
Rf i2 R i1
Vo Ro ( Ra R f  Ra R  R f R )
 V V
io (1  Ro )( Ra R f  Ra R  R f R )  (1  A) Ra R +
Ra R  -AV
R and A comparably large,
Ro ( Ra  R f )
Rout ~
ARa (a) (b)
741 Operational Amplifier
741 operational amplifier
 741 operational amplifier
• What is inside the op-amp?

• Basically we may divide an op-amp into three

main stages:
– Main functional parts
• 1. Input stage
• 2. Second stage (gain stage)
• 3. Output stage

– Other parts
• • Bias circuit
• • Short-circuit protection circuit
The bias circuit in 741 Op-Amp
The bias circuit in 741 Op-Amp
Short-circuit protection in 741 Op-Amp
Input stage in 741 Op-Amp
 Input stage in 741 Op-Amp
• Q1 and Q2 are emitter followers, providing high input
resistance.
• Q3 and Q4 serve as differential amplifier, providing high
CMRR.
• Q5, Q6, Q7 and R1, R2, R3 provide the load (active
load) for the differential amplifier.
This loading circuit also provides a single-ended output
for the next stage.
• Q3 and Q4 also serve as DC level shifter.
Q3 and Q4 are pnp transistors, hence protect the input
stage Q1 and Q2 against emitter-base junction
breakdown, since the emitter base junction of npn may
break down at about 7V of reverse bias. Usually, pnp has
emitter-base breakdown around 50 V!!
Second stage (gain stage) in 741
 Second stage (gain stage) in 741
• Q16 is an emitter follower, providing high input
resistance for the stage so as to minimize its loading
effect.
• Q17 is a common-emitter amplifier, loaded by Q13B.
• Q13B is a current mirror and serves as active load.
• The gain is
GAINsecond stage ≈ gm,17 ro,13B
• Note the capacitor Cc. This is called internal
compensation cap and is used for maintaining stability in
when the op-amp is used in a feedback configuration.
• We’ll revisit this issue later when we study feedback and
stability.
Output stage in 741
 Output stage in 741
• Provides low output resistance.
• Class AB output stage provided by Q14 and Q20
as complementary push-pull.
• Q19 and Q18 maintain a VBE drop to smooth
out the crossover distortion, as in the class AB
amplifier.
Op‐Amp Parameters
 Op‐Amp Parameters
• Input Offset Voltage, VOS is the difference in the voltage
between the inputs that is necessary to make Vout(error)=0.
– Vout(error) is caused by a slight mismatch of VBE1 and VBE2.
– Typical values of VOS are ≤ 2 mV.
• Input Offset Voltage Drift specifies how VOS changes with
temperature. Typically a few μV/oC.
• Input Bias Current is the dc current required by the
inputs of the amplifier to properly operate the first stage.
By definition, it is the average of the two input bias
currents, IBIAS = (I1 + I2)/2.
 Op‐Amp Parameters
• Differential Input Impedance is the total resistance
between the inverting and non‐inverting inputs.
• Common‐mode Input Impedance is the resistance
between each input and ground.
• Input Offset Current is the difference of the input bias
currents: IOS = |I1 ‐ I2|, and VOS = IOSRin(CM). Typically in nA
range.
• Output Impedance is the resistance viewed from the
output terminals.
• Open‐Loop Voltage Gain, Ad or Aol, is the gain of the op‐
amp without any external feedback connections.
 Op‐Amp Parameters
• Common‐mode Rejection Ratio for op‐amp is defined as
CMRR = Adm/Acm or 20log (Adm/Acm) in dB.
• Slew Rate is the maximum rate of change of the output
voltage in response to a step input voltage.
Slew rate = Δvout/Δt, where Δvout = +Vmax ‐ (‐Vmax).
The units for slew rate is V/μs.
• Frequency Response is the change in amplifier gain
versus frequency and is limited by internal junction
• capacitances.
• Other features include short circuit protection, no latchup
and input offset nulling.
 DC Offset: Input offset current
Op. Amp. Input offset current I IO is actually is not zero but very small and
equal to (IIB)+ - (IIB)- which are flowing at corresponding input terminals
Due to this Op. Amp. Input offset currents depending upon circuit
connections, there is an output voltage V o even if the two inputs are grounded.
Rf Rf
-
R1 - (IIB) R1 R1
(IIB)

RC vo RC vo
(IIB)+
Thevenin’s +
equivalent (IIB) RC

From differenti al amplifier analysis ,

R1
R   R  
+ 
Vo   f  (IIB  

)R1   1  f  (IIB )RC 
(IIB)
- -
(IIB) R1  R1   R1 
R1
DC

R
- if R1  RC , and if 1  f then
R1
R 
Norton's Thevenin’s R

Vo   f R1  IIB
 
 IIB Rf  IIO
 1
equivalent equivalent 
where input offset current IIO  IIB 
 IIB  
 DC Offset: Input offset voltage
Op. Amp. Input offset voltage V i is actually is not zero but very small and
equal to VIO which appears across the input terminals
Rf If input currents assume zero VRC  0  V   VIO
R1
From non  inverting amplifier analysis ,
RC vo  R 
Vo   1  f VIO 
(VIO)  R1 

Due to both Op. Amp. Input offset voltage V IO and Op. Amp. Input offset
current IIO appearing at the input terminals of the Op. Amp, V o will appears as
follows even if external input voltage sources are grounded (equals zero)
 R 
Vo  Rf  IIO  if VIO  0 and Vo   1  f  VIO  if IIO  0
 R1 
 R 
if VIO  0  IIO from Superposition theorem, Vo  Rf  IIO   1  f  VIO
 R1 
 DC Offset: Average bias current
Op. Amp. Average bias current I IB is sometimes given in IC data. It is the
average of (IIB)+ and (IIB)-

Rf

R1 -
(IIB)

RC (IIB)+ vo

(IIB)+ and (IIB)- can be found from IIB and IIO as follows:
 
IIB  IIB
IIB 
2


and sin ce IIO  IIB 
 IIB 

 IIB  

IIO  IIB 
 IIB


IIB 

 IIB


2IIB  
 IIB
 2  2 2 2

 IIB  

IIO  IIB 
 IIB


IIB 

 IIB


2IIB  
 IIB
 2  2 2 2
Example: (a) Calculate the Vo of the following Op. Amp. Amplifier when V in = 0
The Op. Amp data is Input offset voltage VIO=4mV, Input offset current IIO=150nA.
(b) find (IIB)+ and (IIB)- if Average offset current is given by IIB=900nA.

R1 5k Rf 500k
(Vin)
RC 5k vo

 R 
( a) Vo  Rf  IIO  if VIO  0 and Vo   1  f  VIO  if IIO  0
 R1 
if VIO  0  IIO from Superposition theorem,
 R   500k 
Vo  Rf  IIO   1  f  VIO  500k  150nA   1   4mV  479mV
 R1   5k 

 I   150nA 

(b) IIB   IIB  IO    900nA    975nA
 2   2 
 I   150nA 

IIB   IIB  IO    900nA    825nA
 2   2 
Input Offset Voltage Compensation
 Frequency Parameters

Gain
Av Voltage follower
Gain-BW product = constant
20
BW

10
Vo=Vin
1 Vin
f
@fmax Gain=AV=1
50kHz 100kHz 1000kHz
ft
fmax=BW=ft
Frequency Parameters
 Frequency Parameters
• Op‐Amp Bandwidth
– Open‐loop bandwidth: BWol = fc(ol)
– Closed‐loop critical frequency:

f = f (1 + KA
c(cl) c(ol) ol(mid) )
– Since fc(cl) = BWcl , the closed‐loop bandwidth is:
BWcl = BWol(1 + KAol(mid))
– Gain Bandwidth Product (A.BW) is a constant as long
as the roll‐off rate is fixed:
Aclfc(cl) = Aolfc(ol) = unity‐gain bandwidth
Frequency Parameters
Frequency Parameters
Slew Rate (SR)
Maximum rate at which amplifier output can change in microsecond (ms)
Vo
SR  (V / s)
t
Vo=Vin

V
Vin
Gain=AV=1

t

Maximum frequency (f)

Maximum frequency that an op. amp. May operate at depends on both the
Bandwidth (BW) and the Slew Rate (SR) parameters of the op. amp.

dv o
sin    (when  very small)  vo (t)  K sin 2ft   K 2ft    2fK (V / s)
dt
to have no distortion at the output , rate of change must be less than Slew Rate
SR
2fK (V / s)  SR  K  SR    2f 
K
Example: Determine the maximum frequency that can be used for the following
circuit, Op. Amp. Slew Rate is 0.5V/ms. If the input frequency is 300krad, find
output will be distorted or not.

10k 240k

(Vinp=0.02V, vo
=300x103)

Vo R 240k
Av   f   Vo p
 24  Vin p  24  0.02V  0.48V  K
Vin Ri 10k
SR 0.5V / s 6  1.1  10 6
   1.1  10 rad / s  max f    175kHz
K 0.48V 2 2
3 in 300  10 3
in  300  10  fin    47.75kHz  175kHz  fmax
2 2
 output wave will not be distorted
Phase Compensation
 Compensating Circuits
• Compensation is used to either eliminate openloop roll‐
off rates greater than ‐20 dB/dec or extend the ‐20
dB/dec rate to a lower gain.

• Two basic methods of compensation for IC opamps:

internal and external.

• In either case an RC series circuit is added so that its

critical frequency is less than the dominant (i.e. lowest) fc
of the internal lag circuits of the op‐amp.
 Op-Amp Compensation
• Some op‐amps (e.g. 741) are fully compensated
internally, i.e., their ‐20 dB/dec slope is extended all the
way down to unity gain. Hence, they are unconditionally
stable.

• A disadvantage of fully compensated op‐amps is that the

bandwidth and slew rate are reduced.

• Many op‐amps (e.g. LM101A) have provisions for

external compensation with a small capacitor. This
allows for optimum performance.
 Negative Feedback
• Since the open‐loop gain of the op‐amp is very high, an
extremely small input voltage (such as VOS) would drive
the op‐amp into saturation.
• By feeding a portion of the output voltage to the inverting
input of the op‐amp (negative feedback), the closed‐loop
voltage gain (Acl) can be reduced and controlled (i.e.
stable) for linear operations.
– Amplifiers with negative feedback depend less and less on the
open-loop gain and finally depend only on the properties of the
values of the components in the feedback network.
– The system gives up excessive gain to improve predictability
and reliability.
• Negative feedback also provides for control of Zin, Zout
and the amplifier’s bandwidth.
Negative Feedback Example
Bias Current Compensation
 Positive Feedback & Stability
• Positive feedback, where the output signal being fed
back is in‐phase to the input, will cause the amplifier to
oscillate when the loop gain, AolK = 1 (K: feedback gain).
• Phase margin, θpm (or PM), is the amount of additional
phase shift required to make the total phase shift around
the feedback loop 360o.
• To ensure stability for all midrange frequencies, an Op-
Amp must be operated with an Acl such that the roll‐off
rate beginning at fc is = ‐20 dB/decade.
• Gain margin GM is the amount of additional gain
required to make the total gain around the feedback loop
equals 1 when the phase shift is 360o. Usually given in
dB.
Positive Feedback & Stability
Conventional Op-Amp
Circuits
 Inverting/Noninverting Amplifier

INVERTING AMPLIFIER

v   v  0
Vi  v Vi v V V
 Ia   and IF   o  o
Ra Ra RF RF
Vi  Vo V R
Ii  0  Ia  IF or   AV  O   F
Ra RF Vi Ra
Notice: The closed-loop gain Vo/Vin is dependent upon
the ratio of two resistors, and is independent of the open-
NON-INVERTING AMPLIFIER loop gain. This is caused by the use of feedback output
voltage to subtract from the input voltage.

Vo  Ra
v   v   Vi
Ra  RF
Vo Ra  RF R
  1 F
Vi Ra Ra
 v+ v+
vi + v
i +
vo R v o
v-

1
R 2 v-


Ra Rf R
a R f

Noninverting amplifier Noninverting input with voltage divider

v+ v+
vi + vi +
vo R1 vo
v- R2 v-



Rf Rf
Less than unity gain
Voltage follower
DIFFERENTIAL AMPLIFIER

R4 V v
v  v  Vin1 and I1  Ia  in2  and
R3  R4 R1
v  Vout V  v v V
I2  IF  But Ii  0 I1  I2 in2    out
R2 R1 R2
substituting for v we have
 R2  R4  R 
Vout  Vin1  1     Vin2  2 
 R1  R3  R4   R1 
 INVERTING/NONINVERTING SUMMING AMPLIFIER
1) Kirchhoff node equation at V  : V   0;
Ra R2 R1
v  v  Vo but v  V1  V2 V v V
Ra  RF R1  R2 R1  R2 2) Ia  a   a
Ra Ra
V1 RR V RR  Ra  Vb  v Vb V v V
or v   1 2  2  1 2  Vo  
 and Ib   and Ic  c   c
R1 R1  R2 R2 R1  R2  Ra  RF  Rb Rb Rc Rc
R1R2  RF   V1 V2  3) Kirchhoff node equation at V  :
 Vo   1      
R1  R2  Ra   R1 R2   Vo V V V
 IF  Ia  Ib  Ic  a  b  c
RF Ra Rb Rc
4) Setting V   V – yields
RF
V V V 
VO  RF  a  b  c 
 Ra Rb Rc 
Ra
c V
v- vo Generalize : Vo   R f 
j
R1 v+ j a R j
V1
R2 RF IF
V2 R a Ia
Va
R b Ib
NON-INVERTING SUMMER Vb
R c Ic v- vo
Vc v+

INVERTING SUMMER
DIFFERENTIAL AMPLIFIER
DIFFERENTIAL AMPLIFIER
DIFFERENTIAL AMPLIFIER
DIFFERENTIAL AMPLIFIER
DIFFERENTIAL AMPLIFIER
DIFFERENTIAL AMPLIFIER
 OP-AMP DIFFERENTIATOR & INTEGRATOR
Now replace resistors Ra and Rf by complex Zf
components Za and Zf, respectively, Za
therefore 
Zf
Vo  Vin V
o
Za V ~in +
Supposing
(i) The feedback1 component is a capacitor C,
i.e., Z f  jC

(ii) The input component is a resistor R, Za = R C

Therefore, the closed-loop gain (Vo/Vin) become: R
1 
vo (t ) 
RC  vi (t )dt
V o
V ~in +
where
vi (t )  Vi e jt

What happens if Za = 1/jC whereas, Zf = R?

Inverting differentiator
 OP-AMP DIFFERENTIATOR & INTEGRATOR
OP-AMP DIFFERENTIATOR
R IR
v   v   0  vc  X
C ic
0-Y dvc dX
X  IR  Ic  C C
v- R dt dt
vc Y
v+ dX
 Y  RC  Y  differential of X
dt

This is the differentiator

(theoretically).
OP-AMP INTEGRATOR In practice, this circuit won’t work!!!
-
C ic
v   v   0  vR  X
R iR vc X 1 1 X
X
v- R
 IR  ic but vc  0  Y 
C
ic dt 
C  R
dt
Y 1
v+ Y  
CR 
X dt  Y  integral of X
 Op-Amp Integrator
Example:
C 0.01F
(a) Determine the rate of change +5V R
of the output voltage. 0 
100s
V
i
10 k
V
o
(b) Draw the output waveform. +
Vo(max)=10 V
Solution:
(a) Rate of change of the output voltage
Vo V 5V +5V
 i 
t RC (10 k)(0.01 F)
 50 mV/s
0 V i
0
(b) In 100 s, the voltage decrease -5V

Vo  (50 mV/s)(100μs)  5V

-10V V o
 Op-Amp Differentiator

R
C
0 
to t1 t2 V
i V
o 0
+

to t1 t2

 dV 
vo   i  RC
 dt 
Problem with ideal differentiator

Ideal Real

Circuits will always have some kind of input resistance,

even if it is just the 50 ohms or less from the function generator.
Analysis of real differentiator

1
Z in  Rin 
j Cin
Vout Zf Rf j R f Cin
  
Vin Z in Rin 
1 j RinCin  1
j Cin
Low Frequencies High Frequencies

Vout Vout Rf
  j R f Cin 
Vin Vin Rin
ideal differentiator inverting amplifier
Comparison of ideal and non-ideal

Both differentiate in sloped region.

Both curves are idealized, real output is less well behaved.
A real differentiator works at frequencies below wc=1/RinCin
Problem with ideal integrator (1)

No DC offset.
Works OK.
Problem with ideal integrator (2)

With DC offset.
Saturates immediately.
What is the integration of a constant?
Miller (non-ideal) Integrator

• If we add a resistor to the feedback path,

we get a device that behaves better, but
does not integrate at all frequencies.
 Behavior of Miller integrator

Low Frequencies High Frequencies

Vout Zf Rf Vout Zf 1
   
Vin Z in Rin Vin Z in jRinCf
inverting amplifier ideal integrator

The influence of the capacitor dominates at higher frequencies. Therefore, it

acts as an integrator at higher frequencies, where it also tends to attenuate
(make less) the signal.
 Analysis of Miller integrator
I
1
Rf 
j C f Rf
Zf  
Rf 
1 j R f C f  1
j C f
Rf
Vout Zf j R f C f  1 Rf
  
Vin Z in Rin j Rin R f C f  Rin
Low Frequencies High Frequencies

Vout Rf Vout 1
 
Vin Rin Vin j RinC f
inverting amplifier ideal integrator
Comparison of ideal and non-ideal

Both integrate in sloped region.

Both curves are idealized, real output is less well behaved.
A real integrator works at frequencies above wc=1/RfCf
Problem solved with Miller integrator

With DC offset.
Still integrates fine.
 Why use a Miller integrator?
• Would the ideal integrator work on a signal with no
DC offset?
• Is there such a thing as a perfect signal in real life?
– noise will always be present
– ideal integrator will integrate the noise
• Therefore, we use the Miller integrator for real
circuits.
• Miller integrators work as integrators at w > wc where
wc=1/RfCf
 Comparison
Differentiation Integration
original signal v(t)=Asin(t) v(t)=Asin(t)

mathematically dv(t)/dt = Acos(t) v(t)dt = -(A/cos(t)

mathematical +90 (sine to cosine) -90 (sine to –cosine)
phase shift
mathematical  1/
amplitude change
H(j H(jjRC H(jjRC = j/RC

electronic phase -90 (-j) +90 (+j)

shift
electronic RC RC
amplitude change

 The op amp circuit will invert the signal and multiply the
mathematical amplitude by RC (differentiator) or 1/RC (integrator)
 Examples
Find Vo of the following Op. Amp. circuits
RF
IR1  ii  0  v  v  V1
Ra Vo  Ra
But V1 
v- vo Ra  RF
R1 v+
Vo R  RF  R 
V1
RL   a  Vo  Va  1  F 
Va Ra  Ra 

v- vo There is no current in both resistors

R1 v+
V1  V1  v  v  Vo

Ra RF
Vo  Ra V  R2
v   v  1
Ra  RF R1  R2

R1
v- vo R2  R 
v+  Vo  V1   1  F 
V1 R1  R2  Ra 
R2
Find Vo of the followings Op. Amp. circuits

RF
There is no current in RF
v- vo V1  R2
R1  v  Vo  v 
V1
v+ R1  R2
R2 R2
 Vo  V1
R1  R2

Find IL of the followings Op. Amp. circuits

RF

There is no current in RF
v- vo V  R2
R1 v+  v   Vo  v   1
V1 R1  R2
R2 IL RL
R2 V V R2
Vo  V1  IL  o  1 
R1  R2 RL RL R1  R2
 Input resistance of Op. Amp. amplifiers

Inverting amplifiers Ri
RF

Ra There is no current in R1
Va
Rb v- vo  v  v  0
Vb v+ Then Rin (at Va )  Ra
R1 Also Rin (at Vb )  Rb

Non-inverting amplifiers Ri Input reistance at v   (open)

RF If int ernal R of V2 & V3  0
Ra Then Rin (at V1 )  R1  R2//R3  
v- vo Also if int ernal R of V1 & V3  0
v+
V1
R1
Rin (at V2 )  R2  R1//R3  
R2
V2 Also if int ernal R of V2 & V1  0
V3 R3
Rin (at V3 )  R3  R1//R2  
Design of Multiple-Input Op-Amp
Va RF
Ra
Vb
Rb
Vm
Rm
Ry Vo
R1
V1
R2 Multiple-Input Operational Amplifier circuit
V2
Rn Rx
Vn

To derive a general design table for given V o of Multiple-Input Op.

Amp. Circuit:-
1. Find V- from the input voltages Va---Vm
2. Find V+ from the input voltages Va---Vn
3. Equate V+ and V- and find the Vo
4. Make equal dc path resistance at both input terminals of Op. Amp.
5. Assign coefficient and make design table
 Design of Multiple-Input Op-Amp
1. Find V- from the input voltages Va---Vm
Va RF
Ra
Vb
Rb
Vm
Rm
Ry Vo

v  v  vb  v  v  v  vo  v  0  v 
KCL at v  is  a   ....... m   0
Ra Rb Rm RF RY
  v v v v
v   1  1  ......... 1  1  1   a  b  ....... m  o
 Ra Rb Rm RF RY  Ra Rb Rm RF
 1 1   1 1  v a vb vm vo
v      v 
       ....... 
 Ra // ....// RY RF   RA RF  Ra Rb Rm RF
 v a vb vm vo  RARF   v a vb vm  RARF  v R
 v      .......         .......   o A
 Ra Rb Rm RF  RA  RF   Ra Rb Rm  RA  RF  RA  RF
 Design of Multiple-Input Op-Amp
2. Find V+ from the input voltages V1---Vn

R1
V1 V+
R2
V2 Rx
Vn
Rn
v v v v v v v
KCL at v  is   1   2  .......  n    0
R1 R2 Rn RX
 1 1 1 1  v1 v2 vn
v     .........     .......
 R1 R2 Rn RX  R1 R2 Rn
 1  v1 v2 vn
v   
   .......
 R1 // R2 // .............Rn // RX  R1 R2 Rn
v v v 
 v    1  2  ....... n R1 // R2 // ....Rn // RX 
 R1 R2 Rn 
 Design of Multiple-Input Op-Amp
3. Equate V+ and V- and find the Vo
v  v
 v1 v2 vn  v v v  R R  v R
   ....... R1 // R2 // ....Rn // RX    a  b  ....... m  A F  o A
R  R Rm  RA  RF  R R
 1 R2 Rn   a Rb  A F
 v1 vn   v a vm  RARF  v R
  ... R1 // ....Rn // RX     ...   o A

 R1 Rn   Ra Rm  RA  RF  R R
 A F

 RF   v1 vn   v a vm  RARF 
vo   1 
    ... R1 // ....Rn // RX     ...  
 RA   R1 Rn   Ra Rm  RA  RF 

 v1 vn  R   v a vm  RARF RA  RF 
   ...  1  F R1 // ....Rn // RX     ...   
 R1 Rn  RA   Ra Rm  RA  RF RA 

v1 vn  v a vm 

  
...  Req  
R1 Rn 
  

R
...
R
RF 

  a m
 R 
Where Req   1  F R1 // ....Rn // RX 
 RA 
Design of Multiple-Input Op-Amp
4. Design of the multiple coefficients
Since dc path resis tan ces at both "" and "" inputs are equal
Then R1 // ....Rn // RX   Ra // ....Rm // RY // RF 
1
 X1    Xn   1  1 Ya     Ym   1  1
RF Rx RF Ry RF
and taking X  X1     Xn  Y  Ya     Ym 
1 RF RF
X   1  1 1  Y  1 or Xlying all by RF ,  X    1  Y 
RF Rx RF Ry Rx Ry
R R
Then X  Y  1  F  F  Z (Assume)
Ry Rx
Design of Multiple-Input Op-Amp
5. Design table
R R
Now Z  X  Y  1, or Z  F  F
Ry Rx
R R
Case I  if Rx   , F  0 then Z  0 substitute F  0 in the above equation and
Rx Rx
R R
Case II  if Ry   , F  0 then Z  0 substitute F  0 in the above equation and
Ry Ry
R RF
Case III  if Rx    Ry , then Z  0 substitute F   0 in the above equation
Rx Ry
Summing amplifier design table below gives the summary of the substituted equations

Ra
RF
Va
Ri Rj Rb
Case Z RY RX Vb
(n-inv) (inv)
Rm Ry vo
I Z > 0 RF / Z  RF / Xi RF / Yj Vm
II Z<0  - RF / Z RF / Xi RF / Yj R1
V1
III Z=0   RF / Xi RF / Yj V2
R2
Rx
Rn
Vn
 Summary of Design Equations
Multiple-Input Amplifier
According to Vo equation, multiple input op. amp. circuit is drawn first with positive
term resistors plus standard R X at “n-inv” terminal then with negative term
resistors plus standard RY at “inv” terminal. Add standard RF RF
1. Assume given VO = -10V2 + 5V1 R2
V2
2. Draw circuit with one resistor (R 1) for +5V1 and Ry vo
one standard RX at “n-inv” terminal. R1
3. Continue with one resistor (R 2) for –10V2 and one V1
standard RY at “inv” terminal. Rx
4. Add feedback resistor RF.
Vo  5V1  10V2   coeff. is X  5, and - coeff. is Y  10,
5. Find Z
Find Z  X  Y  1  5  10  1  6

Case Z RY RX Ri (n-inv) Rj (inv)

6. Use Design Table
II Z<0  - RF / Z RF / X i R F / Yj

R R R
7. Find resistor ratio As Z  0 From table, RY  , RX   F , R1  F , R2  F
6 5 10
8. Find RF from required type and value of resistance at input terminal of the op.
Amp. Assume required min 10kW at Op. Amp. Input terminal.
R R R
Now find which resistor is min .  RY  , RX   F , R1  F , R2  F
6 5 10
 R  R
As  R2  F  is min . of all ratios, then 10k  R2  F  Find RF  100k
 10  10

9. Now we can find RX , R1 and R2 by using RF=100k

100k 100k 100k
RX    16.67k, R1   20k, R2   10k
6 5 10

10. Finally draw the circuit with designed values

100k=RF
10k=R2
V2
Open Ry vo V = -10V + 5V
O 2 1

V1
20k=R1 16.67k=Rx
 Design Example-1
H.W. 2.1 (LECTURE)
Design an op. Amp. Circuit to implement the equation V o=4V1+V2-8Va-6Vb .
Design with lowest resistance at any input terminal of the op. Amp = 10kW

Vo  4V1  V2  8Va  6Vb  X  5, Y  14, Z  X  Y  1  5  14  1  10

Ri Rj
Case Z RY RX
(n-inv) (inv)
II Z<0  - RF / Z RF / X i R F / Yj

R R R R R
Z0 From table, RY  , RX   F , R1  F , R2  F , Ra  F , Rb  F
 10 4 1 8 6

RF
Lowest resistance is RX    10k  RF  10  10k  100kΩ
 10
RF=100k
Ra=12.5k Va
100k 100k
 RX    10k, R1   25k, Rb=16.67k Vb
 10 4
VO
100k 100k RY  
R2   100k,& Ra   12.5k,
1 8
R1=25k V1
100k
Rb   16.67k R2=100k V2
6
RX=10k
Design Example-2 (conventional method)
Design an Op. Amp. Circuit with a minimum resistance 10kW and the output
VO = -100VX +50VY.. Design with Superposition Method.
The circuit is differential Op. Amp. Circuit as Ra
RF
the output contain one positive term and one VX
negative term and derive Vo equation. vo
R R1
When VY  0, Vo   F VX & VY
Ra
R2
 R  R2 
When VX  0, Vo  1  F  VY

 Ra  1R  R2 1000k
FromSuperposition theorem, if VX  VY  0 then 10k
VX
 R  R2  R vo
Vo  1  F  VY  F VX  50VY  100VX (given)
 Ra  R1  R2  Ra 10k
VY
R R2 1 10k
 F  100 and  and take R1  R2  10k
Ra R1  R2 2
As any R  10k, Ra  10k Take Ra  10k 1000k
 RF  100Ra  1000k 10k
VX
To make equal dc resis tan ce at both  &  inputsof op. amp, vo

change 20k & 20k at VY termnal 20k

VY
20k
 Design Example-3 (multiple input design method)
Design an Op. Amp. Circuit with a minimum resistance 10kW and the output
VO = -100VX +50VY.. Design with Multiple input design method.

According to Vo equation, it is multiple input op. amp. RF

circuit with one input at “inv” terminal (for -100VX) and Ra
VX
another at “n-inv” terminal (for +50VY). Standard RX vo
Ry
and RY are included first.
Vo  50VY  100VX  X  50, Y  100, Z  X  Y  1  50  100  1  51 R1
VY
Rx
Ri Rj
Case Z RY RX
(n-inv) (inv)
II Z<0  - RF / Z RF / X i R F / Yj
Z0 From table,
 R R   R R   R R 
RY  ,  RX   F   F ,  R1  F  F ,

 Ra  F  F 
 Z 51   X1 50  
 Y1 100 
1000k
RF 10k
Lowest resistance is Ra   10k  RF  100  10k  1000kΩ VX
100 vo
20k
1000k 1000k 1000k VY
 RX    20k, R1   20k, Ra   10k 20k
 51 50 100
 Design Example-4
EXAMPLE 2.5 (PAGE 51-TEXT)
Design an op. Amp. Circuit to implement the equation V o=4V1+V2-8Va-6Vb .
Design with equal DC path resistance = 10kW
Vo  4V1  V2  8Va  6Vb  X  5, Y  14, Z  X  Y  1  5  14  1  10

Case Z RY RX Ri (n-inv) Rj (inv)

II Z<0  - RF / Z RF / X i R F / Yj
R R R R R
Z0 From table, RY  , RX   F , R1  F , R2  F , Ra  F , Rb  F
 10 4 1 8 6
DC path  RX//R1//R2  RY//R a//Rb  10kΩ0kΩ(rered spec.)
1 1 1 1 10 4 1 15
         RF  15  10k  150kΩ
10k RX R1 R2 RF RF RF RF
Or from page 49, equation (2.41), RF  Y  1 10k  (14  1)  10k  150kΩ

150k 150k RF=150k

 RX    15k, R1   37.5k, Ra=18.75k Va
10 4
150k 150k Rb=25k Vb
R2   150k, Ra   18.75k,
1 8 VO
150k
RYy= 
R 
Rb   25k
6 R1=37.5k V1
R2=150k V2

RX=15k
 Design Example-5
EXAMPLE 2.5 (PAGE 51-TEXT)
Design an op. Amp. Circuit to implement the equation V o=4V1+V2-8Va-6Vb .
Design with highest resistance of 200k at any input terminal except feedback resistor R F
Vo  4V  V  8Va  6V  X  5, Y  14, Z  X  Y  1  5  14  1  10
1 2 b
Ri Rj
Case Z RY RX
(n-inv) (inv)
II Z<0  - RF / Z RF / X i R F / Yj

R R R R R
Z0 From table, RY  , RX   F , R1  F , R2  F , Ra  F , Rb  F
 10 4 1 8 6
R
Highest resistance is R2  F  200k  RF  200kΩ
1

RF=200k
Ra=25k Va
200k 200k
 RX    20k, R1   50k, Vb
 10 4 Rb=33.33k
200k 200k VO
R2   200k,& Ra   25k, RRyY=  

1 8
200k R1=50k V1
Rb   33.33k
6 R2=200k V2

RX=20k
 Multiple-Stage Gain
Multiple-Stage Gain
Rf Rf Rf  R   R 
Q1   1  f Vi and Q2    f Q1
R1 R2 R3  R1   R2 
 R   R  R 
and Vo    f Q2    f   f Q1
Q1 Q2 Vo  R3   R3  R2 
 R   R  R 
Vi    f     f  1  f Vi
 R3   R2  R1 

50k 500k

Vo1
 500k 
Vo1    Vi  10Vi
25k 500k  50k 
 500k 
Vo2 Vo2    Vi  20Vi
 25k 
 500k 
Vo3    Vi  50Vi
 10k 
10k 500k

Vo3
Vi
Voltage Subtraction

R1 Rf Rf
R3

V1 Vo1 Vo2
R2
V2

 R   R 
Vo2    f Vo1    f V2
 R3   R2 
 R 
But Vo1    f V1
 R1 
 R  R   R 
Vo2    f   f V1    f V2
 R3  R1   R2 
R R R
 f  f  V1  f  V2
R3 R1 R2
if Rf  R1  R2  R3  Vo2  V1  V2
Subtraction
Op-Amp Instrumentation circuits

o Instrumentation Circuits
o Active Filters
 Instrumentation Circuits
DC Millivoltmeter
100k
V1(DC) Vo
R1
0 - 1mA
M
meter
Rf
Io
100k R 10
S

Vo (DC) R
Neglecting meter int ernal resis tan ce,  f
V1 (DC) R1
Vo (DC)  R f  1
Neglecting IRf  IRS  Io  IRS      V1 (DC)  
RS  R1  RS
Io R 1 100k 1 1mA
  f     
V1 (DC) R1 RS 100k 10  10mV (DC)

If Rf  100k is changed to 200k meter will have :

Io R 1 200k 1 1mA
  f     
V1 (DC) R1 RS 100k 10  5mV (DC)
AC Millivoltmeter 100k Filter
V1(AC) Vo Capacitor
R1 500F
D2
D1
0 - 1mA M
meter

Rf Coupling
Capacitor
100k Io 1F
RS 10

Vo
Vi is AC then Vo is AC
D1 D2 conduct through meter and RS in full  wave DC
Vo (AC) R
Neglecting meter int ernal resis tan ce,  f
V1 (AC) R1
Vo (AC)  R f  1
Neglecting IRf  IRS  Io  IRS      V1 (AC)  
RS  R1  RS
Io R 1 100k 1 1mA
  f     
V1 (AC) R1 RS 100k 10  10mV (AC)
 600mA

Lamp display driver V1(input)

30mA lamp

Io 100k 

5V

20mA
LED driver V1(input)
Io
LED
(5V-2V)/20mA=150
 Instrumentation Amplifier

V2 VX R

R R
V2
RP Vo
R
V1 R
R

V1 VY

- Input impedance is infinite and can provide higher gains

- Rp is an external gain-setting resistor.
- Output voltage: Vout = Acl(V1 – V2)
- For R1 = R2 = R, and R3 = R4 = R5 = R6 = R
Acl= 1+2R/Rp
If VX and VY are input to final differenti al amp.
 R   R2  R R R  R
Vo  VY  1  f      VX   VY  1       V   VY  VX
R R  R  R  R   R  R 
X
R
 1   2 3
Increase of
(v   v  )  two voltages V2 and V1 are at the junction of R and RP respectively differential gain will
V1  V2  VY  VX  make CMRR larger as
IR  IRP   CMRR = Ad / Ac
RP 2R  RP 
V  V2   2R 
Vo  VY  VX  1  2R  RP    1    V1  V2 

RP  RP 
Instrumentation Amplifier
 Notes on Instrumentation Amplifier
• The main purpose of an instrumentation amplifier is to
amplify small signals that are riding on large common‐
mode voltages.
• Commonly used in environments with high common‐
mode noise, e.g., remote temperature or pressure
sensing over a long transmission line.
• Its main characteristics are: high Zin, high CMRR, low
output offset, and low Zout
• A typical IC instrumentation amplifier : AD521
Example: Find Vo in terms of V1 and V2 and find the differential gain Ad = (Vo/(V1-V2)). This
make how many times CMRR larger compared to the use of only final differential amplifier?

V2 VX 5k

5k 5k
V2
0.5k Vo
5k
V1 5k
5k

V1 VY

(v   v  )  two voltages V2 and V1 are at the junction of R and RP respectively

V1  V2  VY  VX  VY  VX 
IR  IRP   
0.5k 2  5k  0.5k  10.5k 
V  V2 
Vo  VY  VX  1  10.5k   21  V1  V2 
0.5k
Vo
Ad   21
V1  V2 
Increase of differential gain is 21 , this make
CMRR larger 21 times as CMRR = Ad / Ac
Controlled Sources
 Controlled Sources
Voltage–Controlled Voltage Source

R1 Rf
Voltage Non-inverting
Vo source  R 
Vo   1  f V1  kV1
V1 RC Ii=0  R1 

Control Voltage

No drop in RC

Rf
Voltage Inverting
R1
source  R 
Vo Vo    f V1  kV1
V1  R1 

Control Voltage
 Controlled Sources
Voltage–Controlled Current Source
Current
source V 
I L  I o  I1   1   kV1  RL
 R1 

Control Voltage
Current source for grounded load
Current source for grounded load
(voltage controllable)
Current–Controlled Current Source

I2 Io
R2 I1 R
L
R1 I1R1  I2R2  v   v   0 
I R   R 
Io  I1  I2  I1   1 1    1  1 I1  kI1
I1  R2   R2 

Current source Control Current

Current–Controlled Voltage Source (Current‐

to‐Voltage Converter)

I1 RL I1

I1 Vo

Voltage
source
Vo  I1RL  kI1 - As the amount of light changes, the
current through the photocell changes;
Control Current Thus Vout = -IiRf
Example: Calculate IL in the circuit below.
4k
I1 2k IL
+  8V 
Iin=0 IL  I1     0.5mA  8V  4mA
8V  2k 
-
2k

Example: Calculate Vo in the circuit below.

+ 2k -
10mA

Vo  I1RL   2k I1  2k  10mA  20V

10mA Vo
Design of Op-Amp Circuits
for Special Applications
- Negative Resistance Circuit
- Sign Changer
- Differential Voltage-Current Converters
- Voltage-Current Converters
- Analog Computation Circuits
Negative Resistance Circuit
RF
RA

vo
i
Negative +
Resistance v R
-

voRA  R 
v  v   v  vo   1  F   v
RA  RF  RA 
v  vo v  R  v v R 
i    1  F     1  1  F 
R R  RA  R R  RA 
v  RR 
    A 
i  RF 

Negative Resistance generator !

Example
• Draw the negative resistance Op. Amp. circuit and find the value of the
negative resistance in terms of the circuit components, R F , RA and R
• Design the circuit to have a negative resistance of –1kW, and a specified
minimum dc path resistance at each op. amp. input of 10kW.

RF
vR  R 
v   v   o A  v  vo   1  F   v
RA  RF  RA  RA
v  vo v  R  v v R 
i    1  F     1  1  F  vo
R R  RA  R R  RA  i
v  RR  +
    A  v R
i  RF  -

v  RR 
  A   1k, But dc path at non  inv input  R  10k
i  RF 
R  1k
 A   0.1
RF  10k
RF RA RA RA
dc path at inv. input RF // RA   10k  
RF  RA RA 1  0.1
1
RF
R
 RA  1.1  10k  11k, RF  A  110k
0.1
 Sign Changer
R
R
vi
+ vO
- R1

when the switch is at ""

v   v   vi no current in both R also in R1 
 vo  v   vi  vo   vi 
when the swich is at ""
Sign Changer !
v   v   0 no current in R1 
vo  0 0  vi
  vo  vi
R R
 Example
• Draw the Sign Changer Op. Amp. circuit and show how the output sign
changes according to the switch position
• Design the circuit which has an input resistance of 1MW.

when the switch is at "" R

v   v   vi no current in both R also in R1  R
 vo  v   vi  vo   vi  vi
+ vO
when the swich is at ""
- R1
v   v   0 no current in R1 
vo  0 0  vi a
  vo  vi
R R

when the switch is at "" Rin    R1    1M   or R1  1M is OK

and vO  vi
when the swich is at "" Rin  R  1M
and vO  vi
Differential Voltage-Current Converter
R2

R1
v
vO
vi
R1

R2
RL IL

V  Vi V  Vo V  V V  Vo
  IL  0   
R1 R2 R1 R2
V  Vi V V
  IL  
R1 R1
V  V  V  Vi  V1  V
IL   
R1 R1

Differential voltage to current converter !

Example
• Draw the Differential voltage to current converter Op. Amp. circuit and find
the value of the load current I L in terms of the circuit components, R 1 , V1 and V
• Design the circuit to have a full-swing load current I L of ±1mA for a specified
full input of ± 1mV at the circuit of the op. amp.
0mV R1 R2
v
vO
vi
V  Vi V  Vo V  V V  Vo R2
  IL  0   +1mV R1
R1 R 2 R 1 R 2
V  Vi V V
  IL   RL IL
R1 R1
V  V  V  Vi  V1  V
IL    +1A
R1 R1

V V  1mV  1mV
IL  1  1A   R1   1k
R1 R1  1A
We can take RL  R2  R1  1k
Voltage-Current Converter
R

IL V1
R

V1 R1

V  V  V1
but ILR1  V (no drop at R)
 V  V1  ILR1
V1
IL 
R1

Voltage to current converter !

Example
• Draw the Voltage to current converter Op. Amp. circuit and find the value of
the load current IL in terms of the circuit components, R 1 , V1 and V
• Design the circuit to drive a dc motor with load current I L of 20mA from digital
drive voltage of 5V connected to the input of the op. amp. Circuit. (Note that op.
amp. power supply should be ±Vcc > ±5V)
R

V  V  V1 5V
20mA
but ILR1  V (no drop at R) R
 V  V1  ILR1 IL
5V R1
V1 dc motor
IL 
R1

V 5V
IL  1  20mA  R1   250
R1 20mA
we can take R  R1  250,
(Note input current int o the circuit is nearly zero from 5V digital source)
 Summary of Design Equations
Special Application Circuits

1. Negative Resistance RF 2. Sign Changer

R
Generator
RA
R
vi
vo + vO
i
v  RR 
  A  + - R1
i v R
 RF  - switch at "" vo  v1 a switch at "" vo  v1

3. Differential voltage to 4. Voltage to current converter

R2
current converter
R
R1
v
vO
vi
IL V1
R1 R
R2 V
RL IL V1 R1 IL  1
V V R1
IL  1
R1
 Analog Computation Circuits
• Integration and Multiple Summing

d3x d2x dx Q3  x
Q Q1   Q2  C ic
dt 3 dt 2 dt
R iR vc
R C C X
v-
R C Y
R v+

RC=1
RC=1 RC=1 1
Y
CR 
X dt  Y  integral of X

R1 R
R R  dx  R  d2 x  R
R2 Y    x       Z
Y R1 R2 dt  dt2  R
  R3   4
R3
R R dx R  d2 x  R
R4  x       
 dt  R
2
Z 
Z R1 R2  dt  R3   4

 X1V1  Y1V2  X2V3  Y2V4  Output equation

Example
• Design the Op. Amp. Circuit, that can operate the following differential
equation and whose lowest resistance at any input terminal of the Op. Amp
should bed310kW
x dx d2x
 4x  8  12
dt3 dt dt2

(a) Draw Integrators with RC=1 where the first input is the highest order in given
differential equation. Note the output of each Integrator.
d3x d2x dx
Q Q1   Q2  V1  x
dt3 dt2 dt

R C C
R C
R

RC=1
RC=1 RC=1

(b) Rearrange the given equation using available output of each Integrator.
d3x dx d2x
 4x   8 2  12
dt3 dt dt Here the constant “12” is taken as a (+2V
dx  d2x  battery) with a coefficient of 6.
 4(-x)   8 - 2   6 2 
dt  dt 
 
Available outputs from the Integrators
(c) Find Z from the modified equation and design the Multiple-Input Op. Amp. to
get Vo same value as the highest order and draw the designed circuit:

d3x dx  d2x 
Assume Vo  3  4(-x)   8 - 2   6 2   X  9, Y  10, Z  9  10  1   2
dt dt  dt 
 
Ri Rj
Case Z RY RX
(n-inv) (inv)
II Z<0  - RF / Z R F / Xi RF / Yj

R R R R R
Z0 From table, RY  , RX   F , R1  F , R2  F , Ra  F , Rb  F
2 1 8 4 6
R
Lowest resistance is R2  F  10k,  RF  80k
8

RF=80k
R 80k
R1  F  80k, R2   10k, 20k
1 8 -x
80k 80k 2V VO
Ra   20k, Rb   13.33k
4 6 13.33k
dx/dt 80k
-(d x/dt2)
2 10k dx d2 x
Vo  4x  8  12
Rx 40k dt dt2
(d) Connect the Multiple-Input Op. Amp. Inputs with the outputs of the Integrators
showing the output equals to the highest order of the given equation and draw the
designed circuit:
d3x d2x dx
Q Q1   Q2  V1  x
dt3 dt2 dt

R C C
R C
R
Input signal
RC=1
RC=1 RC=1

RF=80k
20k
-x

2V VO
13.33k
dx/dt
80k Output signal
10k dx d2x d3x
2
-(d x/dt ) 2
Rx 40k Vo  4x   8 2  12  3
dt dt dt
 (e) form a loop connecting the output Vo back to the first input (highest
order of the equation) of the Integrators and get the Analog Computation
Circuit that can operate the given differential equation

d3x d2x dx
Q Q1   Q2  V1  x
dt3 dt2 dt

R C C
R C
R
Input signal
RC=1
RC=1 RC=1 Designed Analog
Computation
Circuit

RF=80k
20k
-x
d3 x dx d2 x
Vo   4x  8  12
2V VO 3 dt 2
dt dt
13.33k
dx/dt Output signal d3 x d2 x dx
80k or 8   4x  12
10k dt3 dt2 dt
-(d2x/dt2) Rx 40k
 • Initial Condition of the
equation
(f) The initial condition of the equation is electronically generated by
a voltage source connected at the output of the given term.

switch closes at t  0 switch closes at t  0

2
d x d x 2 switch closes at t  0
Q1   2  5 or 5 dx
Q1   3 Q3  x  0
dt dt 2 dt

d3x d2x dx
Q Q1   2 Q2  Q3  x
3 dt
dt dt
5V 3V

t=0 t=0 t=0

R C C
R C
R
"0"
"0"
RC=1 "0"
RC=1 RC=1
 Summary of Design Equations
Analog Computation Circuit
(a) Draw Integrators with RC=1 where the first input is the highest degree in given
differential equation. Note the output of each Integrator.
(b) Rearrange the given equation using available output of each Integrator.

(c) Find Z from the modified equation and design the Multiple-Input Op. Amp. to
get Vo same value as the highest order and draw the designed circuit:
(d) Connect the Multiple-Input Op. Amp. Inputs with the outputs of the Integrators
showing the output equals to the highest order of the given equation and draw the
designed circuit:

(e) form a loop connecting the output Vo back to the first input (highest
order of the equation) of the Integrators and get the Analog Computation
Circuit that can operate the given differential equation
(f) The initial condition of the equation is electronically generated by
a voltage source connected at the output of the given term.
 Comparators
By Schmitt Trigger Design
 Comparator IC
Comparator IC = Two inputs of the IC are compared to each other as below:
+VCC

• When “V+” is more positive than “V-” Output V o will go high to +VCC
V-
( = “V-” is more negative than “V+” ) VO

V+
• When “V-” is more positive than “V+” Output V o will go low to –VCC
-VCC
( = “V+” is more negative than “V-” )

+10 +10 +10

0
VO=+10V +0.1 +0.1 VO=+10V
VO=-10V
0 +0.5
+0.1

-10 -10 -10

Output is binary either “+10V” or “-10V”

 +10 When Reference is “0V”
Reference (Zero-crossing Comparator)
+10
VO
+1
Output is digital either “+10” or “-10”
-1 -10
Input -10
• When “V+” is more positive than “0” Output V o will go high to +VCC
• When “V+” is more negative than “0” Output V o will go low to –VCC

+10
Input
+1 +10
VO
-1 Output is digital either “+10” or “-10”

-10
Reference -10

• When “V-” is more positive than “0” Output V o will go low to -VCC
• When “V-” is more negative than “0” Output V o will go high to +VCC
Zero-crossing Comparator can be used for non-sinusoidal waveforms.
It can be used to detect whether the signal has overshot a given level
and what duration it has overshot, etc.
+ VCC Vin
+
+ VCC
R 0 t
2 7
6 -
VO
R 3
4
+ VO
+ VCC
0 t
- VCC - VCC - VCC
Click to add
- text
Vin
Zero-crossing Detector (Non-inverting)

Vin Vin
+
+ VCC + VCC
0 t

R
2 7
6 -
VO
3
4
+ VO
+ VCC
R
0 t
- VCC - VCC

- VCC
-
Zero-crossing Detector (Inverting)
 When Reference is “Non-0V”
(Reference-crossing Comparator or Nonzero‐Level Detector)

+5
+10
0
+5
R1 -4-5
VO
+10
-4 Output is
-5 R2 digital
-10

-10
• When “V-” is more positive than Vref “-4” Output Vo will go low to -VCC
• When “V-” is more negative than V ref “-4” Output Vo will go high to +VCC
Reference-crossing Comparator can be used for non-sinusoidal waveforms.
It can be used to detect whether the signal has overshot a given level
and what duration it has overshot, etc.

+ VCC Vin
+
+ VCC Vref
R 0 t
Vref 2 7
6 -
VO
2R 3
4
+ VO
+ VCC
0 t
- VCC - VCC
Vin
-
V(ref)-crossing Detector (Non-inverting)
 Comparator With Hysteresis
(Schmitt trigger)
- Hysteresis is achieved by positive
feedback and makes the
comparator on the input less
sensitive to noise input.

- If input voltage is higher than

UTL (VUT) Vo will become VLO
- If input voltage is lower than LTL
(VLT) Vo will become VHI.
R2 R1
LTL  VREF  V
R1  R2 R1  R2 LO
R2 R1
HTL  VREF  V
R1  R2 R1  R2 HI

- If VREF=0, VLO=-Vsat, VHI=+Vsat then:

R1
V LT  LTL  (Vsat )
R1  R2
R1
VUT  HTL  (Vsat )
R1  R2
 Example:
Find HTL and LTL of the given Schmitt Trigger circuit. Take e in =
±5V, VHI=+5V and VLO=-5V, VREF=3V. Find Hysterisis and Sketch the
output waveform.
ein= ±5V vHI =+5V
vLO =-5V

R1=5kW R2=10kW
ein=±5V

VREF=3V
UTL=3.67V

Hyterisis=3.67-0.33=3.34V
10k 5k
LTL=0.33V LTL  3 ( 5)  0.33V
5k  10k 5k  10k
10k 5k
HTL  3 ( 5)  3.67V
5k  10k 5k  10k
Hyterisis  3.67  0.33  3.34V
VHI=+5V

t
VLO=-5V
 Example:
An inverting Schmitt trigger has a sine wave input e in of amplitude
5V. If output level is to be VHI=+5V and VLO=-5V respectively, design
R1 and feedback resistor R2 so as to eliminate random switching by a
noise level between a Hysterisis from (-0.5) V to +1V. Take V REF=0.6V
and R1 + R2=100k.

ein
ein= ±5V vHI =+5V
vLO =-5V
Noise

R1 R2

+5V VREF=0.6V R2 R1
LTL  0.6  ( 5)  0.5
R1  R2 R1  R2
R2 R1
HTL  0.6  ( 5)  1
vo R1  R2 R1  R2
R2
HTL  LTL  1.2  0.5  R2  41.67k
100k
R2 R
-5V HTL  LTL  10  1.5  2 10  1.5
R1  R2 100k
R2  0.15  100k  15k
 Window Comparator

The peak detector does one thing: it monitors a voltage of interest

and retains its peak value as its output.
 Application:
Over-temperature sensing circuit
Application: ADC
 Other Application Circuits and
Nonlinear Circuits with OP-AMP
 Operational Transconductance Amplifier
(OTA)
• The OTA is primarily a voltage‐to‐current amplifier where
Iout = gmVin.
• The voltage‐to‐current gain of an OTA is the
transconductance, gm = KIBIAS where K is dependent on
the internal circuit design.
Basic OTA Circuit
OTA Amplitude Modulator
Output Bounding With One Zener
Output Bounding With Two Zeners
 Log Amplifiers
• The basic log amplifier produces an output voltage as a
function of the logarithm of the input voltage; i.e.,
Vout = ‐K ln(Vin)
where K is a constant.

• Recall that the a diode has an exponential characteristic

up to a forward voltage of approximately 0.7 V.

• Hence, the semiconductor pn junction in the form of a

diode or the base‐emitter junction of a BJT can be used
to provide a logarithm characteristic.
Diode & BJT Log Amplifiers
Basic Antilog Amplifier
Signal Compression With Log Amplifier
• When a signal with a large dynamic range is
compressed with a logarithmic amplifier, the
higher voltages are reduced by a greater
percentage than the lower voltages, thus
keeping the lower signals from being lost in
noise.
Peak Detector
Triangular‐Wave Oscillator
Square‐Wave Oscillator
Precision Rectifier Circuit
(with non-ideal diode)
Precision Rectifier Circuit
(with non-ideal diode)
Precision Rectifier Circuit
(with non-ideal diode)
Precision Rectifier Circuit
(with non-ideal diode)
Precision Full-Wave Rectifier
Precision Rectifier Circuit
(with non-ideal diode)
Other Precision Circuits
Limiter Circuits for Precise Output Levels
Two-segment function generator
(assume diode is ideal)
Nonlinear function generator
(assume ideal diodes)
Nonlinear function generator
(assume ideal diodes)
Nonlinear function generator
(assume ideal diodes)
 Generalized Nonlinear Function Generator
Rn
Vn
Rn-1
Vn-1

R0
Dk OR

R-m+1 RF
V-m+1
R-m
V-m
VOUT
VIN

Assume Vn > Vn-1 >...V1 > 0 > V-1 >… > V-m

• Provides m+n+1 segment nonlinear function

• Slopes are always positive and greater than 1
• Can generate arbitrary nonlinear transfer characteristic
• Actually works better with nonideal diodes
• Can be extended to provide slopes less than 1
• Can be further extended to provide slopes of arbitrary sign and arbitrary magnitude
Generalized Nonlinear Function Generator

^
^ Rs
Vs Ds
^
Rn OR
^ Vn Dn
Vs-1 Ds-1 Rn-1
Vn-1 Dn-1
^
R0
R0
^
^
R-r+1 RF RX
^
V-r+1 D-r+1
^
^ R-r
V-r D-r R-m+1 RF
V-m+1 D-m+1
VIN VOUT1 R-m
^ V-m
(1-θ)R D-m VOUT
^
θR VIN
(1-θ)R
θR

• Provides m+n+r+s+2 segment nonlinear function

• Slopes can be positive or negative of any magnitude
• Analysis and design tedious but straight forward
Nonlinear function generator
(assume ideal diodes)
 Passive Components
• Resistors
– The resistor or capacitor type is defined by
• the manufacturing process,
• the materials used, and
• the testing performed.
– carbon composition
• hot-pressed carbon granules
• used in digital circuits as +3.3V pullups.
– 1% metal film, thick film or thin film resistors
• analog amplifier circuits
• analog filter circuits
 Passive Components
• Capacitors
 Passive Components
• Polarized capacitors
– only positive voltages are applied
– DC power supply filters
• Nonpolarized or bipolar capacitors
– operate for both positive and negative voltages
– analog filters
• Capacitor specification
– low leakage (impedance),
– accuracy (tolerance)
– low temperature coefficient
– temperature range,
– voltage range,
– frequency range,
• Extremely High Quality Capacitors
– Teflon, polystyrene
– Polypropylene, 1,2,3,5%.
• Medium Quality Capacitors 5%, 10%, 20% tolerance
– C0G ceramic, 5%, 30ppm/oC, ±0.3% over -55 to 125oC
– X7R ceramic, 10%, ±15% over -55 to 125oC
– Z5U ceramic, 20%, 22 to -56% over 10 to 86oC
Review of OPAMP, Instrument OPAMP and
Filters

Open data sheet for OPA2350 and observe this data

 Review of OPAMP, Instrument OPAMP and
Filters
• A wide range of analog circuits can be designed by
following these simple design rules 1 through 10:
– 1. Choose quality components
– 2. Negative feedback is required to create
– a linear mode circuit.
– 3. Assume no current flows into the op
amp inputs, Ix=Iy=0.
– 4. Assume negative feedback equalizes the op
amp input voltages, Vx=Vy.
– 5. Choose resistor values in the 1 kΩ to 1 MΩ range.
– 6. The analog circuit bandwidth depends on the gain and the op
amp performance.
• Let the unity-gain op amp frequency response be f1, and the analog
circuit gain be G. The frequency response or bandwidth of the analog
circuit, BW, will be f1/G.
Review of OPAMP, Instrument OPAMP and
Filters
– 7. Equalize the effective resistance to ground at the two op
amp input terminals.
– 8. The impedance is the voltage divided by the current.
Review of OPAMP, Instrument OPAMP and
Filters
– 9. Match input impedances to improve CMRR.
Review of OPAMP, Instrument OPAMP and
Filters
– 10. Rail-to-rail considerations.
• When designing with rail-to-rail op amps, we must
guarantee that the voltages at all input and output
pins of the op amps never go outside the range of
-Vs to +Vs .
 Review of OPAMP, Instrument OPAMP and
• Filters
Linear Mode Op Amp Circuits
– Design an analog circuit in the form as in the figure:
Vout = A1V1 + A2V2 +…+ AnVn + ArefVref
– To determine the resistor values, add a ground input Vg = 0:
Vout = A1V1 + A2V2 +…+ AnVn + ArefVref + AgVg
– Choose Ag such that: A1+ A2 +…+ An + Aref + Ag= 1
– Choose Rf in the range of 10 kΩ to 1MΩ. The larger the gains,
the larger the value of Rf must be. Then calculate input resistors
to create the desired gains as below. Note if the gain is positive,
then the input resistor is connected to the positive terminal of the
op amp and vice versa.
 Review of OPAMP, Instrument OPAMP and
•
Filters
Example of Linear Mode Op Amp Circuits
– Design an analog circuit with a transfer function of:
Vout = 3V1 + 6V2 – 7.5
– Choose REF3312 +1.25 V as a reference
voltage:
Vout = 3V1 + 6V2 – 6Vref
– Add a ground input to the equation so that the
sum of all the gains is equal to one:
Vout = 3V1 + 6V2 – 6Vref – 2Vg
– Choose a feedback resistor, Rf =60 kΩ. The
value is a common multiple of the gains:
6,3,2. Then calculate input resistors to create
the desired gains.
 Review of OPAMP, Instrument OPAMP and
Filters
• Instrumentation Amp
– Necessary condition (this must be true)
• amplify a differential voltage, shown below as V2-V1
– Sufficient condition (one or more of this made
be true)
• large gain (above 100),
• a high input impedance, and
• a good common mode rejection ratio. Or low noise
 Active Filters
Input of the filter is all frequencies but the output of the filter is a certain band
of frequencies and no output at any other frequencies depending upon the type of
the filter such as Low-pass filter, High-pass filter , Band-pass filter, and Band-
reject filter. Active filters use active components such as BJT, FET, IC etc.
Vin Vin Vo Vo
1V Low-pass filter 1V

f f
0  fH

Vin Vin Vo Vo
1V High-pass filter 1V

f f
0  fL

Vin Vin Vo Vo
1V Band-pass filter 1V

f f
0  fL fH

Vin Vin Vo Vo
1V Band-reject
1V
filter
f f
0  fH fL
First order Low-pass Filter Rf
RG

vo
At low frequencies C1 opens v+
V1(input)
and thus V+ = V1 passing the R1
low frequencies C1
R= Op. Amp. then amplifies
V+ to V   1  Rf   V
o  RG 


V

V+ falls 20dB/decade
(= 6dB/octave) due to R1C1
 R  Vi  V
Vo   1  f   V
 RG 
f
1 Higher cut-off frequency
fH  fH
2R1 C1
Second order Low-pass Filter
Rf When R1C1 = R2C2= RC
V
RG V+ falls 40dB/decade (=
12dB/octave) due to
both R1C1 = R2C2= RC
vo
V1(input) v+
 R  Vi  V
R1 R2 Vo   1  f   V
 RG 
C1 C2 f
R= 1
fH  fH Higher cut-off frequency
2RC
Op. Amp. then amplifies
V+ to V   1  Rf   V
o  RG 


When R1C1 and R2C2 are different
V
V+ falls 20dB/decade (=
6dB/octave) due to R1C1
after fH1
V+ falls 40dB/decade (=
R  Vi  V

Vo   1  f   V
12dB/octave) due to both
 RG  R1C1 = R2C2 after fH2
f
1 1
fH1 
2R1C1
fH1 fH2 fH2 
2R2C2
First order High-pass Filter Rf
RG

v+ vo
At high frequencies C1 short V1(input)
C1
and thus V+ = V1 passing the
R1
high frequencies R=
Op. Amp. then amplifies
V+ falls 20dB/decade V+ to V   1  Rf   V
o  RG 

(= 6dB/octave) due to R1C1 
V

 R  Vi  V
Vo   1  f   V
 RG 
f
1 Lower cut-off frequency
fL  fL
2R1 C1
Second order High-pass Filter When R1C1 = R2C2= RC
Rf V+ falls 40dB/decade (=
V 12dB/octave) due to
RG both R1C1 = R2C2= RC

V1(input) v+ vo
C1 C2  R 
Vo   1  f   V
Vi  V
RG 
R1 R2 
R= f
fL 
1 fL Lower cut-off frequency
Op. Amp. then amplifies 2RC
V+ to V   1  Rf   V
o  RG 



V When R1C1 and R2C2 are different

V+ falls 20dB/decade (=
6dB/octave) due to R1C1
after fL1
 R  Vi  V V+ falls 40dB/decade (=
Vo   1  f   V
 RG  12dB/octave) due to both
R1C1 = R2C2 after fL2
f
fL2 
1 fL2 fL1 fL1 
1
2R2C2 2R1 C1
 Band-pass Filter When R1C1 = R2C2= RC Rf
Rf
When fH > fL RG
RG
v+ vo
v+
V1(input) v2 R2
C1 C2
R1 R=
R=

At high frequencies C1 short At low frequencies C2 opens

and thus V+ = V1 passing the and thus V+ = V2 passing the
high frequencies (High-pass) low frequencies (Low-pass)
above fL below fH
V+ falls 20dB/decade
(= 6dB/octave) below V+ falls 20dB/decade
V fL (High-pass) due to Op. Amp. then amplifies
(= 6dB/octave) above
R1C1 fH (Low-pass) due to V+ to V   1  Rf   V
o  RG 

R2C2 

 R  Vi  V
Vo   1  f   V
 RG 
f
1 1
fL  fL fH fH 
2R1 C1 2R2 C2
 Band-reject Filter Rf
Rf
When fL > fH RG
RG
v+ vo
v+
V1(input) v2 R2
C1 C2
R1 R=
R=

At high frequencies C1 short At low frequencies C2 opens

and thus V+ = V1 passing the and thus V+ = V2 passing the
high frequencies (High-pass) low frequencies (Low-pass)
above fL below fH

V+ falls 20dB/decade
V (= 6dB/octave) above
fH (low-pass) due to Op. Amp. then amplifies
R2C2 V+ to V   1  Rf   V
o  RG 

V+ falls 20dB/decade 
(= 6dB/octave) below
 R  Vi  V Vi  V fL (High-pass) due to
Vo   1  f   V
 RG  R1C1
f
1 1
fH  fH fL fL 
2R2 C2 2R1 C1
 Example: Find cutoff frequencies fL and fH if R1 = R1=10kW , C1=0.1mF and , C2=0.002mF. Is it
a Band-pass filter or a Band-reject filter? Find the pass-band gain if RG=10kW and Rf=100kW
Rf
Rf
RG
RG
vo vo
v +
v+
V1(input) R2
C1 C2
R1 R=
R=
1 1
fL    159.15Hz
 
2C1R1 2 0.1  10 6 10  10 3


1 1 V
fH    7.96kHz
 
2C2R2 2 0.002  10  6 10  10 3 
When fH > fL it is a
Band –pass filter
At pass  band, V  Vi
 R  V  100k  f
Vo   1  f   V  o   1    11
 RG  Vi  10k  fL=159Hz fH=7.96kHz
 Example: Find cutoff frequencies fL and fH if R1 = R1=10kW , C2=0.1mF and , C1=0.002mF. Is it
a Band-pass filter or a Band-reject filter? Find the pass-band gain if RG=10kW and Rf=100kW
Rf
Rf
RG
RG
vo vo
v +
v+
V1(input) R2
C1 C2
R1 R=
R=
1 1
fL    7.96kHz
 
2C1R1 2 0.002  10  6 10  10 3  V
1 1
fH    159.15Hz
 
2C2R2 2 0.1  10 6 10  10 3


When fH < fL it is a
Band –reject filter
At pass  band, V  Vi
 R  V  100k  f
Vo   1  f   V  o   1    11
 RG  Vi  10k  fH=159Hz fL=7.96kHz