Micro

TOPIC : INTERFACING
& REFRESHING
DYNAMIC RAM
PRESENTED BY: Kanishk Pathania

DYNAMIC RAM :
 In DRAM Cell , the memory bits are stored in the form of charges across the
capacitor (as the representation of data).
 It has a presence of data bit either 0 or 1 corresponding to presence or
absence of stored charges in a capacitor.
or in other words, we can say that,
By charging and discharging the capacitor, it represents whether the bit that
is stored inside the capacitor is logic 1 or logic 0.
 One bit of DRAM cell , consists of one

transistor and one capacitor.
The other components of DRAM Cell are:
• Bitline/dataline
• Wordline /address line
READ OPERATION IN DRAM :
1. By applying voltage to the word line/address line(WL=1) , Turn
on the transistor.
2. As voltage is applied , charge available at capacitor will loose
and start flowing in the bitline/ dataline (represented by
logic 1).
3. By using Sense Amplifier , we can read the voltage at this
biltline.
As charges loose at capacitor during read operation ,it is called
Destructive Read Operation.
 To avoid the data loss at capacitor, we need to perform refresh
operation after every read cycle.
 It will be time consuming & reduce the read operation speed.
 To save the speed ,this bitline is precharged with finite
voltage.
By pre-charging this bitline by some finite value ,we can
reduce the read operation speed.
WRITE OPEARTION IN DRAM :
 During write operation ,all the bitlies are

precharged with some finite value.
 On which bitline we want to write, bit voltage is
applied to the particular bitline.
This is write operation in DRAM.
RAM HIERARCHY : RAM
DRAM SRAM
ADRAM
SDRAM ADRAM
SDR DDR
SDRAM SDRAM
DDR 1
DDR 2
DDR 3
DDR 4
DIFFERENT TYPES OF DRAM :
ADRAM (Asynchronous SDRAM (Synchronous
Dynamic RAM) Dynamic RAM)
  RAM is synchronized with the CPU
RAM is not synchronized with the
CPU CLOCK. CLOCK.
  Memory controller in the CPU know
CPU doesn’t know the exact timing of
data that is available in RAM . the exact timing of the data available
on the i/o bus.
 CPU doesn’t need to wait for memory
access (that will increase read/write
speed).
Further types of SDRAM :
SDR SDRAM DDR SDRAM
 Double Data Rate Synchronous
 Single Data Rate Synchronous
Dynamic Random Access Memory.
Dynamic Random Access Memory.
 Data is transferred twice during
 Data is transferring at the every
each cycle.
rising edge of the CPU clock cycle.
(that is at positive as well as
negative edge of the CPU clock cycle).
Refreshing Dynamic RAM
 REFRESHING DRAMs is the process of periodically reading data from the
memory. This counters the natural leakage of charge in DRAM capacitors,
which would otherwise cause data loss.
The basic Dynamic RAM cell uses a capacitor to store the charge as a
representation of data. This capacitor is manufactured as a diode that is
reverse-biased that gradually leaks charge that tends to data loss.
To avoid this possible data loss, the data stored in a dynamic RAM cell must
be refreshed after a fixed time interval regularly. The process of refreshing
the data in the RAM is known as REFRESH CYCLE .
• A refresh cycle involves reading the data from a cell, amplifying it, and
then writing it back to the same cell.
• During his refresh period all other operations (accesses , like : Read or
write operation) related to the memory subsystem are suspended.
• Therefore, Access time get increased in DRAM as compared to SRAM.
• Refresh cycle is similar to memory read cycle with some differences:
o Memory address is provided by CPU address Bus in memory read cycle but
during refreshing the same process is done using refresh counter.
INTERFACING DYNAMIC RAM in 8085
1. DRAM Selection: Choose DRAM chips compatible with the 8085's memory interface.
2. Memory Address Decoding: the 8085's address lines (A0-A15) are decoded to enable the specific
DRAM chip during read/write operations.
3. Data Bus Connection: The 8-bit data bus (D0-D7) of the 8085 connects to the data pins of the
DRAM. This allows data transfer between the processor and memory.
4. Control Signal Interfacing: Several control signals from the 8085 need connections to the DRAM and
refresh circuitry:
 ALE (Address Latch Enable): Latches the lower order address lines onto the DRAM for data access.
 RD (Read): Indicates a read operation from the 8085.
 WR (Write): Indicates a write operation from the 8085.
 CE (Chip Enable ): Enables the specific DRAM chip based on address decoding.
 OE(Output Enable): Enables the specific output data buffer of memory chip.
1. Refreshing: The timer/counter triggers the refresh process at specific intervals.
 It generates the row address to be refreshed and sends it to the DRAM.
 The refresh control signal ensures the DRAM performs a refresh operation instead of a data access.
1. Buffering (Optional): Buffer circuits might be needed to ensure proper signal levels between the
8085 and DRAM.
DYNAMIC CELL ARRAY ARCHITECURE
Advantages of Dynamic RAM
• Higher Density: DRAM can pack more memory cells into a given area compared to SRAM,
making it more suitable for applications requiring large amounts of memory.
• Lower Cost Per Bit: Due to its higher density, DRAM generally has a lower cost per bit
compared to SRAM, making it more economical for applications with large memory
requirements.
• Low power consumption.
• Refreshing: Although DRAM requires periodic refreshing to maintain data integrity, its refresh
mechanism allows for higher memory density and lower cost, making it a practical choice for
many applications despite this drawback.
Most of the advanced computer systems are designed using dynamic RAMs.

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TOPIC : INTERFACING

PRESENTED BY: Kanishk Pathania

 One bit of DRAM cell , consists of one

 During write operation ,all the bitlies are

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