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    Eee311 L11

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    Saidul Islam Munna

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    Eee311 L11

    Uploaded by

    Saidul Islam Munna
    6 views17 pages

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    EEE311-L11

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    © © All Rights Reserved

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    6 views17 pages

    Eee311 L11

    Uploaded by

    Saidul Islam Munna

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 17

    EEE311

    Digital Electronics
    Lecture 11 – 27/10/2022

    Dr. MD. AMIRUL ISLAM


    Associate Professor
    EEE, BSMRSTU, Gopalganj
    FLIP-FLOPS (FF)
    AND
    RELATED DEVICES

    2
    NAND GATE LATCH (SR Latch)
    S
    Qn+1 S R Qn+1 n+1 State

    0 0 1 1 INVALID

    0 1 1 0 SET
    n+1
    1 0 0 1 RESET

    R 1 1 Qn n No change / HOLD
    NAND Gate Latch

     The latch is called SR latch because of the inputs (SET and RESET).
     NAND latch inputs are active low. Because, to obtain Q = 1 (or set the latch), S input should be 0.
     To keep the previous state unchanged (memory), both the inputs should be 1 (called resting state).
    3
    NOR Gate Latch

    Two cross-coupled NOR gates can be used as a NOR gate latch. The
    arrangement, shown in the figure below. The output is similar to the NAND
    latch except that the Q and Q outputs have reversed positions.

    4
    Clock Signals and Clocked Flip-flops
    Digital systems can operate either asynchronously or synchronously. In
    asynchronous systems, the outputs of logic circuits can change state any
    time one or more of the inputs change. An asynchronous system is
    generally more difficult to design and troubleshoot than a synchronous
    system.
    In synchronous systems, the exact times at which any output can change
    states are determined by a signal commonly called the clock. This clock
    signal is generally a rectangular pulse train or a square wave.

    5
    PGT and NGT of Clock
    In most digital system, outputs can
    change state only when the clock
    makes a transition. The transitions
    (also called edges) are pointed out
    in the following figure. When the
    clock changes from a 0 to a 1, this
    is called the positive-going The speed of a synchronous digital system
    operates is dependent on the clock. A clock
    transition (PGT); when the clock cycle is measured from one PGT to the next
    PGT (or NGT to NGT). The number of clock
    goes from 1 to 0, this is the cycles that happen in one second (cycles/second
    negative-going transition (NGT). or Hz) is known as frequency (F) of the clock.
    6
    Clocked FF
    Clocked FFs have a clock input that is typically labeled CLK, CK, or CP.

    The control inputs control the WHAT (i.e., what state the output will go to); the
    CLK input determines the WHEN.
    7
    Clocked (PGT) S-R FLIP-FLOP

    8
    Clocked (PGT) S-R FLIP-FLOP

    9
    Clocked (NGT) S-R FLIP-FLOP

    Clocked S-R flip-flop that triggers only on negative-going transitions.


    10
    Clocked S-R Flip-Flop
    CLK S R Qn+1 n+1 State

    0 X X Qn n No change
    1 0 0 1 1 No change
    1 0 1 0 1 RESET
    1 1 0 1 0 SET
    S-R latch
    1 1 1 1 1 INVALID

    The FF loads the control inputs (S and R) only when CLK is HIGH. If CLK is
    LOW, the output does not change. This clocked S-R FF is active HIGH, which
    is opposite to S-R latch.
    https://www.youtube.com/watch?v=dbmSWwu-RGA
    11
    How to create CLK pulse
    The INVERTER produces a delay of
    a few nanoseconds so that the
    transitions of CLK occur a little bit
    after those of CLK. The AND gate
    produces an output spike that is
    HIGH only for the few nanoseconds
    when CLK and are both HIGH. The
    result is a narrow pulse at CLK*,
    which occurs on the PGT of CLK.
    12
    CLOCKED J-K FLIP-FLOP
    A clocked J-K flip-flop that is triggered
    when a PGT (or NGT) occurs. The
    output states of a J-K flip-flop are same
    as S-R flip-flop except for one major
    difference. That is, when J=K=1 appears
    in the input, the output is not INVALID
    anymore. When J=K=1 appears in the
    input, the output toggles (FF will always
    go to its opposite state). This mode of
    operation is called toggle mode.
    13
    J-K FLIP-FLOP - Example

    Initially, Q = 1 is assumed

    14
    Thank You
    J-K FLIP-FLOP – Internal Circiuitry

    S R Qn+1 n+1 State

    0 1 0 0 Qn n No change / Hold

    0 1

    16
    J-K FLIP-FLOP – Internal Circiuitry

    S R Qn+1 n+1 State

    0 1 0 0 Qn n No change / Hold

    1 ?

    17

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