TOPIC 5

FLIP-FLOPS AND SEQUENTIAL

CIRCUITS
Flip-flops are synchronous bistable devices, also known as bistable multivibrators.
In this case, the term synchronous means that the output changes state only at a
specified point on the triggering input called the clock (CLK), which is designated
as a control input, C; that is, changes in the output occur in synchronization with
the clock.

An edge-triggered flip-flop changes state either at the positive edge (rising

edge) or at the negative edge (falling edge) of the clock pulse and is sensitive to
its inputs only at this transition of the clock. Three types of edge triggered flip-
flops covered in this topic are; S-R, D and J-K flip-flops. Although the S-R flip-flop
is not available in IC form, it is the basis for the D and J-K flip-flops. Flip-flops can
be either positive edge-triggered (no bubble at the clock input) or negative edge
triggered (bubble at the clock input). The key to identifying an edge triggered flip-
flop by its logic symbol is the small triangle inside the block at the clock (C) input.
This triangle is called the dynamic input indicator.

The S-R, J-K and D inputs are called synchronous inputs because data on these
inputs are transferred to the flip-flop's output only on the triggering edge of the
clock pulse. On the other hand, the direct set (SET) and clear (CLR) inputs are
called asynchronous inputs, as they are inputs that affect the state of the flip-flop
independent of the clock. For the synchronous operations to work properly, these
asynchronous inputs must both be kept LOW.

1.0 S-R Flip-Flop

The S and R inputs of the S-R flip-flop are called synchronous inputs because data
on these inputs are transferred to the flip-flop’s output only on the triggering edge
of the clock pulse.

Fig. Logic symbol for S-R flip-flop

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1.1 Operation
When S is HIGH and R is LOW, the Q output goes HIGH on the triggering edge of
the clock pulse, and the flip-flop is SET. When S is LOW and R is HIGH, the Q
output goes LOW on the triggering edge of the clock pulse, and the flip-flop is
RESET. When both S and R are LOW, the output does not change from its prior
state. An invalid condition exists when both S and R are HIGH.

Remember, the flip-flop cannot change state except on the triggering edge of the
clock pulse. The S and R inputs can be changed at any time when the clock input
is LOW or HIGH (except for a very short interval around the triggering transition
of the clock) without affecting the output.

S-R flip-flop can be wired from logic gates. NAND and NOR gates can be used to
form S-R flip-flop. An active-HIGH input S-R (SET-RESET) flip-flop is formed with
two cross-coupled NOR gates, as shown in figure (a) below; an active-LOW input
S.R flip-flop is formed with two cross-coupled NAND gates, as shown in figure (b)
below.

Latch R-S Flip Flop Using NOR and NAND Gates

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1.2 Truth Table
Truth table for a positive edge-triggered S-R flip-flop is shown below;

The operation and the truth table for a negative edge triggered S-R flip-flop are
the same as those for a positive edge-triggered device except that the falling edge
of the clock pulse is the triggering edge.

Example:
Determine the Q and Q output waveforms of the flip-flop
shown on the right, for the S, R, and CLK inputs in figure
below. Assume that the positive edge-triggered flip-flop is
initially RESET.

Solution
1. At clock pulse 1, S is LOW and R is LOW, so Q does not change.
2. At clock pulse 2, S is LOW and R is HIGH, so Q remains LOW (RESET).
3. At clock pulse 3, S is HIGH and R is LOW, so Q goes HIGH (SET).
4. At clock pulse 4, S is LOW and R is HIGH, so Q goes LOW (RESET).
5. At clock pulse 5, S is HIGH and R is LOW, so Q goes HIGH (SET).
6. At clock pulse 6, S is HIGH and R is LOW, so Q stays HIGH.

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Once Q is determined, Q is easily found since it is simply the complement of Q .
The resulting waveforms for Q and Q are shown below for the input waveforms.

2.0 D Flip-Flop
The D flip-flop is useful when a single data bit (1 or 0) is to be stored. The addition
of an inverter to an S-R flip-flop creates a basic D flip-flop as shown below, where
a positive edge-triggered type is shown.

(a). Logic Symbol (b). Clocked D Flip-flop logic diagram

2.1 Operation
If there is a HIGH on the D input when a clock pulse is applied, the flip-flop will
set, and the HIGH on the D input is stored by the flip-flop on the positive-going
edge of the clock pulse. If there is a LOW on the D input when the clock pulse is
applied, the flip-flop will reset, and the LOW on the D input is stored by the flip-
flop on the leading edge of the clock pulse. In the SET state, the flip-flop is storing
a 1, and in the RESET state it is storing 0.

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2.2 Truth Table
The logical operation of the positive edge-triggered D flip-flop is summarized
below.

The operation of a negative edge-triggered device is, of course, the same, except
that triggering occurs on the falling edge of the clock pulse. Remember, Q follows
D at the active or triggering clock edge.

Example:
Given the waveforms in figure below for the D input
and the clock, determine the Q output waveform if the
flip-flop starts out RESET.

Solution
The Q output goes to the state of the D input at the time of the positive-going
clock edge. The resulting output is as shown below.

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3.0 J-K Flip-Flop
The J-K flip-flop is versatile and is a widely used type of flip-flop. The functioning
of the J-K flip-flop is identical to that of the S-R flip-flop in the SET, RESET, and
no-change condition of operation. The difference is that the J-K flip-flop has no
invalid state as does the S-R flip-flop.

Fig. Logic symbol for J-K Flip-flop

Figure below show the basic internal logic for a positive edge-triggered J-K flip-
flop. It differs from the S-R edge-triggered flip-flop in that the Q output is
connected back to the input of G2, and the Q output is connected back to the
input of gate G1.

1.1 Operation
If the J and K input are both at 1 and the clock pulse is applied, then the output
will change state, regardless of its previous condition.
If both J and K inputs are at 0 and the clock pulse is applied there will be no
change in the output. There is no indeterminate condition in the operation of JK
flip flop i.e. it has no ambiguous state.
When J = 0 and K = 0; these J and K inputs disable the AND gates, therefore clock
pulse have no effect on the flip flop. In other words, Q returns it last value.

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3.2 Truth Table
The logical operation of the edge-triggered J-K flip-flop is summarized in the truth
table below. Notice that there is no invalid state as there is with an S-R flip-flop.

The truth table for a negative edge-triggered device is identical except that it is
triggered on the falling edge of the clock pulse.

Example: 1
The waveforms in figure below are applied to the
J, K, and clock inputs as indicated. Determine the
Q output, assuming that the flip-flop is initially
RESET.

Solution
1. First, since this is a negative edge-triggered flip-flop, as indicated by the
“bubble” at the clock input, the Q output will change only on the negative-
going edge of the clock pulse.
2. At the first clock pulse, both J and K are HIGH; and because this is a toggle
condition, Q goes HIGH.
3. At clock pulse 2, a no-change condition exists on the inputs, keeping Q at
a HIGH level.
4. When clock pulse 3 occurs, J is LOW and K is HIGH, resulting in a RESET
condition; Q goes LOW.
5. At the clock pulse 4, J is HIGH and K is LOW, resulting in a SET condition;
Q goes HIGH.

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 6. A SET condition still exists on J and K when clock pulse 5 occurs, so Q will
remain HIGH.

The resulting Q waveform is as shown below;

Example: 2
The waveforms in figure below are applied to the flip-flop as shown. Determine
the Q output, starting in the RESET state.

Solution
The Q output assumes the state determined by the states of the J and K inputs at
the positive-going edge (triggering edge) of the clock pulse. A change in J or K
after the triggering edge of the clock has no effect on the output, as shown below.

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4.0 Flip-Flop Operating Characteristics
The operating characteristics mention here applies to all flip-flops regardless of
the particular form of the circuit. They are typically found in data sheets for
integrated circuits. They specify the performance, operating requirements, and
operating limitations of the circuit.
1. Propagation Delay Time - is the interval of time required after an input
signal has been applied for the resulting output change to occur.
2. Set-Up Time - is the minimum interval required for the logic levels to be
maintained constantly on the inputs (J and K, or S and R, or D) prior to the
triggering edge of the clock pulse in order for the levels to be reliably
clocked into the flip-flop.
3. Hold Time - is the minimum interval required for the logic levels to remain
on the inputs after the triggering edge of the clock pulse in order for the
levels to be reliably clocked into the flip-flop.
4. Maximum Clock Frequency - is the highest rate that a flip-flop can be
reliably triggered.
5. Power Dissipation - is the total power consumption of the device.
6. Pulse Widths - are the minimum pulse widths specified by the
manufacturer for the Clock, SET and CLEAR inputs.

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5.0 Flip-flop Applications
5.1 Frequency Division
When a pulse waveform is applied to the clock input of a J-K flip-flop that is
connected to toggle, the Q output is a
square wave with half the frequency of
the clock input. If more flip-flops are
connected together as shown in the
figure, further division of the clock
frequency can be achieved.

The Q output of the second flip-flop is one-fourth the frequency of the original
clock input. This is because the frequency of the clock is divided by 2 by the first
flip-flop, and then divided by 2 again by the second flip-flop. If more flip-flops are
connected this way, the frequency division would be 2 to the power n, where n is
the number of flip-flops.

5.2 Parallel Data Storage

In digital systems, data are normally stored in groups
of bits that represent numbers, codes, or other
information. So, it is common to take several bits of
data on parallel lines and store them simultaneously
in a group of flip-flops. This operation is illustrated in
the figure on the right.

Each of the three parallel data lines is connected to

the D input of a flip-flop. Since all clock inputs are
connected to the same clock, the data on the D inputs
are stored simultaneously by the flip-flops on the
positive edge of the clock. Registers, a group of flip-
flops use for data storage, will be explained in more
detail in a later chapter.

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5.3 Counting
Another very important application of flip-flops is in digital counters.

A counter that counts from 0 to 3 is

illustrated in the timing diagram below.
The two-bit binary sequence repeats
every four clock pulses. When it counts
to 3, it recycles back to 0 to begin the
sequence again.

6.0 Registers
A register is a digital circuit with two basic functions: data storage and data
movement. The storage capability of a register makes it an important type of
memory device.

Basic data movement in shift registers

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6.1 Serial In/Serial Out Shift Register
The serial in/serial out shift register accepts data serially – that is, one bit at a
time on a single line. It produces the stored information on its output also in serial
form. a traditional logic block symbol for an 8-
bit serial in/serial out shift register is shown on
the right. The “SRG 8” designation indicates a
shift register (SRG) with an 8-bit capacity.
Serial In/Serial Out shift register is shown
below;

Example:
Show the states of the 5-bit register in figure below for the specified data input
and clock waveforms. Assume that the register is initially cleared (all 0’s).

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Solution
The first data bit (1) is entered into the register on the first clock pulse and then
shifted from left to right as the remaining bits are entered and shifted. The register
contains Q4Q3Q2Q1Q0 = 11010 after five clock pulses. See figure below;

6.2 Serial In/Parallel Out Shift Register

Data bits are entered serially (right-most bit first) into this type of register in the
same as the above register. The difference is the way in which the data bits are
taken out of the register; in the parallel output register, the output of each stage
is available. Once the data are stored, each bit
appears on its respective output line, and all bits are
available simultaneously, rather than on a bit-by-bit
basis as with the serial output. Figure below shows
a 4-bit serial in/parallel out shift register and its logic
block symbol shown on the right.

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Example:
Show the state of the 4-bit register (SRG 4) for the data input and clock waveforms
in figure below. The register initially contains all 1’s.

Solution
The register contains 0110 after four clock pulses. See figure below.

6.3 Parallel In/Serial Out Shift Register

For a register with parallel data inputs, the bits are entered simultaneously into
their respective stages on parallel lines rather than on a bit-by-bit basis on one
line as with serial data inputs. The serial output is the same as described in serial
in/serial out shift register, once the
data are completely stored in the
register. 4-bit parallel in/serial out
shift register logic symbol is shown on
the right and its logic diagram below;

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Example:
Show the data-output waveform for a 4-bit register with the parallel input data
and the clock and SHIFT / LOAD waveforms given in figure below. Refer above for
its logic diagram.

Solution
On clock pulse 1, the parallel data (D0D1D2D3 = 1010) are loaded into the register,
making Q3 a 0. On clock pulse 2 the 1 from Q2 is shifted onto Q3; on clock pulse 3
the 0 is shifted onto Q3; on clock pulse 4 the last data bit (1) is shifted onto Q3;
and on clock pulse 5, all
data bits have been
shifted out, and only 1’s
remain in the register
(assuming the D input
remains a 1). See figure
on the right.

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6.4 Parallel In/Parallel Out Shift Register
Parallel entry of data, and parallel output of data has been described earlier and
this is employed by the parallel in/parallel out register. Immediately following the
simultaneous entry of all data bits, the bits appear on the parallel outputs.
Figure below shows a parallel in/parallel out shift register.

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