8259 PIC AND 8237 DMA: by Harjot Kaur (2203448) Isha (2203461)

8259 PIC AND 8237
DMA
By Harjot kaur (2203448)
Isha (2203461)
8259 INTERRUPT
CONTROLLER
INTRODUCTION
• Intel 8259 is a Programmable Interrupt Controller (PIC).
• There are 5 hardware interrupts and 2 hardware interrupts in Intel 8085 and
Intel 8086 microprocessors respectively.
• But by connecting Intel 8259 with these microprocessors, we can increase
their interrupt handling capability.
• Intel 8259 combines the multi-interrupt input sources into a single interrupt
output.
• Interfacing of single PIC provides 8 interrupts inputs from IR0-IR7.
Vcc and Gnd:
It is the Power supply and ground pins. +5V power supply isused in
this chip.
D7-0:
For communication with the processor, there are Eight bi-
directional data pins.
RD*:
It is active low-input pin activated by the processor to read the
information status from the 8259.
WR*:
It is an active low-input pin which is activated by the processor to write the
control information to 8259.
CS*
For selecting the chip it is used an active low input pin.
A0:
An address input pin used along with RD* and WR* which is used to identify the
various command words.
IR0-IR7:
There are Eight asynchronous interrupt request inputs. These interrupt requests
can be programmed for level-trigger or edge-triggered mode.
INT:
A strong active high-output pin which interrupts the processor. Always connected
to the INTR interrupt input of 8085. The INT output is only activated when all
the given conditions are satisfied correctly.
CAS:2-0:
These are cascaded lines. Used only when there are multiple 8259s in the system.
The interrupt control system might have a master 8259 and maximum eight
Slave 8259s.
INTA*:
It is termed as an active low-input pin. The 8259 receives the signal from INTA* to the
output of 8085. 8085 sends the three consecutive INTA* signals, the 8259sends a 3-byte
CALL instruction to the 8085 via D7-0 pins. The two bytes termed as second and third
bytes of the CALL instruction contains the ISS address which depends on the IR input of
8259 that is going to be serviced.
SP*/EN*:
SP*/EN* stands for “slave program/enable buffer”. This pinserves dual function. When it
is used as EN* pin it provides an active low-output pin that controls the buffer transceivers
in the buffer mode.
8237 DMA
CONTROLLER
INTRODUCTION
Intel 8237 is a direct memory access (DMA) controller, a part of the 8085
microprocessor family. It enables data transfer between memory and the I/O
with reduced load on the system's main processor by providing the memory
with control signals and memory address information during the DMA transfer
CS Input
CHIP SELECT:Chip Select is an active low input used to select the 8237A as an I/O
device during the Idle cycle. This allows CPU communication on the data bus.
RESET Input
RESET: Reset is an active high input which clears the Command, Status, Request and
Temporary registers.
READY Input
READY: Ready is an input used to extend the memory read and write pulses from the
8237A to accommodate slow memories or I/O peripheral devices.
HLDA Input
HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU
indicates that it has relinquished control of the system busses.
DREQ0 ±DREQ3 Input
DMA REQUEST: The DMA Request lines are individual asynchronous channel request inputs used by peripheral circuits to
obtain DMA service. In fixed Priority, DREQ0 has the highest priority and DREQ3 has the lowest priority. A request is generated
by activating the DREQ line of a channel. DACK will acknowledge the recognition of DREQ signal. Polarity of DREQ is
programmable. Reset initializes these lines to active high. DREQ must be maintained until the corresponding DACK goes active.
DB0 ±DB7
DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data bus. The outputs are enabled in
the Program condition during the I/O Read to output the contents of an Address register, a Status register, the Temporary register
or a Word Count register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle when the CPU is
programming the 8237A control registers. During DMA cycles the most significant 8 bits of the address are output onto the data
bus to be strobed into an external latch by ADSTB. In memory-to-memory operations, data from the memory comes into the
8237A on the data bus during the read-from-memory transfer. In the write-to-memory transfer, the data bus outputs place the data
into the new memory location.
IOR Input/Output
I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input control signal used by the CPU
to read the control registers. In the Active cycle, it is an output control signal used by the 8237A to access data from a peripheral
during a DMA Write transfer.
IOW Input/Output
I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input control signal used by the CPU
to load information into the 8237A. In the Active cycle, it is an output control signal used by the 8237A to load data to the
peripheral during a DMA Read transfer.
A0 ±A3 Input/Output
ADDRESS: The four least significant address lines are bidirectional three-state signals. In the Idle cycle they are inputs and are
used by the CPU to address the register to be loaded or read. In the Active cycle they are outputs and provide the lower 4 bits of
the output address.
A4 ±A7 Output
ADDRESS: The four most significant address lines are three-state outputs and provide 4 bits of address. These lines are enabled
only during the DMA service.
EOP Input/Output
END OF PROCESS: End of Process is an active low bidirectional signal. Information concerning the completion of DMA
services is available at the bidirectional EOP pin.
HRQ Output
HOLD REQUEST: This is the Hold Request to the CPU and is used to request control of the system bus. If the corresponding mask bit
is clear, the presence of any valid DREQ causes 8237A to issue the HRQ.
DACK0 ±DACK3 Output
DMA ACKNOWLEDGE: DMA Acknowledge is used to notify the individual peripherals when one has been granted a DMA cycle. The
sense of these lines is programmable. Reset initializes them to active low.
AEN Output
ADDRESS ENABLE:Address Enable enables the 8-bit latch containing the upper 8 address bits onto the system address bus. AEN can
also be used to disable other system bus drivers during DMA transfers. AEN is active HIGH.
ADSTB Output
ADDRESS STROBE: The active high, Address Strobe is used to strobe the upper address byte into an external latch.
MEMR Output
MEMORY READ: The Memory Read signal is an active low three-state output used to access data from the selected memory location
during a DMA Read or a memory-to-memory transfer.
MEMW Output
MEMORY WRITE: The Memory Write is an active low three-state output used to write data to the selected memory location during a
DMA Write or a memory-to-memory transfer.
THANK YOU

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