EC8791-EMBEDDED & REAL

TIME SYSTEMS
Topic - 1
B.MANIKANDAN
AP/ECE, UCE (BIT)
ANNA UNIVERSITY.
Success Criteria
 Definition of CISC & RISC processor
 Difference between CISC & RISC
processor.
 Architecture of ARM processor

ERTS - Chapter 2 2
 CISC Vs RISC
 Reduced Instruction Set Computer
 Fewer Addressing modes.
 Fewer Instructions available.
 For example, ARM, NEC VR
series.
 Complex Instruction Set Computer
 More Instructions available.
 Many addressing modes.
 For example, Intel x86.

ERTS - Chapter 2 3
Architectural Inheritance
 Used:
 Load- store architecture
 Fixed- length 32- bit instructions
 3 address format
 Rejected:
 Register windows=> Costly
 Use Shadow Registers in ARM
 Delayed branches
 Single cycle execution of all instructions
 Memory Access
 Multiple Cycles when no separate data and instruction
memory support
 Auto-indexing Addressing Modes
Result: RISC with a few CISC features

ERTS - Chapter 2 4
 ARCHITECTURE
The ARM7TDMI processor is a member of the Advanced
RISC machine family of general purpose 32-bit
microprocessor
What does mean ARM7TDMI ?
ARM7 - 32-bit Advanced RISC Machine
T - Thumb architecture extension
Two separate instruction sets, 32-bit ARM
instructions and 16-bit Thumb instructions
D - Debug extension
M - Enhanced multiplier
I - Embedded ICE macrocell extension

ERTS - Chapter 2 5
ARCHITECTURE contd…
• Von Neumann Architecture
• 3-stage pipeline
– fetch, decode, execute

• 32-bit Data Bus

• 32-bit Address Bus
• 37 32-bit registers
• 32-bit ARM instruction set
• 16-bit THUMB instruction set
• 32x8 Multiplier
• Barrel Shifter

ERTS - Chapter 2 6
ARCHITECTURE contd…
• The ARM7TDMI contains a Current Program Status Register
(CPSR), plus five Saved Program Status Registers (SPSRs) for
use by exception handlers.

• These register's functions are:

– Hold information about the most recently performed ALU
operation
– Control the enabling and disabling of interrupts
– Set the processor operating mode

ERTS - Chapter 2 7
Program Status Register
• Condition Code Flags
– The N, Z, C and V bits may be changed as a result of arithmetic and logical
operations, and may be tested to determine whether an instruction
should be executed
• In ARM state, all instructions may be executed conditionally.
• In THUMB state, only the Branch instruction is capable of conditional
execution.

• Control Bits
– The I, F, T and M[4:0]) bits will be changed when an exception arises. If the
processor is operating in a privileged mode, they can also be manipulated
by software.
– T bit:
• This reflects the operating state. When this bit is set, the processor is executing
in THUMB state, otherwise it is executing in ARM state. This is reflected on the
TBIT external signal.
• Note that the software must never change the state of the TBIT in the CPSR. If
this happens, the processor will enter an unpredictable state.

ERTS - Chapter 2 8
Program Status Register
• Control Bits
– Interrupt disable bits:
• The I and F bits are the interrupt disable bits. When set, these
disable the IRQ and FIQ interrupts respectively.

– Mode bits:
• The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits.
These determine the processor's operating mode. Not all
combinations of the mode bits define a valid processor mode.
Only those explicitly described shall be used. The user should
be aware that if any illegal value is programmed into the mode
bits, M[4:0], then the processor will enter an unrecoverable
state. If this occurs, reset should be applied.

ERTS - Chapter 2 9
ARCHITECTURE contd…
• The ARM7TDMI processor has two operating states:
– ARM state which executes 32-bit, word aligned ARM instructions
– THUMB state which can execute 16-bit, halfword aligned THUMB
instructions

• Switching state
– Entering THUMB state
• BX instruction with the state bit (bit 0) set in the operand register.
• Automatically on return from an exception (IRQ, FIQ, ABORT, SWI,…),
if the exception was entered with the processor in THUMB state.
– Entering ARM state
• BX instruction with the state bit clear in the operand register.
• Automatically on the processor taking an exception. In this case, the
PC is placed in the exception mode’s link register.

ERTS - Chapter 2 10
ARCHITECTURE contd…
• The ARM7TDMI supports seven modes of operation:
– User (usr): The normal ARM program execution state
– FIQ (fiq): Designed to support a data transfer or channel process
– IRQ (irq): Used for general-purpose interrupt handling
– Supervisor (svc): Protected mode for the operating system
– Abort mode (abt): Entered after a data or instruction prefetch abort
– System (sys): A privileged user mode for the operating system
– Undefined (und): Entered when an undefined instruction is executed

• Mode changes may be made under software control, or may be brought

about by external interrupts or exception processing.
– Most application programs will execute in User mode. The non-user
modes' known as privileged modes-are entered in order to service
interrupts or exceptions, or to access protected resources.

ERTS - Chapter 2 11
ARM REGISTERS

B.Manikandan, AP/ECE, UCE, BIT 12

15/09/2018
ARM State Vs THUMB State

ERTS - Chapter 2 13
 EXCEPTION
Exceptions arise whenever the normal flow of a program has to be halted temporarily
For example to service an interrupt from a peripheral.

ARM supports 7 types of exception and has a privileged processor mode for each type of
exception.

ARM Exception vectors

Address Exception Mode in Entry

0x00000000 Reset Supervisor
0x00000004 Undefined instruction Undefined
0x00000008 Software Interrupt Supervisor
0x0000000C Abort (prefetch) Abort
0x00000010 Abort (data) Abort
0x00000014 Reserved Reserved
0x00000018 IRQ IRQ
0x0000001C FIQ FIQ
WHEN ARM7 HANDLES EXCEPTION
 Preserves the address of the next instruction in the appropriate Link
Register.
 Copies the CPSR into the appropriate SPSR.
 Forces the CPSR mode bits to a value which depends on the
exception.
 Forces the PC to fetch the next instruction from the relevant
exception vector.
 It may also set the interrupt disable flags to prevent otherwise
unmanageable nesting of exceptions.
If the processor is in THUMB state when an exception occurs, it will
automatically switch into ARM state when the PC is loaded with the
exception vector address.
 On completion, the exception handler.
 Moves the Link Register, minus an offset where appropriate, to the PC.
(The offset will vary depending on the type of exception).
 Copies the SPSR back to the CPSR.
 Clears the interrupt disable flags, if they were set on entry
ARM INSTRUCTION SET

ERTS - Chapter 2
16
ARM INSTRUCTION SET
• All ARM instructions can be conditionally
executed, which means that their execution
may or may not take place depending on
the values of values of the N, Z, C and V
flags in the CPSR

• Every instruction contains a 4-bit condition

code field in bits 31 to 28

ERTS - Chapter 2 17
ARM INSTRUCTION SET
• There are fifteen different conditions, each represented by
a two-character suffix that can be appended to the
instruction's mnemonic.
– A Branch (B in assembly) becomes BEQ for "Branch if Equal", which
means the Branch will only be taken if the Z flag is set.
Code Suffix Flags Meaning
0000 EQ Z set Equal
0001 NE Z clear Not equal
0010 CS C set Unsigned higher or same
0011 CC C clear Unsigned lower
0100 MI N set Negative
0101 PL N clear Positive or zero
0110 VS V set Overflow
0111 VC V clear No overflow
1000 HI C set and Z clear Unsigned higher
1001 LS C clear or Z set Unsigned lower or same
1010 GE N equals V Greater or equal
1011 LT N not equal to V Less than
1100 GT Z clear AND (N equals V) Greater than
1101 LE Z set OR (N not equal to V) Less than or equal
1110 AL (ignored) always

ERTS - Chapter 2 18
ARM INSTRUCTION SET
• All ARM Processors support a branch instruction that allows a conditional
branch forwards or backwards up to 32Mbytes.
– As the Program Counter (PC) is one of the general-purpose registers (register 15), a
branch or jump can also be generated by writing a value to register 15.

• A subroutine call is a variant of the standard branch, the Branch with Link
instruction preserves the address of the instruction after the branch (the
return address) in register 14 (link register or LR).

• A load instruction provides a way to branch anywhere in the 4Gbyte address

space. A 32-bit value is loaded directly from memory into the PC, causing a
branch.

• The ARM7TDMI processor that support the Thumb instruction set also support
a branch instruction (BX) that jumps to a given address, and optionally
switches executing Thumb instructions.

ERTS - Chapter 2 19
ARM INSTRUCTION SET
• List of branch instructions
B, BL Branch, and branch with link
BX Branch and exchange instruction set

• Examples
B label ; branch unconditionally to label
BCC label ; branch to label if carry flag is clear

BEQ label ; branch to label if zero flag is set

MOV PC, #0 ; R15 = 0, branch to location zero

BL func ; subroutine call to function

func MOV PC, LR ; R15=R14, return to instruction after the BL

MOV LR, PC ; store the address of the instruction after the next one into
R14
LDR PC, =func ; load a 32-bit value into the program counter

ERTS - Chapter 2 20
ARM INSTRUCTION SET
• ARM has 16 data processing instructions. Most data processing instructions
take two source operands (Move and Move Not have only one operand) and
store a result in a register (except for the Compare and Test instructions which
only update the condition codes)
– Of the two source operands, one is always a register, the other is called a shifter
operand, and is either an immediate value or a register. If the second operand is a
register value, it may have a shift applied to it before it is used as the operand to the
ALU

ERTS - Chapter 2 21
ARM INSTRUCTION SET
• List of data processing instructions
Assembler Mnemonic OP Code Action
AND 0000 Operand1 AND operand2
EOR 0001 Operand1 EOR operand2
WUB 0010 Operand1 – operand2
RSB 0011 Operand2 operand1
ADD 0100 Operand1 + operand2
ADC 0101 Operand1 + operand2 + carry
SBC 0110 Operand1 – operand2 + carry –1
RSC 0111 Operand2 – operand1 + carry –1
TST 1000 As AND, but results is not written
TEQ 1001 As EOR, but result is not written
CMP 1010 As SUB, but result is not written
CMN 1011 As ADD, but result is not written
ORR 1100 Operand1 OR operand2
MOV 1101 Operand2 (operand1 is ignored)
BIC 1110 Operand1 AND NOT operand2 (Bit clear)
MVN 1111 NOT operand2 (operand1 is ignored)

ERTS - Chapter 2 22
ARM INSTRUCTION SET
• ARM has two classes of multiply instruction
– normal, 32-bit result
– long, 64-bit result
• All multiply instructions take two register operands as the input to the
multiplier
– ARM does not directly support a multiply by constant instruction due to the
efficiency of shift and add, or shift and reverse subtract instructions
– There are two multiply instructions that produce 32-bit results
– MUL, multiplies the values of two registers together, truncates the result to 32 bits,
and stores the result in a third register.
– MLA, multiplies the values of two registers together, adds the value of a third
register, truncates the result to 32 bits, and stores the result into a fourth register
(multiply and accumulate)
MUL R4, R2, R1 ; Set R4 to value of R2 multiplied by R1
MULS R4, R2, R1 ; R4 = R2xR1, set N and Z flags
MLA R7, R8, R9, R3 ; R7 = R8xR9 + R3
ERTS - Chapter 2 23
 ARM INSTRUCTION SET
• There are four multiply instructions that produce 64-bit results (long multiply)
– Two of the variants multiply the values of two registers together and store the 64-
bit result in a third and fourth register. There are a signed (SMULL) and unsigned
(UMULL) variants.
– The remaining two variants multiply the values of two registers together, add the
64-bit value from a third and fourth register and store the 64-bit result back into
those registers (third and fourth). There are also signed (SMLAL) and unsigned
(UMLAL) variants. These instructions perform a long multiply and accumulate

SMULL R4, R8, R2, R3 ; R4 = bits 0 to 31 of R2xR3

; R8 = bits 32 to 63 of R2 x R3
UMULL R6, R8, R0, R1 ; R6, R8 = R0 x R1
UMLAL R5, R8, R0, R1 ; R5, R8 = R0 x R1 + R5, R8

ERTS - Chapter 2 24
 ARM INSTRUCTION SET
• Load and store instruction come in three types:
– load or store the value of a single register
– load and store multiple register values
– swap a register value with the value of a memory location

• Load and store single register

– Load register instructions can load a 32-bit word, a 16-bit halfword or an
8-bit byte from memory into a register.
– Store register instructions can store a 32-bit word, a 16-bit halfword or an
8-bit byte from a register to memory.
– List of load and store single register:
• LDR/STR, Load/Store word
• LDRB/STRB, Load/Store byte
• LDRH/STRH, Load/Store unsigned halfword
• LDRSB, Load signed byte
• LDRSH, Load signed halfword

ERTS - Chapter 2 25
 ARM INSTRUCTION SET
• Load and Store multiple registers
– Load and Store multiple instructions perform a block transfer of any number of the
general purpose registers to or from memory
– Four addressing modes are provided:
• pre-increment
• post-increment
• pre-decrement
• post-decrement
– List of load and store multiple instructions
• LDM, Load multiple
• STM, Store multiple

• Swap a register value with the value of a memory location

– Swap can load a value from a register-specified memory location, store the contents
of a register to the same memory location, then write the loaded value to a register.
– List of semaphore instructions
• SWP, Swap
• SWPB, Swap Byte

ERTS - Chapter 2 26
 ARM INSTRUCTION SET
• The Software Interrupt instruction enters supervisor mode
in a controlled manner:
– The instruction causes the software interrupt trap to be taken,
which effects the mode change
– If the SWI vector address is suitably protected (by external
memory management hardware) from modification by the user, a
fully protected operating system may be constructed.

• The bottom 24 bits of the instruction are ignored by the

processor, and may be used to communicate information
to the supervisor code.

ERTS - Chapter 2 27
THUMB Instructions

28
 THUMB Instructions
• The Thumb instruction set is a subset of the ARM
instruction set, optimized for code density.
• Almost every Thumb instructions have an ARM
instructions equivalent:
– ADD Rd, #Offset8 <> ADDS Rd, Rd, #Offset8

• Inline expansion of Thumb Instruction to ARM

Instruction
– Real time decompression
– Thumb instructions are not actually executed on the core

• The core needs to know whether it is reading

Thumb instructions or ARM instructions.
– Core has two execution states - ARM and Thumb
– Core does not have a mixed 16 and 32 bit instruction set.

ERTS - Chapter 2 29
THUMB Instructions
THUMB: ADD Rd,#Constant
15 0

001 10 Rd Constant

Always Major Minor Destination & Zero extended

condition opcode opcode source register constant

31 28 24 21 20 19 16 15 12 11 8 7 0

1110 00 1 0100 1 0 Rd 0 Rd 0000 Constant

I op1+op2 S
ARM: ADDS Rd, Rd, #Constant

ERTS - Chapter 2 30
 THUMB Instructions
• Thumb supports four types of branch instruction:
– an unconditional branch that allows a forward or backward branch of up
to 2Kbytes
– a conditional branch to allow forward and backward branches of up to 256
bytes
– a branch with link is supported with a pair of instructions that allow
forward and backwards branches of up to 4Mbytes
– a branch and exchange instruction branches to an address in a register and
optionally switches to ARM code execution

• List of branch instructions

– B conditional branch
– B unconditional branch
– BL Branch with link
– BX Branch and exchange instruction set

ERTS - Chapter 2 31
 THUMB Instructions
• Thumb data-processing instructions are a subset
of the ARM data-processing instructions
– All Thumb data-processing instructions set the
condition codes

• List of data-processing instructions

– ADC, Add with Carry
– ADD, Add
– AND, Logical AND
– ASR, Arithmetic shift right
– BIC, Bit clear
– CMN, Compare negative
– CMP, Compare
– EOR, Exclusive OR
– LSL, Logical shift left
– LSR, Logical shift right

ERTS - Chapter 2 32
 THUMB Instructions
• Thumb supports 8 types of load and store register
instructions

• List of load and store register instructions

– LDR Load word
– LDRB Load unsigned byte
– LDRH Load unsigned halfword
– LDRSB Load signed byte
– LDRSH Load signed halfword
– STR Store word
– STRB Store byte
– STRH Store halfword
ERTS - Chapter 2 33
 THUMB Instructions
• Thumb supports four types of load and store multiple
instructions

• Two (a load and store) are designed to support block copy

• The other two instructions (called PUSH and POP)
implement a full descending stack, and the stack pointer is
used as the base register

• List of load and store multiple instructions

– LDM Load multiple
– POP Pop multiple
– PUSH Push multiple
– STM Store multiple

ERTS - Chapter 2 34