Gate Level Modeling

GATE-LEVEL MODELING
• A logic circuit can be designed by use of logic gates. Verilog

supports basic logic gates as predefined primitives. These primitives
are instantiated like modules except that they are predefined in
Verilog and do not need a module definition.
• There are two classes of basic gates: and/or gates and buf/not gates.
AND/OR GATES
• And/or gates have
one scalar output
and multiple scalar
inputs.
TRUTH
TABLE OF
AND/OR
GATES
BUF/NOT GATES
• Buf/not gates have one scalar
input and one or more scalar
outputs.
• Notice that these gates can

have multiple outputs but
exactly one input, which is
the last terminal in the port
list.
TRUTH
TABLE OF
BUF/NOT
GATES
BUFIF/NOTIF GATES
• Gates with an additional
control signal on buf and not
gates are also available.
• These gates propagate only if
their control signal is
asserted.
• They propagate z if their
control signal is deasserted.
TRUTH TABLE
OF
BUFIF/NOTIF
GATES
ARRAY OF INSTANCES
• There are many situations when repetitive instances are required. These
instances differ from each other only by the index of the vector to which
they are connected. To simplify specification of such instances, Verilog
HDL allows an array of primitive instances to be defined.
• Example:wire [3:0] OUT, IN1, IN2;
// basic gate instantiations.
nand n_gate[3:0](OUT, IN1, IN2);
// This is equivalent to the following 4 instantiations
nand n_gate0(OUT[0], IN1[0], IN2[0]);
GATE DELAYS
• Gate delays allow the Verilog user to specify delays through the
logic circuits. Pin-to-pin delays can also be specified in Verilog.
• There are 3 main delays:
Rise
Fall
Turn-off
RISE DELAY
• The rise delay is associated with a gate output transition to a 1 from
another value.
FALL DELAY
• The fall delay is associated with a gate output transition to a 0 from
another value.
TURN-OFF DELAY
• The turn-off delay is associated with a gate output transition to the

high impedance value (z) from another value.
• NOTE:
Three types of delay specifications are allowed.
If only one delay is specified, this value is used for all transitions.
If two delays are specified, they refer to the rise and fall delay
values. The turn-off delay is the minimum of the two delays.
If all three delays are specified, they refer to rise, fall, and turn-off
delay values. If no delays are specified, the default value is zero.
EXAMPLES OF DELAYS
• and #(5) a1(out, i1, i2); //Delay of 5 for all transitions, i.e., Rise =
5, Fall = 5, Turn-off = 5
• and #(4,6) a2(out, i1, i2); // Rise = 4, Fall = 6, Turn-off=4
• bufif0 #(3,4,5) b1 (out, in, control); // Rise = 3, Fall = 4, Turn-off

=5
MIN/TYP/MAX VALUES
• For each type of delay- rise, fall, and turn-off,three values- min, typ,
and max, can be specified. Any one value can be chosen at the start
of the simulation.
• Min/typ/max values are used to model devices whose delays vary
within a minimum and maximum range because of the IC
fabrication process variations.
• Min value-The min value is the minimum delay value that the
designer expects the gate to have.
• Typ value-The typ value is the typical delay value that the designer
expects the gate to have.
• Max value-The max value is the maximum delay value that the
designer expects the gate to have.
• Min, typ, or max values can be chosen at Verilog run time.
EXAMPLES OF
MIN/TYP/MAX VALUES
• // One delay
// if mindelays, delay= 4
// if typdelays, delay= 5
// if +maxdelays, delay= 6
and #(4:5:6) a1(out, i1, i2);
• // Two delays
// if +mindelays, rise= 3, fall= 5, turn-off = min(3,5)
// if +typdelays, rise= 4, fall= 6, turn-off = min(4,6)
// if +maxdelays, rise= 5, fall= 7, turn-off = min(5,7)
and #(3:4:5, 5:6:7) a2(out, i1, i2);
• // Three delays
// if +mindelays, rise= 2 fall= 3 turn-off = 4
// if +typdelays, rise= 3 fall= 4 turn-off = 5
// if +maxdelays, rise= 4 fall= 5 turn-off = 6
and #(2:3:4, 3:4:5, 4:5:6) a3(out, i1,i2);
EXAMPLE OF DELAYS
• Let us consider a simple example to illustrate the use of gate delays
to model timing in the logic circuits.
• A simple module called D implements the following logic
equations:
out = (a*b) + c
• Verilog Definition for Module D with Delay
// Define a simple combination module called D
module D (out, a, b, c);
// I/O port declarations
output out; input a,b,c;
// Internal nets
wire e;
// Instantiate primitive gates to build the circuit
and #(5) a1(e, a, b); //Delay of 5 on gate a1
or #(4) o1(out, e,c); //Delay of 4 on gate o1 endmodule
• Stimulus for Module D with Delay
// Stimulus (top-level module)
module stimulus;
// Declare variables
reg A, B, C;
wire OUT;
// Instantiate the module D
D d1( OUT, A, B, C);
// Stimulate the inputs. Finish the simulation at 40 time units.
initial begin
A= 1'b0; B= 1'b0; C= 1'b0;
#10 A= 1'b1; B= 1'b1; C= 1'b1;
#10 A= 1'b1; B= 1'b0; C= 1'b0;
#20 $finish;
end
endmodule
• Waveform for D module with delays:
THANK YOU

Gate Level Modeling

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GATE-LEVEL MODELING

• A logic circuit can be designed by use of logic gates. Verilog

• Notice that these gates can

• The turn-off delay is associated with a gate output transition to the

• and #(4,6) a2(out, i1, i2); // Rise = 4, Fall = 6, Turn-off=4

• bufif0 #(3,4,5) b1 (out, in, control); // Rise = 3, Fall = 4, Turn-off

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