Analysis and Design of Digital Circuits

With HDL(22EC34)
Gate-Level and Data Flow Modelling

1
Content
1. Basic Verilog gate primitives

2. Description of and/or and buf/not type gates

3. Rise, fall and turn-off delays

4. Min, max, and typical delays

5. Continuous assignments

6. Delay specification

7. Expressions, Operators, operands

8. Operator types
Learning Objectives

◼ Identify logic gate primitives provided in Verilog.

◼ Understand instantiation of gates, gate symbols,
and truth tables for and/or and buf/not type
gates.
◼ Understand how to construct a Verilog
description from the logic diagram of the circuit.
◼ Describe rise, fall, and turn-off delays in the
gate-level design and Explain min, max, and
type delays in the gate-level design
Learning Objectives
◼ Describe the continuous assignment (assign)
statement, restrictions on the assign
statement, and the implicit continuous
assignment statement.
◼ Explain assignment delay, implicit assignment
delay, and net declaration delay for continuous
◼ assignment statements and Define
expressions, operators, and operands.
◼ Use dataflow constructs to model practical
digital circuits in Verilog
 Gate Types
◼ A logic circuit can be designed by use of logic
gates.
◼ Verilog supports basic logic gates as
predefined primitives.
◼ These primitives are instantiated like modules
except that they are predefined in Verilog and
do not need a module definition.
◼ All logic circuits can be designed by using
basic gates. There are two classes of basic
gates: and/or gates and buf/not gates.
 And/Or Gates
◼ And/or gates have one scalar output and multiple scalar
inputs.
◼ The first terminal in the list of gate terminals is an output
and the other terminals are inputs.
◼ The output of a gate is evaluated as soon as one of the
inputs changes.
◼ The and/or gates available in Verilog are: and, or, xor,
nand, nor, xnor.
◼ The corresponding logic symbols for these gates are
shown in Figure 3-1. Consider the gates with two inputs.
◼ The output terminal is denoted by out. Input terminals
are denoted by i1 and i2.
 Gate Instantiation of And / Or
◼ wire OUT, IN1, IN2;
Gates
◼ // basic gate instantiations.
◼ and a1(OUT, IN1, IN2);
◼ nand na1(OUT, IN1, IN2);
◼ or or1(OUT, IN1, IN2);
◼ nor nor1(OUT, IN1, IN2);
◼ xor x1(OUT, IN1, IN2);
◼ xnor nx1(OUT, IN1, IN2);
◼ // More than two inputs; 3 input nand gate
◼ nand na1_3inp(OUT, IN1, IN2, IN3);
◼ // gate instantiation without instance name
◼ and (OUT, IN1, IN2); // legal gate instantiation
Truth Table
 Buf/Not Gates
◼ Buf/not gates have one scalar input and one or more scalar
outputs. The last terminal in the port list is connected
◼ to the input. Other terminals are connected to the outputs. We
will discuss gates that have one input and one
◼ output. Two basic buf/not gate primitives are provided in
Verilog.
◼ The symbols for these logic gates are shown in Figure 3-2.
 Example 3-2 Gate Instantiations of Buf/Not
Gates
◼ These gates are instantiated in Verilog as shown Example 3-
2. Notice that these gates can have multiple outputs but
exactly one input, which is the last terminal in the port list.
◼ // basic gate instantiations.
◼ buf b1(OUT1, IN);
◼ not n1(OUT1, IN);
◼ // More than two outputs
◼ buf b1_2out(OUT1, OUT2, IN);
◼ // gate instantiation without instance name
◼ not (OUT1, IN); // legal gate instantiation
◼ Truth tables for gates with one input and one output are
shown in Table 3-2.
 Bufif/notif
◼ Gates with an additional control signal on buf and not
gates are also available.
◼ These gates propagate only if their control signal is
asserted. They propagate z if their control signal is
deasserted. Symbols for bufif/notif are shown in Figure
3-3.
 Example 3-3 Gate Instantiations of
Bufif/Notif Gates
◼ //Instantiation of bufif gates.
◼ bufif1 b1 (out, in, ctrl);
◼ bufif0 b0 (out, in, ctrl);
◼ //Instantiation of notif gates
◼ notif1 n1 (out, in, ctrl);
◼ notif0 n0 (out, in, ctrl);
 Array of Instances
◼ There are many situations when repetitive
instances are required.
◼ These instances differ from each other only by
the index of the vector to which they are
connected.
◼ To simplify specification of such instances,
Verilog HDL allows an array of primitive
instances to be defined.
 Simple Array of Primitive Instances
◼ wire [7:0] OUT, IN1, IN2;
◼ // basic gate instantiations.
◼ nand n_gate[7:0](OUT, IN1, IN2);
◼ // This is equivalent to the following 8 instantiations
◼ nand n_gate0(OUT[0], IN1[0], IN2[0]);
◼ nand n_gate1(OUT[1], IN1[1], IN2[1]);
◼ nand n_gate2(OUT[2], IN1[2], IN2[2]);
◼ nand n_gate3(OUT[3], IN1[3], IN2[3]);
◼ nand n_gate4(OUT[4], IN1[4], IN2[4]);
◼ nand n_gate5(OUT[5], IN1[5], IN2[5]);
◼ nand n_gate6(OUT[6], IN1[6], IN2[6]);
◼ nand n_gate7(OUT[7], IN1[7], IN2[7]);
Gate-level multiplexer
Logic Diagram for Multiplexer
 Example 3-5 Verilog Description of
Multiplexer
◼ // Module 4-to-1 multiplexer. Port list is taken exactly
from// the I/O diagram.
◼ module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
◼ // Port declarations from the I/O diagram
◼ output out;
◼ input i0, i1, i2, i3;
◼ input s1, s0;
◼ // Internal wire declarations
◼ wire s1n, s0n;
◼ wire y0, y1, y2, y3;
◼ // Gate instantiations
◼ // Create s1n and s0n signals.
◼ not (s1n, s1);
◼ not (s0n, s0);
◼ // 3-input and gates instantiated
◼ and (y0, i0, s1n, s0n);
◼ and (y1, i1, s1n, s0);
◼ and (y2, i2, s1, s0n);
◼ and (y3, i3, s1, s0);
◼ // 4-input or gate instantiated
◼ or (out, y0, y1, y2, y3);
 Stimulus for Multiplexer
◼ // Define the stimulus module (no ports)
◼ module stimulus;
◼ // Declare variables to be connected// to inputs
◼ reg IN0, IN1, IN2, IN3;
◼ reg S1, S0;
◼ // Declare output wire
◼ wire OUTPUT;
◼ // Instantiate the multiplexer
◼ mux4_to_1 mymux(OUTPUT, IN0, IN1, IN2, IN3, S1,
S0);
◼ // Stimulate the inputs
◼ // Define the stimulus module (no ports)
◼ initial
◼ begin
◼ // set input lines
◼ IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
◼ #1 $display("IN0= %b, IN1= %b, IN2= %b, IN3=
%b\n",IN0,IN1,IN2,IN3);
◼ // choose IN0
◼ S1 = 0; S0 = 0;
◼ #1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1,
S0, OUTPUT);
◼ // choose IN1
◼ S1 = 0; S0 = 1;
◼ #1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1,
S0, OUTPUT);
◼ // choose IN2
◼ S1 = 1; S0 = 0;
◼ #1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1,
S0, OUTPUT);
◼ // choose IN3
◼ S1 = 1; S0 = 1;
◼ #1 $display("S1 = %b, S0 = %b, OUTPUT = %b \n", S1,
S0, OUTPUT);
◼ end
◼ endmodule
◼ The output of the simulation is shown below.
Each combination of the select signals is
tested.
◼ IN0= 1, IN1= 0, IN2= 1, IN3= 0
◼ S1 = 0, S0 = 0, OUTPUT = 1
◼ S1 = 0, S0 = 1, OUTPUT = 0
◼ S1 = 1, S0 = 0, OUTPUT = 1
◼ S1 = 1, S0 = 1, OUTPUT = 0
1-bit Full Adder
◼ Example 3-7 Verilog Description for 1-bit
Full Adder
◼ // Define a 1-bit full adder
◼ module fulladd(sum, c_out, a, b, c_in);
◼ // I/O port declarations
◼ output sum, c_out;
◼ input a, b, c_in;
◼ // Internal nets
◼ wire s1, c1, c2;
◼ // Instantiate logic gate primitives
◼ xor (s1, a, b);
◼ and (c1, a, b);
◼ xor (sum, s1, c_in);
◼ and (c2, s1, c_in);
◼ xor (c_out, c2, c1);
◼ endmodule
4-bit Ripple Carry Full Adder
◼ Example 3-8 Verilog Description for 4-bit
Ripple Carry Full Adder
◼ // Define a 4-bit full adder
◼ module fulladd4(sum, c_out, a, b, c_in);
◼ // I/O port declarations
◼ output [3:0] sum;
◼ output c_out;
◼ input[3:0] a, b;
◼ input c_in;
◼ // Internal nets
◼ wire c1, c2, c3;
◼ // Instantiate four 1-bit full adders.
◼ fulladd fa0(sum[0], c1, a[0], b[0], c_in);
◼ fulladd fa1(sum[1], c2, a[1], b[1], c1);
◼ fulladd fa2(sum[2], c3, a[2], b[2], c2);
◼ fulladd fa3(sum[3], c_out, a[3], b[3], c3);
◼ endmodule
◼ Example 3-9 Stimulus for 4-bit Ripple
Carry Full Adder
◼ // Define the stimulus (top level module)
◼ module stimulus;
◼ // Set up variables
◼ reg [3:0] A, B;
◼ reg C_IN;
◼ wire [3:0] SUM;
◼ wire C_OUT;
◼ // Instantiate the 4-bit full adder. call it FA1_4
◼ fulladd4 FA1_4(SUM, C_OUT, A, B, C_IN);
◼ // Set up the monitoring for the signal values
◼ initial
◼ begin
◼ $monitor($time," A= %b, B=%b, C_IN= %b, --
- C_OUT= %b, SUM= %b\n",
◼ A, B, C_IN, C_OUT, SUM);
◼ End
◼ // Stimulate inputs
◼ initial
◼ Begin
◼ A = 4'd0; B = 4'd0; C_IN = 1'b0;
#5 A = 4'd3; B = 4'd4;
◼ #5 A = 4'd2; B = 4'd5;
◼ #5 A = 4'd9; B = 4'd9;
◼ #5 A = 4'd10; B = 4'd15;
◼ #5 A = 4'd10; B = 4'd5; C_IN = 1'b1;
◼ end
◼ endmodule
◼ The output of the simulation is shown below.
◼ 0 A= 0000, B=0000, C_IN= 0, --- C_OUT= 0, SUM=
0000
◼ 5 A= 0011, B=0100, C_IN= 0, --- C_OUT= 0, SUM=
0111
◼ 10 A= 0010, B=0101, C_IN= 0, --- C_OUT= 0, SUM=
0111
◼ 15 A= 1001, B=1001, C_IN= 0, --- C_OUT= 1, SUM=
0010
◼ 20 A= 1010, B=1111, C_IN= 0, --- C_OUT= 1, SUM=
1001
◼ 25 A= 1010, B=0101, C_IN= 1,--- C_OUT= 1, SUM=
0000
 Gate Delays
◼ Until now, circuits are described without any
delays (i.e., zero delay). In real circuits, logic
gates have delays associated with them.
◼ Gate delays allow the Verilog user to specify
delays through the logic circuits.
◼ Pin-to-pin delays can also be specified in
Verilog.
◼ There are three types of delays from the
inputs to the output of a primitive gate : Rise,
Fall, and Turn-off Delays
◼ Rise delay
◼ The rise delay is associated with a gate
output transition to a 1 from another value.

◼ Fall delay
◼ The fall delay is associated with a gate output
transition to a 0 from another value.
 Turn-off delay
◼ The turn-off delay is associated with a gate output transition
to the high impedance value (z) from another value.
◼ If the value changes to x, the minimum of the three delays
is considered.
◼ Three types of delay specifications are allowed. If only one
delay is specified, this value is used for all transitions.
◼ If two delays are specified, they refer to the rise and fall
delay values. The turn-off delay is the minimum of the two
delays.
◼ If all three delays are specified, they refer to rise, fall, and
turn-off delay values.
◼ If no delays are specified, the default value is zero.
Examples of delay specification are shown in Example 3-
10.
 Example 3-10 Types of Delay
Specification
◼ // Delay of delay_time for all transitions
◼ and #(delay_time) a1(out, i1, i2);
◼ // Rise and Fall Delay Specification.
◼ and #(rise_val, fall_val) a2(out, i1, i2);
◼ // Rise, Fall, and Turn-off Delay Specification
◼ bufif0 #(rise_val, fall_val, turnoff_val) b1 (out,
in, control);
◼ Examples of delay specification are shown
below.
◼ and #(5) a1(out, i1, i2); //Delay of 5 for all
transitions
◼ and #(4,6) a2(out, i1, i2); // Rise = 4, Fall = 6
◼ bufif0 #(3,4,5) b1 (out, in, control); // Rise = 3,
Fall = 4, Turn-off= 5
 Min/Typ/Max Values
◼ Verilog provides an additional level of control for each
type of delay mentioned above.
◼ For each type of delay? rise, fall, and turn-off? three
values, min, typ, and max, can be specified.
◼ Any one value can be chosen at the start of the
simulation.
◼ Min/typ/max values are used to model devices whose
delays vary within a minimum and maximum range be
◼ Min value:- The min value is the minimum delay value
that the designer expects the gate to have.
◼ Typ val:- The typ value is the typical delay value that the
designer expects the gate to have.
◼ Max value
◼ The max value is the maximum delay value that the
designer expects the gate to have.
◼ Min, typ, or max values can be chosen at Verilog run
time.
◼ Method of choosing a min/typ/max value may vary for
different simulators or operating systems. (For Verilog-
XL , the values are chosen by specifying options
+maxdelays, +typdelays, and +mindelays at run time.
◼ If no option is specified, the typical delay value is the
default).
◼ This allows the designers the flexibility of building three
delay values for each transition into their design.
◼ The
◼ designer can experiment with delay values without
modifying the design.
◼ Example 3-11 Min, Max, and Typical Delay
Values
◼ // One delay
◼ // if +mindelays, delay= 4
◼ // if +typdelays, delay= 5
◼ // if +maxdelays, delay= 6
◼ and #(4:5:6) a1(out, i1, i2);
◼ // Two delays
◼ // if +mindelays, rise= 3, fall= 5, turn-off = min(3,5)
◼ // if +typdelays, rise= 4, fall= 6, turn-off = min(4,6)
◼ // if +maxdelays, rise= 5, fall= 7, turn-off = min(5,7)
◼ and #(3:4:5, 5:6:7) a2(out, i1, i2);
◼ // Three delays
◼ // if +mindelays, rise= 2 fall= 3 turn-off = 4
◼ // if +typdelays, rise= 3 fall= 4 turn-off = 5
◼ // if +maxdelays, rise= 4 fall= 5 turn-off = 6
◼ and #(2:3:4, 3:4:5, 4:5:6) a3(out, i1,i2);
◼ Examples of invoking the Verilog-XL simulator with the
command-line options are shown below. Assume that
the module with delays is declared in the file test.v.
◼ //invoke simulation with maximum delay
◼ > verilog test.v +maxdelays
◼ //invoke simulation with minimum delay
◼ > verilog test.v +mindelays
◼ //invoke simulation with typical delay
◼ > verilog test.v +typdelays
 Delay Example
◼ Let us consider a simple example to illustrate the use of
gate delays to model timing in the logic circuits.
◼ A simple module called D implements the following logic
equations:
◼ out = (a b) + c
◼ The gate-level implementation is shown in Module D
(Figure 3-8). The module contains two gates with delays
of 5 and 4 time units.
◼ Example 3-12 Verilog Definition for Module D with
Delay
◼ // Define a simple combination module called D
◼ module D (out, a, b, c);
◼ // I/O port declarations
◼ output out;
◼ input a,b,c;
◼ // Internal nets
◼ wire e;
◼ // Instantiate primitive gates to build the circuit
◼ and #(5) a1(e, a, b); //Delay of 5 on gate a1
◼ or #(4) o1(out, e,c); //Delay of 4 on gate o1
◼ endmodule
◼ Example 3-13 Stimulus for Module D with Delay
◼ // Stimulus (top-level module)
◼ module stimulus;
◼ // Declare variables
◼ reg A, B, C;
◼ wire OUT;
◼ // Instantiate the module D
◼ D d1( OUT, A, B, C);
◼ // Stimulate the inputs. Finish the simulation at 40 time units.
◼ initial
◼ begin
◼ A= 1'b0; B= 1'b0; C= 1'b0;
◼ #10 A= 1'b1; B= 1'b1; C= 1'b1;
◼ #10 A= 1'b1; B= 1'b0; C= 1'b0;
◼ #20 $finish;
◼ end
◼ endmodule
◼ The waveforms from the simulation are shown in Figure
3-9 to illustrate the effect of specifying delays on
◼ gates.
◼ The waveforms are not drawn to scale. However,
simulation time at each transition is specified below the
◼ transition.
◼ The outputs E and OUT are initially unknown.
◼ At time 10, after A, B, and C all transition to 1, OUT
transitions to 1 after a delay of 4 time units and E
changes value to 1 after 5 time units.
◼ At time 20, B and C transition to 0. E changes value to 0
after 5 time units, and OUT transitions to 0, 4 time units
after E changes.
Data Flow Modeling
◼ For small circuits, the gate-level modeling approach
works very well because the number of gates is limited
and the designer can instantiate and connects every
gate individually.
◼ Also, gate-level modeling is very intuitive to a designer
with a basic knowledge of digital logic design. However,
in complex designs the number of gates is very large.
◼ Thus, designers can design more effectively if they
concentrate on implementing the function at a level of
abstraction higher than gate level.
◼ Dataflow modeling provides a powerful way to implement
a design.
◼ Verilog allows a circuit to be designed in terms of the
data flow between registers and how a design processes
data rather than instantiation of individual gates.
 Continuous Assignments
◼ A continuous assignment is the most basic statement in
dataflow modeling, used to drive a value onto a net. This
◼ assignment replaces gates in the description of the
circuit and describes the circuit at a higher level of
abstraction.
◼ The assignment statement starts with the keyword
assign. The syntax of an assign statement is as follows.
◼ continuous_assign ::= assign [ drive_strength ] [ delay3 ]
list_of_net_assignments ;
◼ list_of_net_assignments ::= net_assignment { ,
net_assignment }
◼ net_assignment ::= net_lvalue = expression
◼ The default value for drive strength is strong1 and strong0. The
delay value is also optional and can be used to specify delay on
the assign statement. This is like specifying delays for gates.
Continuous assignments have the following characteristics:
◼ The left hand side of an assignment must always be a scalar or
vector net or a concatenation of scalar and vector nets. It cannot
be a scalar or vector register.
◼ Continuous assignments are always active. The assignment
expression is evaluated as soon as one of the right hand- side
operands changes and the value is assigned to the left-hand-side
net.
◼ The operands on the right-hand side can be registers or nets or
function calls. Registers or nets can be scalars or vectors.
◼ Delay values can be specified for assignments in terms of time
units. Delay values are used to control the time when a net is
assigned the evaluated value.
◼ This feature is similar to specifying delays for gates. It is very
useful in modeling timing behavior in real circuits.
◼ Example 3-14 Examples of Continuous
Assignment
◼ // Continuous assign. out is a net. i1 and i2 are nets.
◼ assign out = i1 & i2;
◼ // Continuous assign for vector nets. addr is a 16-bit
vector net // addr1 and addr2 are 16-bit vector
registers.
◼ assign addr[15:0] =addr1_bits[15:0]^addr2_bits[15:0];
◼ // Concatenation. Left-hand side is a concatenation of
a scalar// net and a vector net.
◼ assign {c_out, sum[3:0]} = a[3:0] + b[3:0] + c_in;
 Implicit Continuous Assignment
◼ Instead of declaring a net and then writing a continuous
assignment on the net, Verilog provides a shortcut by which
a continuous assignment can be placed on a net when it is
declared. There can be only one implicit declaration
◼ assignment per net because a net is declared only once.
◼ In the example below, an implicit continuous assignment is
contrasted with a regular continuous assignment.
◼ //Regular continuous assignment
◼ wire out;
◼ assign out = in1 & in2;
◼ //Same effect is achieved by an implicit continuous
assignment
◼ wire out = in1 & in2;
 Implicit Net Declaration
◼ If a signal name is used to the left of the
continuous assignment, an implicit net
declaration will be inferred for that signal name.
◼ If the net is connected to a module port, the
width of the inferred net is equal to the width of
the module port.
◼ wire i1, i2;
◼ assign out = i1 & i2; //Note that out was not
declared as a wire
◼ //but an implicit wire declaration for out
◼ //is done by the simulator
 Delays
◼ Delay values control the time between the change in a right-hand-side
operand and when the new value is assigned to the left-hand side.
◼ Three ways of specifying delays in continuous assignment statements
are regular assignment delay, implicit continuous assignment delay,
and net declaration delay.
 Regular Assignment Delay
◼ The first method is to assign a delay value in a
continuous assignment statement.
◼ The delay value is specified after the keyword assign.
◼ Any change in values of in1 or in2 will result in a delay of
10 time units before re-computation of the expression in1
& in2, and the result will be assigned to out.
◼ If in1 or in2 changes value again before 10 time units
when the result propagates to out, the values of in1 and
in2 at the time of re-computation are considered.
◼ This property is called inertial delay. An input pulse that
is shorter than the delay of the assignment statement
does not propagate to the output.
◼ assign #10 out = in1 & in2; // Delay in a continuous assign
◼ 1. When signals in1 and in2 go high at time 20, out goes to a
high 10 time units later (time = 30).
◼ 2. When in1 goes low at 60, out changes to low at 70.
◼ 3. However, in1 changes to high at 80, but it goes down to low
before 10 time units have elapsed.
◼ 4. Hence, at the time of re-computation, 10 units after time 80,
in1 is 0. Thus, out gets the value 0. A pulse of width less than
the specified assignment delay is no propagated to the
output.
 Implicit Continuous Assignment Delay
◼ An equivalent method is to use an implicit
continuous assignment to specify both a delay and
an assignment on the net.
◼ //implicit continuous assignment delay
◼ wire #10 out = in1 & in2;
◼ //same as
◼ wire out;
◼ assign #10 out = in1 & in2;
◼ The declaration above has the same effect as
defining a wire out and declaring a continuous
assignment on out.
◼
Net Declaration Delay
A delay can be specified on a net when it is declared
without putting a continuous assignment on the net. If a
delay is specified on a net out, then any value change
applied to the net out is delayed accordingly.
◼ Net declaration delays can also be used in gate-level
modeling.
◼ //Net Delays
◼ wire # 10 out;
◼ assign out = in1 & in2;
◼ //The above statement has the same effect as the
following.
◼ wire out;
◼ assign #10 out = in1 & in2;
 Expressions, Operators, and
Operands
◼ Dataflow modeling describes the design in terms of
expressions instead of primitive gates.
◼ Expressions, operators, and operands form the basis of
dataflow modeling.
◼ Expressions are constructs that combine operators and
operands to pro
◼ // Examples of expressions. Combines operands and
operators
◼ a^b
◼ addr1[20:17] + addr2[20:17]
◼ in1 | in2
 Operands
◼ Operands can be any one of the data types defined,
Data Types.
◼ Some constructs will take only certain types of
operands.
◼ Operands can be constants, integers, real numbers,
nets, registers, times, bit-select (one bit of vector net
or a vector register), part-select (selected bits of the
vector net or register vector), and memories or
function calls
◼ Examples: integer count, final_count;
◼ final_count = count + 1;//count is an integer operand
◼ real a, b, c;
◼ c = a - b; //a and b are real operands
◼ reg [15:0] reg1, reg2;
◼ reg [3:0] reg_out;
◼ reg_out = reg1[3:0] ^ reg2[3:0];//reg1[3:0] and
reg2[3:0] are //part-select register operands
◼ reg ret_value;
◼ ret_value=calculate_parity(A,B);//calculate_p
arity is a//function type operand
 Operators
◼ Operators act on the operands to produce
desired results.
◼ Verilog provides various types of operators.
Operator
◼ Types d1 && d2 // && is an operator on
operands d1 and d2.
◼ !a[0] // ! is an operator on operand a[0]
◼ B >> 1 // >> is an operator on operands B
and 1
Operator Types
◼ Arithmetic
◼ There are five arithmetic operators in Verilog.
◼ module Arithmetic (A, B, Y1, Y2, Y3, Y4, Y5);
◼ input [2:0] A, B;
◼ output [3:0] Y1;
◼ output [4:0] Y3;
◼ output [2:0] Y2, Y4, Y5;
◼ reg [3:0] Y1;
◼ reg [4:0] Y3;
◼ reg [2:0] Y2, Y4, Y5;
◼ always @(A or B)
◼ begin
◼ Y1=A+B;//addition
◼
Y2=A-B;//subtraction
◼
Y3=A*B;//multiplication
◼
Y4=A/B;//division
◼
Y5=A%B;//modulus of A divided by B
◼ end
◼ endmodule
Logical and Relational Operators
Equality and Bitwise Operators
◼ Equality and inequality
◼ Equality and inequality operators are used in exactly the same way
as relational operators and return a true or false indication
depending on whether any two operands are equivalent or not.
◼ module Equality (A, B, Y1, Y2, Y3);
◼ input [2:0] A, B;
◼ output Y1, Y2;
◼ output [2:0] Y3;
◼ reg Y1, Y2;
◼ reg [2:0] Y3;
◼ always @(A or B)
◼ begin
◼ Y1=A==B;//Y1=1 if A equivalent to B
◼ Y2=A!=B;//Y2=1 if A not equivalent to B
◼ if (A==B)//parenthesis needed
◼ Y3=A;
◼ else
◼ Y3=B;
◼ end
◼ endmodule
◼ Bit-wise
◼ Logical bit-wise operators take two single or multiple operands on
either side of the operator and return a single bit result. The only
exception is the NOT operator, which negates the single operand that
follows. Verilog does not have the equivalent of NAND or NOR
operator, their funstion is implemented by negating the AND and OR
operators.
◼ module Bitwise (A, B, Y);
◼ input [6:0] A;
◼ input [5:0] B;
◼ output [6:0] Y;
◼ reg [6:0] Y;
◼ always @(A or B)
◼ begin
◼ Y(0)=A(0)&B(0); //binary AND
◼ Y(1)=A(1)|B(1); //binary OR
◼ Y(2)=!(A(2)&B(2)); //negated AND
◼ Y(3)=!(A(3)|B(3)); //negated OR
◼ Y(4)=A(4)^B(4); //binary XOR
◼ Y(5)=A(5)~^B(5); //binary XNOR
◼ Y(6)=!A(6); //unary negation
◼ end
◼ endmodule
◼ Reduction
◼ Verilog has six reduction operators, these operators accept a single
vectored (multiple bit) operand, performs the appropriate bit-wise
reduction on all bits of the operand, and returns a single bit result.
For example, the four bits of A are ANDed together to produce Y1.
◼ module Reduction (A, Y1, Y2, Y3, Y4, Y5, Y6);
◼ input [3:0] A;
◼ output Y1, Y2, Y3, Y4, Y5, Y6;
◼ reg Y1, Y2, Y3, Y4, Y5, Y6;
◼ always @(A)
◼ begin
◼ Y1=&A; //reduction AND
◼ Y2=|A; //reduction OR
◼ Y3=~&A; //reduction NAND
◼ Y4=~|A; //reduction NOR
◼ Y5=^A; //reduction XOR
◼ Y6=~^A; //reduction XNOR
◼ end
◼ Shift
◼ Shift operators require two operands. The operand before the
operator contains data to be shifted and the operand after the
operator contains the number of single bit shift operations to be
performed. 0 is being used to fill the blank positions.
◼ module Shift (A, Y1, Y2);
◼

◼ input [7:0] A;
◼ output [7:0] Y1, Y2;
◼ parameter B=3; reg [7:0] Y1, Y2;
◼

◼ always @(A)
◼ begin
◼ Y1=A<<B; //logical shift left
◼ Y2=A>>B; //logical shift right
◼ end
◼ endmodule
◼ Concatenation and Replication
◼ The concatenation operator "{ , }" combines (concatenates) the bits
of two or more data objects. The objects may be scalar (single bit) or
vectored (muliple bit). Multiple concatenations may be performed
with a constant prefix and is known as replication.
◼ module Concatenation (A, B, Y);
◼ input [2:0] A, B;
◼ output [14:0] Y;
◼ parameter C=3'b011;
◼ reg [14:0] Y;
◼ always @(A or B)
◼ begin
◼ Y={A, B, (2{C}}, 3'b110};
◼ end
◼ endmodule
◼
◼ Conditional
◼ An expression using conditional operator
evaluates the logical expression before the
"?".
◼ If the expression is true then the expression
before the colon (:) is evaluated and assigned
to the output.
◼ If the logical expression is false then the
expression after the colon is evaluated and
assigned to the output.
 4-to-1 Multiplexer
◼ Gate-level modeling of a 4-to-1 multiplexer, Example.
The logic diagram for the multiplexer is given in Figure
3.4 and the gate-level Verilog description is shown in
Example.
◼ We describe the multiplexer, using dataflow statements.
◼ We show two methods to model the multiplexer by using
dataflow statements.
◼ Method 1: logic equation
◼ We can use assignment statements instead of gates to
model the logic equations of the multiplexer.
◼ Notice that everything is same as the gate-level Verilog
description except that computation of out is done by
specifying one logic equation by using operators instead
of individual gate instantiations.
◼ I/O ports remain the same.
◼ This important so that the interface with the environment
does not change. Only the internals of the module
change.
◼ Example 4-to-1 Multiplexer, Using Logic Equations
◼ // Module 4-to-1 multiplexer using data flow. logic
equation
◼ module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
◼ output out;
◼ input i0, i1, i2, i3;
◼ input s1, s0;
◼ //Logic equation for out
◼ assign out = (~s1 & ~s0 & i0)|(~s1 & s0 & i1) |(s1 & ~s0
& i2) |(s1 & s0 & i3) ;
◼ endmodule
◼ Method 2: Conditional Operator
◼ There is a more concise way to specify the 4-to-1
multiplexers.
◼ Example of 4-to-1 Multiplexer, Using Conditional
Operators
◼ // Module 4-to-1 multiplexer using data flow. Conditional
operator.
◼ module multiplexer4_to_1 (out, i0, i1, i2, i3, s1, s0);
◼ // Port declarations from the I/O diagram
◼ output out;
◼ input i0, i1, i2, i3
◼ input s1, s0;
◼ assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ;
◼ endmodule
 4 bit Full Adder
◼ Method 1: dataflow operators
◼ Example 4-bit Full Adder, Using Dataflow Operators
◼ // Define a 4-bit full adder by using dataflow statements.
◼ module fulladd4(sum, c_out, a, b, c_in);
◼ // I/O port declarations
◼ output [3:0] sum;
◼ output c_out;
◼ input[3:0] a, b;
◼ input c_in;
◼ // Specify the function of a full adder
◼ assign {c_out, sum} = a + b + c_in;
◼ endmodule
 Example 4-bit Full Adder with Carry
Lookahead
◼ module fulladd4(sum, c_out, a, b, c_in);
◼ // Inputs and outputs
◼ output [3:0] sum;
◼ output c_out;
◼ input [3:0] a,b;
◼ input c_in;
◼ // Internal wires
◼ wire p0,g0, p1,g1, p2,g2, p3,g3;
◼ wire
◼ compute the p for each stage
◼ assign p0 = a[0] ^ b[0],
◼ p1 = a[1] ^ b[1],
◼ p2 = a[2] ^ b[2],
◼ p3 = a[3] ^ b[3];c4, c3, c2, c1;
◼ compute the g for each stage
◼ assign g0 = a[0] & b[0],
◼ g1 = a[1] & b[1],
◼ g2 = a[2] & b[2],
◼ g3 = a[3] & b[3];
◼ // compute the carry for each stage
◼ // Note that c_in I
◼ carry lookahead computation
◼ assign c1 = g0 | (p0 & c_in),
◼ c2 = g1 | (p1 & g0) | (p1 & p0 & c_in),
◼ c3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & c_in),
◼ c4 = g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1 & g0) |
◼ (p3 & p2 & p1 & p0 & c_in);
◼ // Compute Sum
◼ assign sum[0] = p0 ^ c_in,
◼ sum[1] = p1 ^ c1,
◼ sum[2] = p2 ^ c2,
◼ sum[3] = p3 ^ c3;
◼ // Assign carry output
◼ assign c_out = c4;
◼ Endmodule
Ripple Counter
 Example: Verilog Code for Ripple
Counter
◼ module counter(Q , clock, clear);
◼ // I/O ports
◼ output [3:0] Q;
◼ input clock, clear;
◼ // Instantiate the T flipflops
◼ T_FF tff0(Q[0], clock, clear);
◼ T_FF tff1(Q[1], Q[0], clear);
◼ T_FF tff2(Q[2], Q[1], clear);
◼ T_FF tff3(Q[3], Q[2], clear);
◼ endmodule
 Stimulus Module for Ripple
Counter
◼ // Top level stimulus module
◼ module stimulus;
◼ // Declare variables for stimulating input
◼ reg CLOCK, CLEAR;
◼ wire [3:0] Q;
◼ initial
◼ $monitor($time, " Count Q = %b Clear= %b",
Q[3:0],CLEAR);
◼ // Instantiate the design block counter
◼ counter c1(Q, CLOCK, CLEAR)
◼ // Stimulate the Clear Signal
◼ initial
◼ begin
◼ CLEAR = 1'b1;
◼ #34 CLEAR = 1'b0;
◼ #200 CLEAR = 1'b1;
◼ #50 CLEAR = 1'b0;
◼ End
◼ // Set up the clock to toggle every 10 time units
◼ initial
◼ begin
◼ CLOCK = 1'b0;
◼ forever #10 CLOCK = ~CLOCK;
◼ end
◼ // Finish the simulation at time 400
◼ initial
◼ begin
◼ #400 $finish;
◼ end
◼ endmodule
The output of the simulation is shown below. Note that the clear signal resets
the count to zero.
T-Flipflop
 Example :Verilog Code for T-flipflop
◼ // Edge-triggered T-flipflop. Toggles every clock
◼ // cycle.
◼ module T_FF(q, clk, clear);
◼ // I/O ports
◼ output q;
◼ input clk, clear;
◼ // Instantiate the edge-triggered DFF
◼ // Complement of output q is fed back.
◼ // Notice qbar not needed. Unconnected port.
◼ edge_dff ff1(q, ,~q, clk, clear);
◼ endmodule
D-flipflop
 Verilog Code for Edge-Triggered D-
flipflop
◼ // Edge-triggered D flipflop
◼ module edge_dff(q, qbar, d, clk, clear);
◼ // Inputs and outputs
◼ output q,qbar;
◼ input d, clk, clear;
◼ // Internal variables
◼ wire s, sbar, r, rbar,cbar;
◼ // dataflow statements
◼ //Create a complement of signal clear
◼ assign cbar = ~clear;
◼ // Input latches; A latch is level sensitive. An edge-
sensitive
◼ // flip-flop is implemented by using 3 SR latches.
◼ assign sbar = ~(rbar & s),
◼ s = ~(sbar & cbar & ~clk),
◼ r = ~(rbar & ~clk & s),
◼ rbar = ~(r & cbar & d);
◼ // Output latch
◼ assign q = ~(s & qbar),
◼ qbar = ~(q & r & cbar);
◼ endmodule
 Module Outcomes
◼ After completion of the module the students are able to:
◼ Identify logic gate primitives provided in Verilog and Understand
instantiation of gates, gate symbols, and truth tables for and/or and
buf/not type gates.
◼ Understand how to construct a Verilog description from the logic
diagram of the circuit.
◼ Describe rise, fall, and turn-off delays in the gate-level design and
Explain min, max, and type delays in the gate-level design
◼ Describe the continuous assignment (assign) statement, restrictions
on the assign statement, and the implicit continuous assignment
statement.
◼ Explain assignment delay, implicit assignment delay, and net
declaration delay for continuous assignment statements and Define
expressions, operators, and operands.
◼ Use dataflow constructs to model practical digital circuits in Verilog
 Recommended questions
◼ 1. Write the truth table of all the basic gates. Input values
consisting of ‘0’, ‘1’, ‘x’, ‘z’.
◼ 2. What are the primitive gates supported by Verilog
HDL? Write the Verilog HDL statements to
◼ instantiate all the primitive gates.

◼ 3. Use gate level description of Verilog HDL to design 4

to 1 multiplexer. Write truth table, top-level
◼ block, logic expression and logic diagram. Also write the
stimulus block for the same.
◼ 4. Explain the different types of buffers and not gates
with the help of truth table, logic symbol, logic expression
◼ 5. Use gate level description of Verilog HDL to describe
the 4-bit ripple carry counter. Also write a stimulus block
for 4-bit ripple carry adder.
◼ 6. How to model the delays of a logic gate using Verilog
HDL? Give examples. Also explain the different delays
associated with digital circuits.
◼ 7. Write gate level description to implement function y =
a.b + c, with 5 and 4 time units of gate delay for
◼ AND and OR gate respectively. Also write the stimulus
block and simulation waveform.
◼ 8. With syntax describe the continuous assignment
statement.
◼ 9. Show how different delays associated with logic circuit
are modelled using dataflow description.
◼ 10. Explain different operators supported by Verilog
HDL.
◼ 11. What is an expression associated with dataflow
description? What are the different types of operands in
an expression?
◼ 12. Discuss the precedence of operators.
◼ 13. Use dataflow description style of Verilog HDL to
design 4:1 multiplexer with and without using
◼ conditional operator.
◼ 14. Use dataflow description style of Verilog HDL to
design 4-bitadder using
◼ i. Ripple carry logic.
◼ ii. Carry look ahead logic.
◼ 15. Use dataflow description style, gate level
description of Verilog HDL to design 4-bit ripple
carry counter. Also write the stimulus block to verify
the same.