Processor Memory

Bus

I/O device 1 I/O device n

•Multiple I/O devices may be connected to the processor and the memory via a bus.
•Bus consists of three sets of lines to carry address, data and control signals.
•Each I/O device is assigned an unique address.
•To access an I/O device, the processor places the address on the address lines.
•The device recognizes the address, and responds to the control signals.
Accessing I/O devices (contd..)
I/O devices and the memory may share the same address
space:
 Memory-mapped I/O.
 Any machine instruction that can access memory can be used to transfer data
to or from an I/O device.
 Simpler software.

I/O devices and the memory may have different address

spaces:
 Special instructions to transfer data to and from I/O devices.
 I/O devices may have to deal with fewer address lines.
 I/O address lines need not be physically separate from memory address lines.
 In fact, address lines may be shared between I/O devices and memory, with a
control signal to indicate whether it is a memory address or an I/O address.

4
 Address lines
Bus Data lines
Control lines

Address Control Data and I/O

decoder circuits status registers interface

Input device

•I/O device is connected to the bus using an I/O interface circuit which has:
- Address decoder, control circuit, and data and status registers.
•Address decoder decodes the address placed on the address lines thus enabling the
device to recognize its address.
•Data register holds the data being transferred to or from the processor.
•Status register holds information necessary for the operation of the I/O device.
•Data and status registers are connected to the data lines, and have unique addresses.
•I/O interface circuit coordinates I/O transfers.
Accessing I/O devices (contd..)
Recall that the rate of transfer to and from I/O
devices is slower than the speed of the processor. This
creates the need for mechanisms to synchronize data
transfers between them.
Program-controlled I/O:
 Processor repeatedly monitors a status flag to achieve the necessary
synchronization.
 Processor polls the I/O device.

Two other mechanisms used for synchronizing data

transfers between the processor and memory:
 Interrupts.
 Direct Memory Access.
Buses
Processor, main memory, and I/O devices are
interconnected by means of a bus.
Bus provides a communication path for the transfer
of data.
 Bus also includes lines to support interrupts and arbitration.

A bus protocol is the set of rules that govern the

behavior of various devices connected to the bus, as
to when to place information on the bus, when to
assert control signals, etc.
Buses (contd..)
Bus lines may be grouped into three types:
 Data
 Address
 Control

Control signals specify:

 Whether it is a read or a write operation.
 Required size of the data, when several operand sizes (byte, word, long word)
are possible.
 Timing information to indicate when the processor and I/O devices may place
data or receive data from the bus.
Schemes for timing of data transfers over a bus can be
classified into:
 Synchronous,
 Asynchronous.
Synchronous bus
All devices derive timing information from a common
clock line.
The clock line has equally spaced pulses which define
equal time intervals.
 In a simple synchronous bus, each of these pulses constitutes a bus cycle.

One data transfer can take place during one bus

cycle.
 Time
Bus clock

Address and
command

Data

t0 t1 t2

Bus cycle
Master places the
device address and Addressed slave places
command on the bus, data on the data lines Master “strobes” the data
and indicates that on the data lines into its
it is a Read operation. input buffer, for a Read
operation.
•In case of a Write operation, the master places the data on the bus along with the
address and commands at time t0.
•The slave strobes the data into its input buffer at time t 2.
Synchronous bus (contd..)
Once the master places the device address and
command on the bus, it takes time for this
information to propagate to the devices:
 This time depends on the physical and electrical characteristics of the bus.

Also, all the devices have to be given enough time to

decode the address and control signals, so that the
addressed slave can place data on the bus.
Width of the pulse t1 - t0 depends on:
 Maximum propagation delay between two devices connected to the bus.
 Time taken by all the devices to decode the address and control signals, so
that the addressed slave can respond at time t1.
Synchronous bus (contd..)
At the end of the clock cycle, at time t2, the master
strobes the data on the data lines into its input buffer
if it’s a Read operation.
 “Strobe” means to capture the values of the data and store them into a
buffer.
When data are to be loaded into a storage buffer
register, the data should be available for a period
longer than the setup time of the device.
Width of the pulse t2 - t1 should be longer than:
 Maximum propagation time of the bus plus
 Set up time of the input buffer register of the master.
 Time
Address & Bus clock
command Data reaches
Seen by
appear on the master t AM the master.
bus. Address and
command

Data
Address & t DM
command reach
Seen by slave
the slave. tAS
Address and Data appears
command on the bus.

Data
tDS

t0 t1 t
2
•Signals do not appear on the bus as soon as they are placed on the bus, due to the
propagation delay in the interface circuits.
•Signals reach the devices after a propagation delay which depends on the
characteristics of the bus.
•Data must remain on the bus for some time after t2 equal to the hold time of the buffer.
Synchronous bus (contd..)
Data transfer has to be completed within one clock
cycle.
 Clock period t2 - t0 must be such that the longest propagation delay on
the bus and the slowest device interface must be accommodated.
 Forces all the devices to operate at the speed of the slowest device.

Processor just assumes that the data are available at

t2 in case of a Read operation, or are read by the
device in case of a Write operation.
 What if the device is actually failed, and never really responded?
Synchronous bus (contd..)
Most buses have control signals to represent a
response from the slave.
Control signals serve two purposes:
 Inform the master that the slave has recognized the address, and is ready
to participate in a data transfer operation.
 Enable to adjust the duration of the data transfer operation based on the
speed of the participating slaves.
High-frequency bus clock is used:
 Data transfer spans several clock cycles instead of just one clock cycle as in
the earlier case.
 Address & command Time
requesting a Read
operation appear on 1 2 3 4
the bus.
Clock

Address

Command
Master strobes data
into the input buffer.
Data

Slave-ready

Slave places the data on the bus, Clock changes are seen by all the devices
and asserts Slave-ready signal. at the same time.
Asynchronous bus
Data transfers on the bus is controlled by a handshake
between the master and the slave.
Common clock in the synchronous bus case is replaced by
two timing control lines:
 Master-ready,
 Slave-ready.

Master-ready signal is asserted by the master to indicate

to the slave that it is ready to participate in a data transfer.
Slave-ready signal is asserted by the slave in response to
the master-ready from the master, and it indicates to the
master that the slave is ready to participate in a data
transfer.
Asynchronous bus (contd..)
Data transfer using the handshake protocol:
 Master places the address and command information on the bus.
 Asserts the Master-ready signal to indicate to the slaves that the address
and command information has been placed on the bus.
 All devices on the bus decode the address.
 Address slave performs the required operation, and informs the processor
it has done so by asserting the Slave-ready signal.
 Master removes all the signals from the bus, once Slave-ready is asserted.
 If the operation is a Read operation, Master also strobes the data into its
input buffer.
 Time
Address
and command

Master-ready

Slave-ready

Data

t0 t1 t2 t3 t4 t5

Bus cycle
t0 - Master places the address and command information on the bus.
t1 - Master asserts the Master-ready signal. Master-ready signal is asserted at t 1 instead of t0
t2 - Addressed slave places the data on the bus and asserts the Slave-ready signal.
t3 - Slave-ready signal arrives at the master.
t4 - Master removes the address and command information.
t5 - Slave receives the transition of the Master-ready signal from 1 to 0. It removes the data
and the Slave-ready signal from the bus.
Asynchronous vs. Synchronous bus
Advantages of asynchronous bus:
 Eliminates the need for synchronization between the sender and the
receiver.
 Can accommodate varying delays automatically, using the Slave-ready

signal.
Disadvantages of asynchronous bus:
 Data transfer rate with full handshake is limited by two-round trip delays.
 Data transfers using a synchronous bus involves only one round trip delay,

and hence a synchronous bus can achieve faster rates.

Interface circuits
I/O interface consists of the circuitry required to connect
an I/O device to a computer bus.
Side of the interface which connects to the computer has
bus signals for:
 Address,
 Data
 Control
Side of the interface which connects to the I/O device has:
 Datapath and associated controls to transfer data between the interface and
the I/O device.
 This side is called as a “port”.
Ports can be classified into two:
 Parallel port,
 Serial port.
Interface circuits (contd..)
Parallel port transfers data in the form of a number of
bits, normally 8 or 16 to or from the device.
Serial port transfers and receives data one bit at a
time.
Processor communicates with the bus in the same
way, whether it is a parallel port or a serial port.
 Conversion from the parallel to serial and vice versa takes place inside the
interface circuit.
 Data

Address
DATAIN Data
Encoder
R /W and Keyboard
Processor SIN
debouncing switches
Master-ready circuit
Valid
Input
Slave-ready
interface

•Keyboard is connected to a processor using a parallel port.

•Processor is 32-bits and uses memory-mapped I/O and the asynchronous bus
protocol.
•On the processor side of the interface we have:
- Data lines.
- Address lines
- Control or R/W line.
- Master-ready signal and
- Slave-ready signal.
 Data

Address
DATAIN Data
Encoder
R/W and Keyboard
Processor SIN
debouncing switches
Master-ready circuit
Valid
Input
Slave-ready
interface

•On the keyboard side of the interface:

- Encoder circuit which generates a code for the key pressed.
- Debouncing circuit which eliminates the effect of a key bounce (a single key
stroke may appear as multiple events to a processor).
- Data lines contain the code for the key.
- Valid line changes from 0 to 1 when the key is pressed. This causes the code to
be loaded into DATAIN and SIN to be set to 1.
 •Output lines of DATAIN are
are connected to the data lines of
the bus by means of 3 state drivers
•Drivers are turned on when the
processor issues a read signal and
the address selects this register.

•SIN signal is generated using a status flag circuit.

•It is connected to line D0 of the processor bus
using a three-state driver.
•Address decoder selects the input interface based
on bits A1 through A31.
•Bit A0 determines whether the status or data
register is to be read, when Master-ready is
active.
•In response, the processor activates the Slave-ready
signal, when either the Read-status or Read-data
is equal to 1, which depends on line A0.
 Data

Address DATAOUT Data

Processor
CPU R /W SOUT Printer
Valid
Master-ready
Output Idle
Slave-ready interface

•Printer is connected to a processor using a parallel port.

•Processor is 32 bits, uses memory-mapped I/O and asynchronous bus protocol.
•On the processor side:
- Data lines.
- Address lines
- Control or R/W line.
- Master-ready signal and
- Slave-ready signal.
 Data

Address DATAOUT Data

Processor
CPU R /W SOUT Printer
Valid
Master-ready
Output Idle
Slave-ready interface

•On the printer side:

- Idle signal line which the printer asserts when it is ready to accept a character.
This causes the SOUT flag to be set to 1.
- Processor places a new character into a DATAOUT register.
- Valid signal, asserted by the interface circuit when it places a new character
on the data lines.
•Data lines of the processor bus
are connected to the DATAOUT
register of the interface.
•The status flag SOUT is connected
to the data line D1 using a three-state
driver.
•The three-state driver is turned on,
when the control Read-status line is
1.
•Address decoder selects the output
interface using address lines A1
through A31.
•Address line A0 determines whether
the data is to be loaded into the
DATAOUT register or status flag is
to be read.
•If the Load-data line is 1, then the
Valid line is set to 1.
•If the Idle line is 1, then the status
flag SOUT is set to 1.
 Bus
D7 PA7

DATAIN
D1
D0 PA0

SIN
•Combined I/O interface circuit.
CA •Address bits A2 through A31, that is
Input
status
30 bits are used to select the overall
PB7
interface.
DATAOUT •Address bits A1 through A0, that is, 2
PB0bits select one of the three registers,
SOUT
CB1
namely, DATAIN, DATAOUT, and
Handshake
control CB2the status register.
Slave-
Ready 1
•Status register contains the flags SIN and
SOUT in bits 0 and 1.
•Data lines PA0 through PA7 connect the
Master- input device to the DATAIN register.
Ready
R/ W
•DATAOUT register connects the data
A31 lines on the processor bus to lines PB0
My-address
Address
decoder through PB7 which connect to the output
A2 device.
A1
RS1 •Separate input and output data lines for
connection to an I/O device.
RS0
A0
Serial port
 Serial port is used to connect the processor to I/O devices that transmit
data one bit at a time.
 Data are transferred in a bit serial fashion on the device side and in a bit
parallel fashion on the processor side.
 Transformation between the parallel and serial formats is achieved with shift registers that have
parallel access capability.
 The interface that deals with bus is same as in the parallel interface.
 Two status flags, which we will refer to as SIN and SOUT flags maintained by
Status and control block.
 SIN  1 when new data are loaded into DATAIN from input shift register.
 SIN0 when these data are read by the processor.
 SOUT 1 when data are transferred from DATAOUT to the output shift
register.
 SOUT0 when processor writes new data into DATAOUT.
 Input shift register Serial
input
•Input shift register accepts input one bit
at a time from the I/O device.
DATAIN •Once all the 8 bits are received, the
contents of the input shift register are
loaded in parallel into DATAIN register.
•Output data in the DATAOUT register
are loaded into the output shift register.
D7 •Bits are shifted out of the output shift
register and sent out to the I/O device one
D0 bit at a time.
•As soon as data from the input shift reg.
My-address DATAOUT are loaded into DATAIN, it can start
RS1 accepting another 8 bits of data.
RS0 •Input shift register and DATAIN registers
Chip and Serial
R /W register Output shift re gister
are both used at input so that the input
Ready select shift register can start receiving another
Accept set of 8 bits from the input device after
loading the contents to DATAIN, before
Receiving clock
Status
the processor reads the contents of
I NTR
and DATAIN. This is called as double-
control ransmission clock
T
buffering.
Serial port (contd..)
 During the serial transmission, the receiver needs to know when each
bit is placed into its input shift register.
 Because there is no separate line to carry a clock signal from
transmitter to the receiver.
 So the timing information must be embedded into the transmitted
data using an encoding scheme.
 2 basic approaches are there.
 Asynchronous transmission (receiver’s clock is not synchronized with
transmitter clock.)
 Synchronous Transmission:
Contd.,
 Asynchronous also know as start-stop transmission.
 Data transmission is not synchronized b/t 2 devices.
 The transmitter sends data irregularly, rather than in a steady stream.
 Here data is sent in the form of character/ byte.
 As each character is preceded by a start bit that alerts the receiving
computer of its arrival and succeeded by one (or) two stop bits that
signal the end of the character.
 Synchronous transmission: data is sent in form of blocks or frames.
There is no gap between data.
Standard I/O interfaces
I/O device is connected to a computer using an interface
circuit.
Do we have to design a different interface for every
combination of an I/O device and a computer?
A practical approach is to develop standard interfaces and
protocols.
A personal computer has:
 A motherboard which houses the processor chip, main memory and some I/O
interfaces.
 A few connectors into which additional interfaces can be plugged.
Processor bus is defined by the signals on the processor
chip.
 Devices which require high-speed connection to the processor are connected
directly to this bus.
Standard I/O interfaces (contd..)
Because of electrical reasons only a few devices can be
connected directly to the processor bus.
Motherboard usually provides another bus that can
support more devices.
 Processor bus and the other bus (called as expansion bus) are
interconnected by a circuit called “bridge”.
 Devices connected to the expansion bus experience a small delay in data
transfers.
Standard I/O interfaces (contd..)
A number of standards have been developed for the
expansion bus.
Three widely used bus standards:
 PCI (Peripheral Component Interconnect)
 SCSI (Small Computer System Interface)

37
 Main
Processor
memory
Bridge circuit translates
signals and protocols from
Processor bus
processor bus to PCI bus.

Bridge

PCI bus
Expansion bus on
the motherboard
Additional SCSI Ethernet USB ISA
memory controller Interface controller Interface

SCSI bus
IDE
disk
Video
Disk CD-ROM
controller controller

CD-
Disk 1 Disk 2 ROM K eyboard Game
PCI Bus
 Peripheral Component Interconnect
 Introduced in 1992
 Low-cost bus
 Processor independent
 PCI bus is connected to the processor bus via a controller called b Bridge.
 In today’s computers, most memory transfers involve a burst of data rather
than just one word. The PCI is designed primarily to support this mode of
operation.
 The bus supports three independent address spaces: memory, I/O, and
configuration.
 we assumed that the master maintains the address information on the bus
until data transfer is completed. But, the address is needed only long enough
for the slave to be selected. Thus, the address is needed on the bus for one
clock cycle only, freeing the address lines to be used for sending data in
subsequent clock cycles. The result is a significant cost reduction.
 A master is called an initiator in PCI terminology. The addressed device that
responds to read and write commands is called a target.
Data transfer signals on the PCI bus.

Name Function

CLK A 33-MHz or 66-MHz clock.

FRAME# Sent b y the initiator to indicate the duration of a

transaction.

AD 32 address/data lines, which may be optionally

increased to 64.

C/BE# 4 command/byte-enable lines (8 for a 64-bit bus).

IRD Y#, TRD Y# Initiator-ready and Target-ready signals.

DEVSEL# A response from the device indicating that it has

recognized its address and is ready for a data
transfer transaction.

IDSEL# Initialization Device Select.

 1 2 3 4 5 6 7

CLK

Frame#

AD Adress #1 #2 #3 #4

C/BE# Cmnd Byte enable

IRDY#

TRD Y#

DEVSEL#

A read operation on the PCI bus

SCSI Bus
 The acronym SCSI stands for Small Computer System Interface.
 It refers to a standard bus defined by the American National
Standards Institute (ANSI).
 Data transfer:- Let us consider how SCSI may be used with a disk
drive.
 Data are stored on a disk in block called sectors.
 Each sector may contain several hundred bytes. When data bytes are
written on a disk, it is not always stored in contagious sectors.
 Hence, a read/ write request may request in accessing several disk
sectors that are not necessary continuous.
SCSI Bus (Contd.,)
Data transfers on the SCSI bus are always controlled
by the target controller.
To send a command to a target, an initiator requests
control of the bus and, after winning arbitration,
selects the controller it wants to communicate with
and hands control of the bus over to it.
Then the controller starts a data transfer operation to
receive a command from the initiator.
SCSI Bus (Contd.,)
 Assume that processor needs to read block of data from a disk drive and
that data are stored in disk sectors that are not contiguous.
 The processor sends a command to the SCSI controller, which causes the
following sequence of events to take place:
1. The SCSI controller, acting as an initiator, contends for control of the bus.
2. When it wins the arbitration process, the SCSI controller sends a
command to the disk controller, specifying required operation.
3. The disk controller can not start to transfer data immediately, it must
first move the read head of the disk to the required sector. Hence, it
sends a message to the SCSI controller indicating that it will
temporarily suspend the connection between the. SCSI bus is now
free to be used by other device.
4. The disk controller sends a command to the disk drive to move the
read head to the first sector involved in the requested read operation.
It reads the data and stored them in a data buffer.
SCSI Bus (Contd.,)
When it ready to begin transfer of data, it request control of the bus.
after it win arbitration, it re-establish the connection with SCSI
controller, send the contents of data buffer, then suspend the
connection again.
5. The process is repeated to read and transfer the contents of the
second disk sector.
6. SCSI controller transfer the requested data to the main memory
and send an interrupt to the processor indicating that the data are
now available.