Pin Diagram of 8086

8086 microprocessor Common signals
Pins and Signals

AD -AD (Bidirectional)
0 15
Address/Data bus
Low order address bus; these are

multiplexed with data.
When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.
When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.
A16/S3, A17/S4, A18/S5, A19/S6
High order address bus. These are

multiplexed with status signals
Pins and Signals

BHE (Active Low)/S 7 (Output)
Bus High Enable/Status
It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.
MN/ MX
MINIMUM / MAXIMUM
This pin signal indicates what mode the

processor is to operate in.
RD (Read) (Active Low)
The signal is used for read operation.

It is an output signal.
It is active when low.
Pins and Signals TEST

𝐓𝐄𝐒𝐓 input is tested by the ‘WAIT’
instruction.
8086 will enter a wait state after

execution of the WAIT instruction and
will resume execution only when the
𝐓𝐄𝐒𝐓 is made low by an active hardware.
This is used to synchronize an external

activity to the processor internal
operation.
READY
This is the acknowledgement from the

slow device or memory that they have
completed the data transfer.
The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.
The signal is active high.

Pins and Signals

RESET (Input)
Causes the processor to immediately

terminate its present activity.
The signal must be active HIGH for at

least four clock cycles.
CLK
The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.
INTR Interrupt Request
This is a triggered input. This is sampled

during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
interrupt acknowledge cycle.
This signal is active high and internally

synchronized.
8086 microprocessor Min/ Max Pins
Pins and Signals

The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.
In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.
In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.
Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).
When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.
8086 microprocessor Minimum mode signals
Pins and Signals Pins 24 -31
For minimum mode operation, the MN/ 𝐌𝐗 is tied

to VCC (logic high)
8086 itself generates all the bus control signals
DT/𝐑
ഥ (Data Transmit/ Receive) Output signal from the
processor to control the direction of data flow
through the data transceivers
𝐃𝐄𝐍 (Data Enable) Output signal from the processor

used as out put enable for the transceivers
ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches
M/𝐈𝐎 Used to differentiate memory access and I/O

access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.
𝐖𝐑 Write control signal; asserted low Whenever

processor writes data to memory or I/O port
𝐈𝐍𝐓𝐀 (Interrupt Acknowledge) When the interrupt

request is accepted by the processor, the output is
low on this line.
8086 microprocessor Minimum mode signals
Pins and Signals Pins 24 -31
For minimum mode operation, the MN/ 𝐌𝐗 is tied

to VCC (logic high)
8086 itself generates all the bus control signals
HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.
Usually used by the DMA controller to get the

control of the bus.
HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.
The acknowledge is asserted high, when the

processor accepts HOLD.
8086 microprocessor Maximum mode signals
Pins and Signals

During maximum mode operation, the MN/ 𝐌𝐗 is
grounded (logic low)
Pins 24 -31 are reassigned
𝑺𝟎 , 𝑺𝟏 , 𝑺𝟐 Status signals; used by the 8086 bus controller to

generate bus timing and control signals. These are
decoded as shown.
Pins and Signals

𝑸𝑺𝟎 , 𝑸𝑺𝟏 (Queue Status) The processor provides the status

of queue in these lines.
The queue status can be used by external device to

track the internal status of the queue in 8086.
The output on QS0 and QS1 can be interpreted as

shown in the table.
Pins and Signals

𝐑𝐐/𝐆𝐓𝟎 , (Bus Request/ Bus Grant) These requests are used

𝐑𝐐/𝐆𝐓𝟏 by other local bus masters to force the processor
to release the local bus at the end of the
processor’s current bus cycle.
These pins are bidirectional.
The request on𝐆𝐓𝟎 will have higher priority than𝐆𝐓𝟏
𝐋𝐎𝐂𝐊 An output signal activated by the LOCK prefix

instruction.
Remains active until the completion of the

instruction prefixed by LOCK.
The 8086 output low on the 𝐋𝐎𝐂𝐊 pin while

executing an instruction prefixed by LOCK to
prevent other bus masters from gaining control of
the system bus.
8086 microprocessor
Architecture
Execution Unit (EU) Bus Interface Unit (BIU)
EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.

Pin Diagram of 8086

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8086 microprocessor Common signals

Pins and Signals

Low order address bus; these are

When AD lines are used to transmit

When data are transmitted over AD lines

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

Pins and Signals

Bus High Enable/Status

It is used to enable data onto the most

This pin signal indicates what mode the

RD (Read) (Active Low)

The signal is used for read operation.

Pins and Signals TEST

8086 will enter a wait state after

This is used to synchronize an external

This is the acknowledgement from the

The signal made available by the devices

The signal is active high.

Pins and Signals

Causes the processor to immediately

The signal must be active HIGH for at

The clock input provides the basic timing

INTR Interrupt Request

This is a triggered input. This is sampled

This signal is active high and internally

Pins and Signals

In the minimum mode of operation the

In the maximum mode the 8086 can work

Minimum or maximum mode operations

When this pin is high 8086 operates in

Pins and Signals Pins 24 -31

For minimum mode operation, the MN/ 𝐌𝐗 is tied

8086 itself generates all the bus control signals

𝐃𝐄𝐍 (Data Enable) Output signal from the processor

ALE (Address Latch Enable) Used to demultiplex the

M/𝐈𝐎 Used to differentiate memory access and I/O

𝐖𝐑 Write control signal; asserted low Whenever

𝐈𝐍𝐓𝐀 (Interrupt Acknowledge) When the interrupt

Pins and Signals Pins 24 -31

For minimum mode operation, the MN/ 𝐌𝐗 is tied

8086 itself generates all the bus control signals

HOLD Input signal to the processor form the bus masters

Usually used by the DMA controller to get the

HLDA (Hold Acknowledge) Acknowledge signal by the

The acknowledge is asserted high, when the

Pins and Signals

Pins 24 -31 are reassigned

𝑺𝟎 , 𝑺𝟏 , 𝑺𝟐 Status signals; used by the 8086 bus controller to

Pins and Signals

Pins 24 -31 are reassigned

𝑸𝑺𝟎 , 𝑸𝑺𝟏 (Queue Status) The processor provides the status

The queue status can be used by external device to

The output on QS0 and QS1 can be interpreted as

Pins and Signals

Pins 24 -31 are reassigned

𝐑𝐐/𝐆𝐓𝟎 , (Bus Request/ Bus Grant) These requests are used

These pins are bidirectional.

The request on𝐆𝐓𝟎 will have higher priority than𝐆𝐓𝟏