Lecture 3: Logic Systems, Data Types, and Operators For Modeling in Verilog HDL
Lecture 3: Logic Systems, Data Types, and Operators For Modeling in Verilog HDL
Lecture 3: Logic Systems, Data Types, and Operators For Modeling in Verilog HDL
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Variables and Logic Value Set
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Data Types: Nets
Nets for connectivity:
wire establishes connectivity
tri same as wire and it will be tri-stated in hardware
wand a net has multiple drivers, wires and, i.e., open
collector circuit
wor a net has multiple drivers, wired or, i.e., emitter
coupled circuit
triand a net that has multiple drivers. It models wired-and. It is
tri-stated.
trior a net that has multiple drivers. It models wired-or. It
is tri- stated.
supply0 a global net connected to the circuit ground
supply1 a global net connected to the power supply
tri0 a net connected to the ground by a resistive
pulldown connection.
tri1 a net connected to the power supply by a resistive
pullup connection.
trireg a net that models the charge stored on a physical
net.
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Data Types: Registers
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Net Declaration
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What if a wire or tri type net is driven
by multiple driver?
wire/tri 0 1 x z
0 0 x x 0
1 x 1 x 1
x x x x x
z 0 1 x z
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BUF and NOT gates
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BUFIF and NOTIF gates
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BUFIF and NOTIF gates
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What is the initial value of a net?
wire a, b, c;
assign a = b+ c; // initial value by default b = z, c = z, a = x
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Wired logic
triand
/wand 0 1 x z
0 0 0 0 0
1 0 1 x 1
x 0 x x x
z 0 1 x z
trior
/wor 0 1 x z
0 0 1 x 0
1 0 1 1 1
x x 1 x x
z 0 1 x z
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Verilog examples
module good_wand;
reg a, b, c;
wire w_nor, w_buf. w_mult;
wand w_wand;
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Register Data Types
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Verilog Example: using register
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Initial Value of a Register Variable
reg A, B;
initial
begin
A = 0; // assign an initial value to A
B = 1; // assign an initial value to B
end
// All registers have an initial value of "x" by default.
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Passing Variables Through Ports
Port Mode
Variable Type Input Output InOut
net variable yes yes yes
register variable no yes no
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Memory Declaration
Memory Declaration
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Hierarchical De-referencing
module test_Add_rca_4();
reg [3:0] a,b;
reg c_in;
wire [3:0] sum;
wire c_out;
initial
begin
$monitor ($time,, "c_out= %b c_in4=%b c_in3=%b c_in2=%b
c_in=%b ",
c_out, M1.c_in4, M1.c_in3, M1.c_in2, c_in);
end
initial
begin
// stimus patterns generated here
end
Add_rca_4 M1 (sum, c_out, a, b, c_in);
endmodule
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Verilog model: 4 bit RCA
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Parameters Substitution
module modXnor (y_out, a, b);
parameter size=8, delay=15;
output [size-1:0] y_out;
input [size-1:0] a, b;
wire [size-1:0] #delay y_out=a~^b;
endmodule
module Param;
wire [7:0] y1_out;
wire [3:0] y2_out;
reg [7:0] b1, c1;
reg [3:0] b2, c2;
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Indirect Parameters Substitution
module modXnor (y_out, a, b);
parameter size=8, delay=15;
output [size-1:0] y_out;
input [size-1:0] a, b;
wire [size-1:0] #delay y_out=a~^b;
endmodule
module hdref_Param;
wire [7:0] y1_out;
wire [3:0] y2_out;
reg [7:0] b1, c1;
reg [3:0] b2, c2;
modXnor G1 (y1_out, b1, c1);
modXnor G2 (y2_out, b2, c2);
endmodule
module annotate;
defparam
hdref_Param.G2.size = 4,
hdref_Param.G2.delay = 5;
endmodule
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Verilog Model Example
Design a 4-to-1 mux by cascading 2-to-1 muxes.
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