Combinational Logic Design Case Studies

 General design procedure

 Examples
Calendar subsystem
BCD to 7-segment display controller
Process line controller
Logical function unit
 Arithmetic
Integer representations
Addition/subtraction
Arithmetic/logic units

CS 150 - Fall 2000 - Combinational Examples - 1

General Design Procedure for Combinational Logic

 1. Understand the Problem

What is the circuit supposed to do?
Write down inputs (data, control) and outputs
Draw block diagram or other picture
 2. Formulate the Problem using a Suitable Design
Representation
Truth table or waveform diagram are typical
May require encoding of symbolic inputs and outputs
 3. Choose Implementation Target
ROM, PAL, PLA
Mux, decoder and OR-gate
Discrete gates
 4. Follow Implementation Procedure
K-maps for two-level, multi-level
Design tools and hardware description language (e.g., Verilog)
CS 150 - Fall 2000 - Combinational Examples - 2
Calendar Subsystem

 Determine number of days in a month (to control

watch display)
Used in controlling the integer number_of_days ( month, leap_year_flag) {
display of a wrist-watch switch (month) {
case 1: return (31);
LCD screen case 2: if (leap_year_flag == 1)
then return (29)
else return (28);
Inputs: month, leap year case 3: return (31);
case 4: return (30);
flag case 5: return (31);
case 6: return (30);
Outputs: number of days case 7: return (31);
case 8: return (31);
case 9: return (30);
case 10: return (31);
 Use software case 11: return (30);
case 12: return (31);
implementation }
default: return (0);

to help understand }

the problem
CS 150 - Fall 2000 - Combinational Examples - 3
 Formalize the Problem

 Encoding:
Binary number for month: 4 bits month leap 28 29 30 31
0000 – – – – –
4 wires for 28, 29, 30, and 31 0001 – 0 0 0 1
one-hot – only one true at any time 0010 0 1 0 0 0
0010 1 0 1 0 0
 Block diagram: 0011
0100
–
–
0
0
0
0
0
1
1
0
month leap 0101 – 0 0 0 1
0110 – 0 0 1 0
0111 – 0 0 0 1
1000 – 0 0 0 1
1001 – 0 0 1 0
1010 – 0 0 0 1
1011 – 0 0 1 0
1100 – 0 0 0 1
1101 – – – – –
111– – – – – –
28 29 30 31

CS 150 - Fall 2000 - Combinational Examples - 4

Choose Implementation Target
and Perform Mapping

 Discrete gates month leap 28 29 30 31

0000 – – – – –
0001 – 0 0 0 1
28 = m8’ m4’ m2 m1’ leap’ 0010 0 1 0 0 0
0010 1 0 1 0 0
0011 – 0 0 0 1
0100 – 0 0 1 0
29 = m8’ m4’ m2 m1’ leap 0101 – 0 0 0 1
0110 – 0 0 1 0
0111 – 0 0 0 1
30 = m8’ m4 m1’ + m8 m1 1000 – 0 0 0 1
1001 – 0 0 1 0
1010 – 0 0 0 1
31 = m8’ m1 + m8 m1’ 1011 – 0 0 1 0
1100 – 0 0 0 1
1101 – – – – –
 Can translate to S-o-P 111– – – – – –

or P-o-S

CS 150 - Fall 2000 - Combinational Examples - 5

BCD to 7-segment display controller

 Understanding the problem

Input is a 4 bit bcd digit (A, B, C, D)
Output is the control signals for the display (7 outputs C0 – C6)
 Block diagram c0
c5 c1

c6
c4 c2

c3
c0 c1 c2 c3 c4 c5 c6

BCD to 7–segment
control signal
decoder

A B C D

CS 150 - Fall 2000 - Combinational Examples - 6

Formalize the problem

 Truth table
Show don't cares A B C D C0 C1 C2 C3 C4 C5 C6
0 0 0 0 1 1 1 1 1 1 0
 Choose implementation 0 0 0 1 0 1 1 0 0 0 0
target 0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
If ROM, we are done 0 1 0 0 0 1 1 0 0 1 1
Don't cares imply PAL/PLA 0 1 0 1 1 0 1 1 0 1 1
may be attractive 0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
 Follow implementation 1 0 0 0 1 1 1 1 1 1 1
procedure 1 0 0 1 1 1 1 0 0 1 1
1 0 1 – – – – – – – –
Minimization using K-maps
1 1 – – – – – – – – –

CS 150 - Fall 2000 - Combinational Examples - 7

Implementation as Minimized Sum-of-Products

 15 unique product terms when minimized individually

A A A A A
1 0 X 1 1 1 X 1 1 1 X 1 1 0 X 1 1 0 X 1
0 1 X 1 1 0 X 1 1 1 X 1 0 1 X 0 0 0 X 0
D D D D D
C 1 1 X X C 1 1 X X C 1 1 X X C 1 0 X X C 0 0 X X
1 1 X X 1 0 X X 0 1 X X 1 1 X X 1 1 X X
B B B B B
A A
1 1 X 1 0 1 X 1
C0 = A + B D + C + B' D'
0 1 X 1
D
0 1 X 1
D C1 = C' D' + C D + B'
C 0 0 X X C 1 0 X X C2 = B + C' + D
0 1 X X 1 1 X X
C3 = B' D' + C D' + B C' D + B' C
C4 = B' D' + C D'
B B
C5 = A + C' D' + B D' + B C'
C6 = A + C D' + B C' + B' C

CS 150 - Fall 2000 - Combinational Examples - 8

Implementation as Minimized S-o-P (cont'd)

 Can do better
9 unique product terms (instead of 15)
Share terms among outputs
Each output not necessarily in minimized form
A A
C2 1 1 X 1 C2 1 1 X 1
1 1 X 1 1 1 X 1
D D
C 1 1 X X C 1 1 X X
0 1 X X 0 1 X X
B B

C0 = A + B D + C + B' D' C0 = B C' D + C D + B' D' + B C D' + A

C1 = C' D' + C D + B' C1 = B' D + C' D' + C D + B' D'
C2 = B + C' + D C2 = B' D + B C' D + C' D' + C D + B C D'
C3 = B' D' + C D' + B C' D + B' C C3 = B C' D + B' D + B' D' + B C D'
C4 = B' D' + C D' C4 = B' D' + B C D'
C5 = A + C' D' + B D' + B C' C5 = B C' D + C' D' + A + B C D'
C6 = A + C D' + B C' + B' C C6 = B' C + B C' + B C D' + A
CS 150 - Fall 2000 - Combinational Examples - 9
PLA implementation
A B C D

BC'
B'C
B'D
BC'D
C'D'
CD
B'D'
A
BCD'

C0 C1 C2 C3 C4 C5 C6 C7

CS 150 - Fall 2000 - Combinational Examples - 10

PAL Implementation

 Limit of 4 Product Terms per Output

Decomposition of functions with larger number of terms
Do not share terms in PAL anyway
(although there are some with some shared terms)
C2 = B + C' + D

C2 = B' D + B C' D + C' D' + C D + B C D'

C2 = B' D + B C' D + C' D' + W need another input and another output
W = C D + B C D'
Decompose into multi-level logic (hopefully with CAD support)
Find common sub-expressions among functions
C0 = C3 + A' B X' + A D Y
C1 = Y + A' C5' + C' D' C6
C2 = C5 + A' B' D + A' C D X = C' + D'
C3 = C4 + B D C5 + A' B' X' Y = B' C'
C4 = D' Y + A' C D'
C5 = C' C4 + A Y + A' B X
C6 = A C4 + C C5 + C4' C5 + A' B' C
CS 150 - Fall 2000 - Combinational Examples - 11
Production Line Control

 Rods of varying length (+/-10%) travel on conveyor belt

Mechanical arm pushes rods within spec (+/-5%) to one side
Second arm pushes rods too long to other side
Rods that are too short stay on belt
3 light barriers (light source + photocell) as sensors
Design combinational logic to activate the arms
 Understanding the problem
Inputs are three sensors
Outputs are two arm control signals
Assume sensor reads "1" when tripped, "0" otherwise
Call sensors A, B, C

CS 150 - Fall 2000 - Combinational Examples - 12

Sketch of Problem

 Position of Sensors
A to B distance = specification – 5%
A to C distance = specification + 5%

spec
- 5%

Too Within Too spec

Long Spec Short + 5%

B
C

CS 150 - Fall 2000 - Combinational Examples - 13

Formalize the problem

 Truth Table
Show don't cares

A B C Function logic implementation now straightforward

0 0 0 do nothing just use three 3-input AND gates
0 0 1 do nothing
0 1 0 do nothing "too short" = AB'C'
0 1 1 do nothing (only first sensor tripped)
1 0 0 too short
1 0 1 don't care "in spec" = A B C'
1 1 0 in spec (first two sensors tripped)
1 1 1 too long
"too long" = A B C
(all three sensors tripped)

CS 150 - Fall 2000 - Combinational Examples - 14

Logical Function Unit

 Multi-purpose Function Block

3 control inputs to specify operation to perform on operands
2 data inputs for operands
1 output of the same bit-width as operands

C0 C1 C2 Function Comments
0 0 0 1 always 1
0 0 1 A+B logical OR
3 control inputs: C0, C1, C2
0 1 0 (A • B)' logical NAND
2 data inputs: A, B
0 1 1 A xor B logical xor
1 output: F
1 0 0 A xnor B logical xnor
1 0 1 A•B logical AND
1 1 0 (A + B)' logical NOR
1 1 1 0 always 0

CS 150 - Fall 2000 - Combinational Examples - 15

Formalize the Problem
C0 C1 C2 A B F
0 0 0 0 0 1
0 0 0 0 1 1
0 0 0 1 0 1 choose implementation technology
0 0 0 1 1 1
0 0 1 0 0 0 5-variable K-map to discrete gates
0 0 1 0 1 1
0 0 1 1 0 1 multiplexer implementation
0 0 1 1 1 1
0 1 0 0 0 1
0 1 0 0 1 1
0 1 0 1 0 1
0 1 0 1 1 0 1 0
0 1 1 0 0 0
0 1 1 0 1 1 1
0 1 1 1 0 1 A
2
0 1 1 1 1 0 B F
1 0 0 0 0 1
A 3 8:1 MUX
1 0 0 0 1 0
1 0 0 1 0 0 B 4
1 0 0 1 1 1
1 0 1 0 0 0
5
1 0 1 0 1 0 A 6
1 0 1 1 0 0 B
1 0 1 1 1 1 0 7
1 1 0 0 0 1 S2 S1 S0
1 1 0 0 1 0
1 1 0 1 0 0
1 1 0 1 1 0
1 1 1 0 0 0 C0 C1 C2
1 1 1 0 1 0
1 1 1 1 0 0
1 1 1 1 1 0

CS 150 - Fall 2000 - Combinational Examples - 16

Arithmetic Circuits

 Excellent Examples of Combinational Logic Design

 Time vs. Space Trade-offs
Doing things fast may require more logic and thus more space
Example: carry lookahead logic
 Arithmetic and Logic Units
General-purpose building blocks
Critical components of processor datapaths
Used within most computer instructions

CS 150 - Fall 2000 - Combinational Examples - 17

Number Systems

 Representation of positive numbers is the same in most

systems
 Major differences are in how negative numbers are
represented
 Representation of negative numbers come in three major
schemes
Sign and magnitude
1s complement
2s complement
 Assumptions
We'll assume a 4 bit machine word
16 different values can be represented
Roughly half are positive, half are negative
CS 150 - Fall 2000 - Combinational Examples - 18
Sign and Magnitude

 One bit dedicate to sign

0 100 = + 4
(positive or negative)
sign: 0 = positive (or zero), 1 = negative 1 100 = – 4

 Rest represent the absolute

–7 +0
value or magnitude +1
–6 1111 0000
three low order bits: 0 (000) 1110 0001
–5 +2
thru 7 (111) 1101 0010
–4
 Range for n bits 1100 0011 +3

+/– 2n–1 –1 (two representations –3 1011 0100 +4

for 0) –2 1010 0101 +5
1001
 Cumbersome addition/subtraction –1 1000 0111
0110
+6
must compare magnitudes –0 +7
to determine sign of result
CS 150 - Fall 2000 - Combinational Examples - 19
1s Complement

 If N is a positive number, then the negative of N ( its

1s complement or N' ) is N' = (2n– 1) – N
Example: 1s complement of 7
4
2 = 10000
1 = 00001
4
2 –1 = 1111
7 = 0111
1000 = –7 in 1s complement form

Shortcut: simply compute bit-wise complement ( 0111 -> 1000 )

CS 150 - Fall 2000 - Combinational Examples - 20

1s complement (cont'd)

 Subtraction implemented by 1s complement and then

addition
 Two representations of 0
Causes some complexities in addition –0 +0
–1 +1
1111 0000
 High-order bit can act as sign bit 1110 0001
–2 +2
1101 0010
–3
1100 0011 +3
0 100 = + 4
–4 1011 0100 +4
1 011 = – 4 1010 0101
–5 +5
1001 0110
–6 1000 0111 +6

–7 +7

CS 150 - Fall 2000 - Combinational Examples - 21

2s Complement

 1s complement with negative numbers shifted one

position clockwise
Only one representation for 0
One more negative number than positive number
High-order bit can act as sign bit –1 +0
–2 +1
1111 0000
–3 1110 0001
+2
1101 0010
0 100 = + 4
–4 1100 0011 +3
1 100 = – 4
–5 1011 0100 +4
1010 0101
–6 +5
1001 0110
–7 1000 0111 +6

–8 +7
CS 150 - Fall 2000 - Combinational Examples - 22
2s complement (cont’d)

 If N is a positive number, then the negative of N ( its

2s complement or N* ) is N* = 2n – N
4
Example: 2s complement of 7 2 = 10000
subtract 7 = 0111
1001 = repr. of –7

4
Example: 2s complement of –7 2 = 10000
subtract –7 = 1001
0111 = repr. of 7

Shortcut: 2s complement = bit-wise complement + 1

0111 -> 1000 + 1 -> 1001 (representation of -7)
1001 -> 0110 + 1 -> 0111 (representation of 7)
CS 150 - Fall 2000 - Combinational Examples - 23
2s Complement Addition and Subtraction

 Simple Addition and Subtraction

Simple scheme makes 2s complement the virtually unanimous
choice for integer number systems in computers

4 0100 –4 1100
+3 0011 + (– 3) 1101
7 0111 –7 11001

4 0100 –4 1100
–3 1101 +3 0011
1 10001 –1 1111

CS 150 - Fall 2000 - Combinational Examples - 24

Why Can the Carry-out be Ignored?

 Can't ignore it completely

Needed to check for overflow (see next two slides)
 When there is no overflow, carry-out may be true but
can be ignored
– M + N when N > M:
M* + N = (2n – M) + N = 2n + (N – M)

ignoring carry-out is just like subtracting 2n

– M + – N where N + M  2n–1
(– M) + (– N) = M* + N* = (2n– M) + (2n– N) = 2n – (M + N) + 2n

ignoring the carry, it is just the 2s complement

representation for – (M + N)
CS 150 - Fall 2000 - Combinational Examples - 25
 Overflow in 2s Complement
Addition/Subtraction

 Overflow conditions
Add two positive numbers to get a negative number
Add two negative numbers to get a positive number
–1 +0 –1 +0
–2 +1 –2 +1
1111 0000 1111 0000
–3 1110 0001 –3 1110 0001
+2 +2
1101 0010 1101 0010
–4 1100 0011 +3 –4 1100 0011 +3

–5 1011 0100 +4 –5 1011 0100 +4

1010 0101 1010 0101
–6 +5 –6 +5
1001 0110 1001 0110
–7 1000 0111 +6 –7 1000 0111 +6

–8 +7 –8 +7
5 + 3 = –8 –7 – 2 = +7
CS 150 - Fall 2000 - Combinational Examples - 26
Overflow Conditions

 Overflow when carry into sign bit position is not equal

to carry-out
0 1 1 1 1 0 0 0
0101 1001
5 –7
0011 1110
3 –2
1000 10111
–8 7
overflow overflow
0 0 0 0
1 1 1 1
0101 1101
5 –3
0010 1011
2 –5
0111 11000
7 –8
no overflow no overflow
CS 150 - Fall 2000 - Combinational Examples - 27
Circuits for Binary Addition

 Half adder (add 2 1-bit numbers)

Sum = Ai' Bi + Ai Bi' = Ai xor Bi
Cout = Ai Bi
 Full adder (carry-in to cascade for multi-bit adders)
Sum = Ci xor A xor B
Cout = B Ci + A Ci + A B = Ci (A + B) + A B
Ai Bi Cin Sum Cout
0 0 0 0 0
Ai Bi Sum Cout 0 0 1 1 0
0 0 0 0 0 1 0 1 0
0 1 1 0 0 1 1 0 1
1 0 1 0 1 0 0 1 0
1 1 1 1 1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
CS 150 - Fall 2000 - Combinational Examples - 28
Full adder implementations
A
 Standard approach B
S
6 gates Cin

2 XORs, 2 ANDs, 2 ORs A

B
Cin
Cout
A
B

Cout = A B + Cin (A xor B) = A B + B Cin + A Cin

 Alternative implementation
5 gates
half adder is an XOR gate and AND gate
2 XORs, 2 ANDs, 1 OR
A xor B Sum A xor B xor Cin Sum
Sum
A
Half Half
B Adder Adder
Cout A B Cout Cin (A xor B)
Cin Cout
CS 150 - Fall 2000 - Combinational Examples - 29
Adder/Subtractor

 Use an adder to do subtraction thanks to 2s

complement representation
A – B = A + (– B) = A + B' + 1
Control signal selects B or 2s complement of B
A3 B3B3' A2 B2B2' A1 B1B1' A0 B0B0'

Sel 0 1 Sel 0 1 Sel 0 1 Sel

0 1

A B A B A B A B
Add'
Cout Cin Cout Cin Cout Cin Cout Cin
Subtract
Sum Sum Sum Sum

S3 S2 S1 S0

Overflow
CS 150 - Fall 2000 - Combinational Examples - 30
Ripple-Carry Adders

 Critical Delay
The propagation of carry from low to high order stages
Cin
4 stage
@0 A @1 @N+1 adder
@0 B A0 S0 @2
@N Cin B0 C1 @2
Cout
@N+2
@0 A
@0 B @1 A1 S1 @3
B1 C2 @4
late two gate delays
arriving to compute Cout A2 S2 @5
signal B2 C3 @6

A3 S3 @7
B3 Cout @8

CS 150 - Fall 2000 - Combinational Examples - 31

Ripple-Carry Adders (cont’d)

 Critical delay
The propagation of carry from low to high order stages
1111 + 0001 is the worst case addition
Carry must propagate through all bits

CS 150 - Fall 2000 - Combinational Examples - 32

Carry-Lookahead Logic

 Carry generate: Gi = Ai Bi
Must generate carry when A = B = 1
 Carry propagate: Pi = Ai xor Bi
Carry-in will equal carry-out here
 Sum and Cout can be re-expressed in terms of
generate/propagate:
Si = Ai xor Bi xor Ci
= Pi xor Ci

Ci+1 = Ai Bi + Ai Ci + Bi Ci
= Ai Bi + Ci (Ai + Bi)
= Ai Bi + Ci (Ai xor Bi)
= Gi + Ci Pi

CS 150 - Fall 2000 - Combinational Examples - 33

Carry-Lookahead Logic (cont’d)

 Re-express the carry logic as follows:

C1 = G0 + P0 C0
C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0
C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0
C4 = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0
+ P3 P2 P1 P0 C0

 Each of the carry equations can be implemented with

two-level logic
All inputs are now directly derived from data inputs and not
from intermediate carries
this allows computation of all sum outputs to proceed in parallel

CS 150 - Fall 2000 - Combinational Examples - 34

Carry-Lookahead Implementation

 Adder with propagate and generate outputs

Ai Pi @ 1 gate delay
Bi

Ci Si @ 2 gate delays

Gi @ 1 gate delay increasingly complex

logic for carries

C0 C0 C0
P0 C1 P0 P0
G0 P1 P1
P2 P2
G0 P3
C0 P1 G0
P0 P2 P1
P1 P2
G1 C3 P3
G0 P2 G1
P1 C2
P2
G2 P3
G1 C4
G2
P3
G3
CS 150 - Fall 2000 - Combinational Examples - 35
Carry-Lookahead Implementation (cont’d)

 Carry-lookahead logic generates individual carries

Sums computed much more quickly in parallel
However, cost of carry logic increases with more stages
Cin Cin
A0 S0 @2
B0
A0 S0 @2
B0 C1 @2 C1 @3
A1 S1 @4
B1
A1 S1 @3
B1 C2 @4 C2 @3
A2 S2 @4
B2
A2 S2 @5
B2 C3 @6 C3 @3
A3 S3 @4
B3
A3 S3 @7
B3 Cout @8 C4 @3 C4 @3

CS 150 - Fall 2000 - Combinational Examples - 36

Carry-Lookahead Adder
with Cascaded Carry-Lookahead Logic

 Carry-lookahead adder
4 four-bit adders with internal carry lookahead
Second level carry lookahead unit extends lookahead to 16 bits

4 4 4 4 4 4 4 4

A[15-12]B[15-12] A[11-8] B[11-8] A[7-4] B[7-4] A[3-0] B[3-0]

4-bit Adder C12 4-bit Adder C8 4-bit Adder C4 4-bit Adder C0
@0
P G P G P G P G
4 4 4 4

S[15-12] S[11-8] S[7-4] S[3-0]

@8 @2 @3 @8 @2 @3 @7 @2 @3 @4 @2 @3
@5 @5 @4
P3 G3 C3 P2 G2 C2 P1 G1 C1 P0 G0
C16 C4 C0 C0
@4 Lookahead Carry Unit @0
P3-0 G3-0
@3 @5

CS 150 - Fall 2000 - Combinational Examples - 37

Carry-Select Adder

 Redundant hardware to make carry calculation go faster

Compute two high-order sums in parallel while waiting for carry-in
One assuming carry-in is 0 and another assuming carry-in is 1
Select correct result once carry-in is finally computed

C8 4-bit adder 1 adder

[7:4] high

C8 4-bit adder 0
[7:4] adder
low

five 1 0 1 0 10 1 0 1 0 C4 4-Bit Adder C0

2:1 mux [3:0]

C8 S7 S6 S5 S4 S3 S2 S1 S0
CS 150 - Fall 2000 - Combinational Examples - 38
Arithmetic Logic Unit Design Specification

M = 0, logical bitwise operations

S1 S0 Function Comment
0 0 Fi = Ai input Ai transferred to output
0 1 Fi = not Ai complement of Ai transferred to output
1 0 Fi = Ai xor Bi compute XOR of Ai, Bi
1 1 Fi = Ai xnor Bi compute XNOR of Ai, Bi
M = 1, C0 = 0, arithmetic operations
0 0 F=A input A passed to output
0 1 F = not A complement of A passed to output
1 0 F = A plus B sum of A and B
1 1 F = (not A) plus B sum of B and complement of A
M = 1, C0 = 1, arithmetic operations
0 0 F = A plus 1 increment A
0 1 F = (not A) plus 1 twos complement of A
1 0 F = A plus B plus 1 increment sum of A and B
1 1 F = (not A) plus B plus 1 B minus A

logical and arithmetic operations

not all operations appear useful, but "fall out" of internal logic
CS 150 - Fall 2000 - Combinational Examples - 39
Arithmetic Logic Unit Design (cont’d)
M S1 S0 Ci Ai Bi Fi Ci+1

 Sample ALU – truth table

0 0 0 X 0 X 0 X
X 1 X 1 X
0 1 X 0 X 1 X
X 1 X 0 X
1 0 X 0 0 0 X
X 0 1 1 X
X 1 0 1 X
X 1 1 0 X
1 1 X 0 0 1 X
X 0 1 0 X
X 1 0 0 X
X 1 1 1 X
1 0 0 0 0 X 0 X
0 1 X 1 X
0 1 0 0 X 1 X
0 1 X 0 X
1 0 0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 1 0 0 0 1 0
0 0 1 0 1
0 1 0 0 0
0 1 1 1 0
1 0 0 1 0 X 1 0
1 1 X 0 1
0 1 1 0 X 0 1
1 1 X 1 0
1 0 1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
1 1 1 0 0 0 1
1 0 1 1 1
1 1 0 1 0
1 1 1 0 1
CS 150 - Fall 2000 - Combinational Examples - 40
 Arithmetic Logic Unit Design (cont’d)

 Sample ALU – multi-level discrete gate logic

implementation
\S1 [35] M
\Bi Ci Ci
[33] \Co
Ci
M [30] Co [30]
[33]
S1 [33] [33] Fi
Bi \Co
M
Ci [30]
[35]
S0 [30] [30]
\Co
Ai \[30]
\[35]

12 gates

CS 150 - Fall 2000 - Combinational Examples - 41

 Arithmetic Logic Unit Design (cont’d)

 Sample ALU – clever multi-level implementation

S1 Bi S0 Ai M Ci first-level gates
use S0 to complement Ai
A1 X1 A2
S0 = 0 causes gate X1 to pass Ai
S0 = 1 causes gate X1 to pass Ai'
use S1 to block Bi
S1 = 0 causes gate A1 to make Bi go forward as 0
(don't want Bi for operations with just A)
S1 = 1 causes gate A1 to pass Bi
use M to block Ci
X2 M=0 causes gate A2 to make Ci go forward as 0
(don't want Ci for logical operations)
M=1 causes gate A2 to pass Ci

other gates
for M=0 (logical operations, Ci is ignored)
A3 A4
Fi = S1 Bi xor (S0 xor Ai)
= S1'S0' ( Ai ) + S1'S0 ( Ai' ) +
S1 S0' ( Ai Bi' + Ai' Bi ) + S1 S0 ( Ai' Bi' + Ai Bi )
for M=1 (arithmetic operations)
Fi = S1 Bi xor ( ( S0 xor Ai ) xor Ci ) =
O1
X3
Ci+1 = Ci (S0 xor Ai) + S1 Bi ( (S0 xor Ai) xor Ci ) =

just a full adder with inputs S0 xor Ai, S1 Bi, and Ci

Ci+1 Fi
CS 150 - Fall 2000 - Combinational Examples - 42
Summary for Examples of Combinational Logic
 Combinational logic design process
Formalize problem: encodings, truth-table, equations
Choose implementation tech (ROM, PAL, PLA, discrete gates)
Implement by following the design procedure for that technology
 Binary number representation
Positive numbers the same
Difference is in how negative numbers are represented
2s complement easiest to handle: one representation for zero,
slightly complicated complementation, simple addition
 Circuits for binary addition
Basic half-adder and full-adder
Carry lookahead logic
Carry-select
 ALU Design
Specification, implementation
CS 150 - Fall 2000 - Combinational Examples - 43