Vlsi/Fpga Design and Test CAD Tool Flow in Mentor Graphics: Victor P. Nelson
Vlsi/Fpga Design and Test CAD Tool Flow in Mentor Graphics: Victor P. Nelson
Vlsi/Fpga Design and Test CAD Tool Flow in Mentor Graphics: Victor P. Nelson
Victor P. Nelson
Physical
DRC & LVS Verify
Layout
Verification Timing
Map/Place/Route
Simulation Input
ADVance MS
Setup Stimuli
Mixed Signal
Eldo, EZwave (VHDL-AMS,
Eldo RF or Xelga ModelSim Verilog-A)
Analog View Results
Mach TA Digital
(SPICE)
Feb 15, 2006 VLSI D&T Seminar
(VHDL,Verilog) 7
Example: 4-bit binary counter
VHDL model (count4.vhd)
– Create working library: vlib work
vmap work work
– Compile: vcom count4.vhd
– Simulate: vsim count4(rtl)
ModelSim simulation-control inputs
– ModelSim “Macro” (count4_rtl.do)
– OR, VHDL testbench
ModelSim results
– listing or waveform
Feb 15, 2006 VLSI D&T Seminar 8
-- count4.vhd 4-bit parallel-load synchronous counter
LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.numeric_std.all;
ENTITY count4 IS
PORT (clock,clear,enable,load_count : IN STD_LOGIC;
D: IN unsigned(3 downto 0);
Q: OUT unsigned(3 downto 0));
END count4;
Clear
Counting
Parallel
Load
Feb 15, 2006 VLSI D&T Seminar 11
Automated Synthesis with
Leonardo Spectrum
VHDL/Verilog
Technology Behavioral/RTL Models
Synthesis
Libraries
wire nx8, nx14, nx22, nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181, nx183, nx185, nx187,
nx189;
wire [3:0] \$dummy ;
dffr Q_0__rename_rename (.Q (Q[0]), .QB (\$dummy [0]), .D (nx126), .CLK (clock), .R (clear)) ;
mux21_ni ix127 (.Y (nx126), .A0 (Q[0]), .A1 (nx8), .S0 (enable)) ;
oai21 ix9 (.Y (nx8), .A0 (load_count), .A1 (Q[0]), .B0 (nx169)) ;
nand02 ix170 (.Y (nx169), .A0 (D[0]), .A1 (load_count)) ;
dffr Q_1__rename_rename (.Q (Q[1]), .QB (\$dummy [1]), .D (nx136), .CLK (clock), .R (clear)) ;
mux21_ni ix137 (.Y (nx136), .A0 (Q[1]), .A1 (nx28), .S0 (enable)) ;
ao22 ix29 (.Y (nx28), .A0 (D[1]), .A1 (load_count), .B0 (nx14), .B1 (nx22) ) ;
or02 ix15 (.Y (nx14), .A0 (Q[0]), .A1 (Q[1])) ;
aoi21 ix23 (.Y (nx22), .A0 (Q[1]), .A1 (Q[0]), .B0 (load_count)) ;
dffr Q_2__rename_rename (.Q (Q[2]), .QB (\$dummy [2]), .D (nx146), .CLK (clock), .R (clear)) ;
mux21_ni ix147 (.Y (nx146), .A0 (Q[2]), .A1 (nx48), .S0 (enable)) ;
oai21 ix49 (.Y (nx48), .A0 (nx181), .A1 (nx183), .B0 (nx189)) ;
aoi21 ix182 (.Y (nx181), .A0 (Q[1]), .A1 (Q[0]), .B0 (Q[2])) ;
nand02 ix184 (.Y (nx183), .A0 (nx185), .A1 (nx187)) ;
inv01 ix186 (.Y (nx185), .A (load_count)) ;
nand03 ix188 (.Y (nx187), .A0 (Q[2]), .A1 (Q[1]), .A2 (Q[0])) ;
nand02 ix190 (.Y (nx189), .A0 (D[2]), .A1 (load_count)) ;
dffr Q_3__rename_rename (.Q (Q[3]), .QB (\$dummy [3]), .D (nx156), .CLK (clock), .R (clear)) ;
mux21_ni ix157 (.Y (nx156), .A0 (Q[3]), .A1 (nx62), .S0 (enable)) ;
mux21_ni ix63 (.Y (nx62), .A0 (nx54), .A1 (D[3]), .S0 (load_count)) ;
xnor2 ix55 (.Y (nx54), .A0 (Q[3]), .A1 (nx187)) ;
Feb 15, 2006
endmodule VLSI D&T Seminar 15
Post-synthesis simulation
(with Leonardo-generated netlist)
Verify synthesized netlist vs behavioral model
Create simulation primitives library for std cells:
>vlib adk
>vcom $ADK/technology/adk.vhd
>vcom $ADK/technology/adk_comp.vhd
Insert library/package declaration in netlist
library adk;
use adk.adk_components.all;
Simulate in Modelsim, using “do file” from behavioral
simulation – results should be same
Memory
& Logic
BIST Boundary
Scan
Internal
Scan Design
ATPG
count4.vhd
count4_0.vhd
count4.v
DFT/ATPG count4_scan.v
Library:
adk.atpg
Layout vs.
Generate Design Rule Backannotate
Schematic
Mask Data Check Schematic
Check
Calibre Calibre Calibre
IC15,Mask
Feb 2006 Data Mach
VLSI TA/Eldo
D&T Seminar Simulation Model 25
Preparation for Layout
1. Use Design Architect-IC to convert Verilog netlist to
Mentor Graphics “EDDM” schematic/netlist format
– Invoke Design Architect-IC (adk_daic)
– On menu bar, select File > Import Verilog
Netlist file: count4.v (the Verilog netlist)
Output directory: count4 (for the EDDM netlist)
Mapping file $ADK/technology/adk_map.vmp
2. Open the generated schematic for viewing
– Click Schematic in DA-IC palette
– Select schematic in directory named above (see next slide)
– Click Update LVS in the schematic palette to create a netlist to
be used later by “Calibre”
3. Create design viewpoints for ICstation tools
– adk_dve count4 –t tsmc035 (V.P’s: layout, lvs, sdl, tsmc035)
Can also create gate/transistor schematics directly in
DA-IC using components from the ADK library
Feb 15, 2006 VLSI D&T Seminar 26
DA-IC generated schematic
Feb 15, 2006 VLSI D&T SeminarSource: Weste “CMOS VLSI Design”
32
Auto “floorplan” the block
place & route > autofp
Draw
rectangle
of metal2
to fill gap
Xilinx “ISE”
Altera “Max Plus 2” Map to FPGA
LUTs, FFs, IOBs
FPGA/PLD
User-Specified Technology
Place & Route Files
Constraints
Generate
Generate
Programming
Timing Model
Data