VLSI/FPGA

Design and Test Flow with

Mentor Graphics CAD Tools

Victor P. Nelson
 Mentor Graphics CAD Tool Suites
„ IC/SoC design flow1
„ DFT/BIST/ATPG design flow1
„ FPGA design flow2,3
„ PCB design flow2
„ Digital/analog/mixed-signal modeling & simulation1,2
„ ASIC/FPGA synthesis1,2
„ Vendor-provided (Xilinx,Altera,etc.) back end tools2

1. User-setup selection: eda/mentor/ICFlow2006.1

2. User-setup selection: eda/mentor/EN2002.3
3. User-setup selection: eda/mentor/FPGA
 Mentor Graphics CAD Tools
(select “eda/mentor” in user-setup on the Sun network*)

„ ICFlow2006.1– For custom & standard cell IC designs

– IC flow tools (Design Architect-IC, IC Station, Calibre)
– Digital/analog/mixed simulation (Modelsim,ADVance MS,Eldo,MachTA)
– HDL Synthesis (Leonardo)
– ATPG/DFT/BIST tools (DFT Advisor, Flextest, Fastscan)
– Limited access to Quicksim II (some technologies)
„ EN2002u3 – For FPGA “front end” design & printed circuit boards
– Design Architect, Quicksim II, Quicksim Pro (Schematic/Simulation)
– ModelSim & Leonardo (HDL Simulation/Synthesis)
– Xilinx ISE & Altera “Quartus” tools (Back end design)
„ FPGA (FPGA Advantage, Modelsim, Leonardo)

*Only one of the above three groups may be selected at a time

 Mentor Graphics ASIC Design Kit (ADK)
„ Technology files & standard cell libraries
– AMI: ami12, ami05 (1.2, 0.5 μm)
– TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25, 0.18 μm)

„ IC flow & DFT tool support files:

– Simulation
ƒ VHDL/Verilog/Mixed-Signal models (Modelsim/ADVance MS)
ƒ Analog (SPICE) models (Eldo/Accusim)
ƒ Post-layout timing (Mach TA)
ƒ Digital schematic (Quicksim II, Quicksim Pro) (exc. tsmc025,tsmc018)
– Synthesis to std. cells (LeonardoSpectrum)
– Design for test & ATPG (DFT Advisor, Flextest/Fastscan)
– Schematic capture (Design Architect-IC)
– IC physical design (standard cell & custom)
ƒ Floorplan, place & route (IC Station)
ƒ Design rule check, layout vs schematic, parameter extraction (Calibre)
 Xilinx/Altera FPGA/CPLD Design
„ Technology files & libraries for front-end design with
Mentor Graphics tools
– Schematic symbols for Design Architect
– Simulation models for Quicksim II, Quicksim Pro
– Synthesis library for Leonardo
„ Vendor tools for back-end design
(map, place, route, configure, timing)
– Xilinx Integrated Software Environment (ISE)
ƒ Xilinx XST can synthesize the design from VHDL or Verilog (instead
of Leonardo)
– Altera Quartus II & Max+Plus2
 ASIC Design Flow
Behavioral
Verify
Model
Function
VHDL/Verilog
Synthesis
DFT/BIST Gate-Level Verify
& ATPG Netlist Function

Test vectors Full-custom IC

Transistor-Level Verify Function

Standard Cell IC Netlist & Timing
& FPGA/CPLD

Physical
DRC & LVS Verify
Layout
Verification Timing
Map/Place/Route

IC Mask Data/FPGA Configuration File

Behavioral Design & Verification
(mostly technology-independent)

VHDL VHDL-AMS
Verilog Create Behavioral/RTL
HDL Model(s) Verilog-A
SystemC

ModelSim Simulate to Verify ADVance MS

(digital) Functionality (analog/mixed signal)

Leonardo Synthesize Gate-Level

Spectrum Circuit
(digital)
Technology Libraries
Post-Layout Simulation,
Technology-Specific Netlist
to Back-End Tools
ADVance MS Simulation System
„ ADVance MS “kernel” supports:
– VHDL & Verilog: digital (via ModelSim)
– VHDL-AMS & Verilog-A: analog/mixed signal
– Eldo/SPICE: analog (via Eldo)
– Eldo RF/SPICE: analog RF (via Eldo RF)
– Mach TA/SPICE: high-speed analog/timing
„ Invoke stand-alone or from Design Architect-IC

„ Mentor Graphics “Legacy” Simulators (PCB design)

– Quicksim II, Quicksim Pro (digital)
– ASIC: adk_quicksim
– FPGA/PLD: Xilinx: pld_quicksim, Altera: max2_quicksim
– Accusim (analog): adk_accusim
 ADVance MS
Digital, Analog, Mixed-Signal Simulation
VHDL,Verilog,
VHDL-AMS, Verilog-A,
SPICE Netlists SPICE
VITAL
models
Working Design_1
Library Design_2 IEEE 1164 Resource
Libraries

Simulation Input
ADVance MS
Setup Stimuli

Mixed Signal
Eldo, EZwave (VHDL-AMS,
Eldo RF or Xelga ModelSim Verilog-A)
Analog Mach TA View Results
(SPICE) Mach PA Digital
(VHDL,Verilog)
 Example: 4-bit binary counter
„ VHDL model (count4.vhd)
– Create working library: vlib work
vmap work work
– Compile: vcom count4.vhd
– Simulate: vsim count4(rtl)
„ ModelSim simulation-control inputs
– ModelSim “Macro” (count4_rtl.do)
– OR, VHDL testbench
„ ModelSim results
– listing or waveform
-- count4.vhd 4-bit parallel-load synchronous counter
LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.numeric_std.all;

ENTITY count4 IS
PORT (clock,clear,enable,load_count : IN STD_LOGIC;
D: IN unsigned(3 downto 0);
Q: OUT unsigned(3 downto 0));
END count4;

ARCHITECTURE rtl OF count4 IS

SIGNAL int : unsigned(3 downto 0);
BEGIN
PROCESS(clear, clock, enable)
BEGIN
IF (clear = '1') THEN
int <= "0000";
ELSIF (clock'EVENT AND clock='1') THEN
IF (enable = '1') THEN
IF (load_count = '1') THEN
int <= D;
ELSE
int <= int + "01";
END IF;
END IF;
END IF;
END PROCESS;
Q <= int;
END rtl;
 Test stimulus:
Modelsim “do” file: count4_rtl.do

add wave /clock /clear /enable /load_count /D /Q

add list /clock /clear /enable /load_count /D /Q
force /clock 0 0, 1 10 -repeat 20
force /clear 0 0, 1 5, 0 10
force /enable 0 0, 1 25
force /load_count 0 0, 1 20, 0 35, 1 330, 0 350
force /D 10#5 0, 10#9 300
run 400
 Testbench: count4_bench.vhd
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all;

ENTITY count4_bench is end count4_bench;

ARCHITECTURE test of count4_bench is
component count4
PORT (clock,clear,enable,load_count : IN STD_LOGIC;
D: IN unsigned(3 downto 0);
Q: OUT unsigned(3 downto 0));
end component;
for all: count4 use entity work.count4(behavior);
signal clk : STD_LOGIC := '0';
signal clr, en, ld: STD_LOGIC; Alternative
signal din, qout: unsigned(3 downto 0);
begin to “do” file
UUT: count4 port map(clk,clr,en,ld,din,qout);
clk <= not clk after 10 ns;
P1: process
begin
din <= "0101"; clr <= '1'; en <= '1'; ld <= '1';
wait for 10 ns;
clr <= '0';
wait for 20 ns;
ld <= '0'; Could also check results &
wait for 200 ns;
end process; “assert” error messages
end;
Count4 – Simulation waveform

Clear
Counting
Parallel
Load
ADVance MS : mixed-signal simulation

A/D converter

digital

analog
VHDL-AMS
ADVance MS: mixed Verilog-SPICE

Verilog top
(test bench)

SPICE
subcircuit
 Automated Synthesis with
Leonardo Spectrum
VHDL/Verilog
Technology Behavioral/RTL Models
Synthesis
Libraries

FPGA Leonardo Spectrum Design

(Level 3) Constraints
ASIC

ADK Level 1 – FPGA

AMI 0.5, 1.2 Technology-
Specific
Level 2 – FPGA + Timing
TSMC 0.35, 0.25
Netlist

VHDL, Verilog, SDF,

EDIF, XNF
Leonardo – ASIC Synthesis Flow
 Leonardo synthesis procedure
1. Invoke leonardo
2. Select & load a technology library (ASIC or FPGA)
– ASIC > ADK > TSMC 0.35 micron
3. Read input VHDL/Verilog file(s): count4.vhd
4. Enter any constraints (clock freq, delays, etc.)
5. Optimize for area/delay/effort level
6. Write output file(s)
– count4_0.vhd - VHDL netlist
– count4.v - Verilog netlist (for IC layout)
– count4.sdf - Standard delay format file (for timing)
– count4.edf - EDIF netlist (for Xilinx/Altera FPGA)
Leonardo-synthesized netlist count4_0.vhd
library IEEE; use IEEE.STD_LOGIC_1164.all;
library adk;
adk; use adk.adk_components.all;
adk.adk_components.all; -- ADDED BY VPN
entity count4 is
port (
clock : IN std_logic ; clear : IN std_logic ; enable : IN std_logic ; load_count : IN std_logic ;
D : IN std_logic_vector (3 DOWNTO 0) ; Q : OUT std_logic_vector (3 DOWNTO 0)) ;
end count4 ;

architecture netlist of count4 is -- rtl changed to netlist by VPN

signal Q_3_EXMPLR, Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, nx8, nx14, nx14, nx22,
nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181,
nx183, nx185, nx187, nx189: std_logic ;
begin
Q(3) <= Q_3_EXMPLR ; Q(2) <= Q_2_EXMPLR ; Q(1) <= Q_1_EXMPLR
Q_1_EXMPLR ; Q(0) <= Q_0_EXMPLR ;
Q_0_EXMPLR_EXMPLR : dffr port map ( Q=>Q_0_EXMPLR, QB=>OPEN, D=>nx126, CLK=>clock, R=>clear); R=>clear);
ix127 : mux21_ni port map ( Y=>nx126, A0=>Q_0_EXMPLR, A1=>nx8,
A1=>nx8, S0=>enable );
ix9 : oai21 port map ( Y=>nx8, A0=>load_count
A0=>load_count,, A1=>Q_0_EXMPLR, B0=>nx169 );
ix170 : nand02 port map ( Y=>nx169, A0=>D(0), A1=>load_count
A1=>load_count););
Q_1_EXMPLR_EXMPLR : dffr port map ( Q=>Q_1_EXMPLR, QB=>OPEN, D=>nx136, CLK=>clock, R=>clear);
ix137 : mux21_ni port map ( Y=>nx136, A0=>Q_1_EXMPLR, A1=>nx28,
A1=>nx28, S0=> enable);
ix29 : ao22 port map ( Y=>nx28, A0=>D(1), A1=>load_count
A1=>load_count,, B0=>nx14, B1=> nx22);
ix15 : or02 port map ( Y=>nx14, A0=>Q_0_EXMPLR, A1=>Q_1_EXMPLR);
A1=>Q_1_EXMPLR);
ix23 : aoi21 port map ( Y=>nx22, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR,
A1=>Q_0_EXMPLR, B0=> load_count);
load_count);
Q_2_EXMPLR_EXMPLR : dffr port map ( Q=>Q_2_EXMPLR, QB=>OPEN, D=>nx146, CLK=>clock, R=>clear); R=>clear);
ix147 : mux21_ni port map ( Y=>nx146, A0=>Q_2_EXMPLR, A1=>nx48,
A1=>nx48, S0=> enable);
ix49 : oai21 port map ( Y=>nx48, A0=>nx181, A1=>nx183, B0=>nx189);
B0=>nx189);
ix182 : aoi21 port map ( Y=>nx181, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR,
A1=>Q_0_EXMPLR, B0=> Q_2_EXMPLR);
ix184 : nand02 port map ( Y=>nx183, A0=>nx185, A1=>nx187);
ix186 : inv01 port map ( Y=>nx185, A=>load_count
A=>load_count););
ix188 : nand03 port map ( Y=>nx187, A0=>Q_2_EXMPLR, A1=>Q_1_EXMPLR,
A1=>Q_1_EXMPLR, A2=> Q_0_EXMPLR);
ix190 : nand02 port map ( Y=>nx189, A0=>D(2), A1=>load_count
A1=>load_count););
Q_3_EXMPLR_EXMPLR : dffr port map ( Q=>Q_3_EXMPLR, QB=>OPEN, D=>nx156, CLK=>clock, R=>clear); R=>clear);
ix157 : mux21_ni port map ( Y=>nx156, A0=>Q_3_EXMPLR, A1=>nx62,
A1=>nx62, S0=> enable);
ix63 : mux21_ni port map ( Y=>nx62, A0=>nx54, A1=>D(3), S0=> S0=>load_count);
load_count);
ix55 : xnor2 port map ( Y=>nx54, A0=>Q_3_EXMPLR, A1=>nx187);
A1=>nx187);
end netlist ;
// Verilog description for cell count4, LeonardoSpectrum Level 3, 2005a.82
module count4 ( clock, clear, enable, load_count,
load_count, D, Q ) ;
input clock ;
input clear ;
input enable ;
input load_count ;
input [3:0]D ;
output [3:0]Q ;

wire nx8, nx14, nx22, nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181, nx183, nx185, nx187,
nx189;
wire [3:0] \$dummy ;

dffr Q_0__rename_rename (.Q (Q[0]), .QB (\ (\$dummy [0]), .D (nx126), .CLK (clock), .R (clear)) ;
mux21_ni ix127 (.Y (nx126), .A0 (Q[0]), .A1 (nx8), .S0 (enable))
(enable)) ;
oai21 ix9 (.Y (nx8), .A0 (load_count
(load_count),
), .A1 (Q[0]), .B0 (nx169)) ;
nand02 ix170 (.Y (nx169), .A0 (D[0]), .A1 (load_count
(load_count)))) ;
dffr Q_1__rename_rename (.Q (Q[1]), .QB (\ (\$dummy [1]), .D (nx136), .CLK (clock), .R (clear)) ;
mux21_ni ix137 (.Y (nx136), .A0 (Q[1]), .A1 (nx28), .S0 (enable))
(enable)) ;
ao22 ix29 (.Y (nx28), .A0 (D[1]), .A1 (load_count
(load_count), ), .B0 (nx14), .B1 (nx22) ) ;
or02 ix15 (.Y (nx14), .A0 (Q[0]), .A1 (Q[1])) ;
aoi21 ix23 (.Y (nx22), .A0 (Q[1]), .A1 (Q[0]), .B0 (load_count
(load_count))
)) ;
dffr Q_2__rename_rename (.Q (Q[2]), .QB (\ (\$dummy [2]), .D (nx146), .CLK (clock), .R (clear)) ;
mux21_ni ix147 (.Y (nx146), .A0 (Q[2]), .A1 (nx48), .S0 (enable))
(enable)) ;
oai21 ix49 (.Y (nx48), .A0 (nx181), .A1 (nx183), .B0 (nx189))
(nx189)) ;
aoi21 ix182 (.Y (nx181), .A0 (Q[1]), .A1 (Q[0]), .B0 (Q[2])) ;
nand02 ix184 (.Y (nx183), .A0 (nx185), .A1 (nx187)) ;
inv01 ix186 (.Y (nx185), .A (load_count
(load_count)))) ;
nand03 ix188 (.Y (nx187), .A0 (Q[2]), .A1 (Q[1]), .A2 (Q[0]))
(Q[0])) ;
nand02 ix190 (.Y (nx189), .A0 (D[2]), .A1 (load_count
(load_count)))) ;
dffr Q_3__rename_rename (.Q (Q[3]), .QB (\ (\$dummy [3]), .D (nx156), .CLK (clock), .R (clear)) ;
mux21_ni ix157 (.Y (nx156), .A0 (Q[3]), .A1 (nx62), .S0 (enable))
(enable)) ;
mux21_ni ix63 (.Y (nx62), .A0 (nx54), .A1 (D[3]), .S0 (load_count
(load_count)))) ;
xnor2 ix55 (.Y (nx54), .A0 (Q[3]), .A1 (nx187)) ;
endmodule
 Post-synthesis simulation
(Leonardo-generated netlist)
„ Verify synthesized netlist matches behavioral
model
„ Create simulation primitives library for std cells:
>vlib adk VITAL
>vcom $ADK/technology/adk.vhd models of all
>vcom $ADK/technology/adk_comp.vhd
ADK std cells
„ Insert library/package declaration into netlist
library adk;
use adk.adk_components.all;

„ Simulate in Modelsim, using “do file” or test bench from

original behavioral simulation
– results should match
 Post-synthesis timing analysis
„ Leonardo can generate SDF (std. delay format) file with
technology-specific, VITAL-compliant timing parameters.
(CELLTYPE "dffr")
(INSTANCE Q_0_EXMPLR_EXMPLR)
(DELAY
(ABSOLUTE
(PORT D (::0.00) (::0.00))
(PORT CLK (::0.00) (::0.00))
(PORT R (::0.00) (::0.00))
(IOPATH CLK Q (::0.40) (::0.47))
(IOPATH R Q (::0.00) (::0.55))
(IOPATH CLK QB (::0.45) (::0.36))
(IOPATH R QB (::0.53) (::0.00))))
(TIMINGCHECK
(SETUP D (posedge CLK) (0.47))
(HOLD D (posedge CLK) (-0.06))))
 Design for test & test generation
„ Consider test during the design phase
– Test design more difficult after design frozen
„ Basic steps:
– Design for test (DFT) – insert test points, scan
chains, etc. to improve testability
– Insert built-in self-test (BIST) circuits
– Generate test patterns (ATPG)
– Determine fault coverage (Fault Simulation)
 DFT & test design flow

Memory
& Logic
BIST Boundary
Scan

Internal
Scan Design

ATPG
 DFTadvisor/FastScan Design Flow

count4.vhd

count4_0.vhd
count4.v

DFT/ATPG count4_scan.v
Library:
adk.atpg

Source: FlexTest Manual

 ASIC DFT Flow
Synthesized VHDL/Verilog Netlist

ATPG Library
DFT Advisor Insert Internal
Scan Circuitry
adk.atpg
VHDL/Verilog
Netlist With
Scan Elements

Fastscan/ Generate/Verify
Flextest Test Vectors

Test Pattern File

 Example DFTadvisor session
„ Invoke:
– dftadvisor –verilog count4.v –lib $ADK/technology/adk.atpg

„ Implement scan with defaults:

(full scan, mux-DFF scan elements)
– set system mode setup
– analyze control signals –auto
– set system mode dft
– run
– insert test logic
– write netlist count4_scan.v –verilog
– write atpg setup count4_scan
(creates count4_scan.dofile for ATPG in Fastscan)
count4 – without scan design
count4 – scan inserted by DFTadvisor
 ATPG with FastScan
(full-scan circuit)
„ Invoke:
– fastscan –verilog count4.v –lib $ADK/technology/adk.atpg
„ Generate test pattern file:
– dofile count4_scan.dofile (defines scan path & procedure)
– set system mode atpg
– create patterns –auto (generate test patterns)
– save patterns

Note: “count4_scan.dofile” created by DFTadvisor

 Test file: scan chain definition and
load/unload procedures
scan_group "grp1" =
scan_chain "chain1" =
scan_in = "/scan_in1";
scan_out = "/output[3]";
length = 4;
end;
procedure shift "grp1_load_shift" = procedure load "grp1_load" =
force_sci "chain1" 0; force "/clear" 0 0;
force "/clock" 1 20; force "/clock" 0 0;
force "/clock" 0 30; force "/scan_en" 1 0;
period 40; apply "grp1_load_shift" 4 40;
end; end;
procedure shift "grp1_unload_shift" = procedure unload "grp1_unload" =
measure_sco "chain1" 10; force "/clear" 0 0;
force "/clock" 1 20; force "/clock" 0 0;
force "/clock" 0 30; force "/scan_en" 1 0;
period 40; apply "grp1_unload_shift" 4 40;
end; end;
end;
 Generated scan-based test
// send a pattern through the scan chain
CHAIN_TEST =
pattern = 0;
apply "grp1_load" 0 = (use grp1_load procedure)
chain "chain1" = "0011"; (pattern to scan in)
end;
apply "grp1_unload" 1 = (use grp1_unload procedure)
chain "chain1" = "1100"; (pattern scanned out)
end;
end;
// one of 14 patterns for the counter circuit
pattern = 0; (pattern #)
apply "grp1_load" 0 = (load scan chain)
chain "chain1" = "1000"; (scan-in pattern)
end;
force "PI" "00110" 1; (PI pattern)
measure "PO" "0010" 2; (expected POs)
pulse "/clock" 3; (normal op. cycle)
apply "grp1_unload" 4 = (read scan chain)
chain "chain1" = "0110"; (expected pattern)
end;
 ASIC Physical Design (Standard Cell)
(can also do full custom layout)
Component-Level Netlist (EDDM format)

Std. Cell Mentor Graphics

Floorplan
Layouts
Chip/Block
“IC Station”
Libraries (adk_ic)
ICblocks
Process Data
Place & Route
Design Rules Std. Cells

Layout vs.
Generate Design Rule Backannotate
Schematic
Mask Data Check Schematic
Check
Calibre Calibre Calibre
IC Mask Data Mach TA/Eldo Simulation Model
Cell-Based IC
Cell-Based Block
Basic standard
Cell layout

Source: Weste “CMOS VLSI Design”

 Preparation for Layout
1. Use Design Architect-IC to convert Verilog netlist to
Mentor Graphics EDDM netlist format
– Invoke Design Architect-IC (adk_daic)
– On menu bar, select File > Import Verilog
ƒ Netlist file: count4.v (the Verilog netlist)
ƒ Output directory: count4 (for the EDDM netlist)
ƒ Mapping file $ADK/technology/adk_map.vmp
2. Open the generated schematic for viewing
– Click Schematic in DA-IC palette
– Select schematic in directory named above (see next slide)
– Click Update LVS in the schematic palette to create a netlist to
be used later by “Calibre”
3. Create design viewpoints for ICstation tools
– adk_dve count4 –t tsmc035 (V.P’s: layout, lvs, sdl, tsmc035)
„ Can also create gate/transistor schematics directly in
DA-IC using components from the ADK library
DA-IC generated schematic
 Eldo simulation from DA-IC
„ Run simulations from within DA-IC
– Eldo, ADVance MS, Mach TA
„ DA-IC invokes a “netlister” to create a
circuit model from the schematic
– SPICE model for Eldo & Mach TA
„ Eldo analyses, forces, probes, etc. same
as SPICE
„ View results in EZwave or Xelga
Eldo input and output files

-Netlist
-Simulation cmds
-Stimulus
SPICE “circuit” file generated by DA-IC SPICE netlist for modulo7 counter

From ADK
library

Force values (created interactively)

Eldo simulation of modulo7 counter
(transient analysis)
Create a std-cell based logic block
in IC Station
„ Invoke: adk_ic
„ In IC Station palette, select: Create Cell
– Cell name: count4
– Attach library: $ADK/technology/ic/process/tsmc035
– Process: $ADK/technology/ic/process/tsmc035
– Rules file: $ADK/technology/ic/process/tsmc035.rules
– Angle mode: 45
– Cell type: block
– Select With connectivity
– EDDM schematic viewpoint: count4/layout
– Logic loading options: flat
Create Cell dialog box
Auto-”floorplan” the block
place & route > autofp
Auto-place the std cells
Autoplc > StdCel
Auto-place “ports” (Autoplc > Ports)
Signal connections on cell boundaries
 AutoRoute all nets
(hand-route any unrouted “overflows”)
Then: Add > Port Text to copy port names from schematic – for Calibre
Layout design rule check (DRC)
„ Technology-specific design rules specify
minimum sizes, spacing, etc. of features
to ensure reliable fabrication
– Design rules file specified at startup
Ex. tsmc035.rules
„ From main palette, select ICrules
– Click Check and then OK in prompt box
(can optionally select a specific area to check)
– Rules checked in numeric order
 Common errors detected by DRC
„ To fix, click on First in palette to highlight first
error
– Error is highlighted in the layout
– Click View to zoom in to the error (see next)
– Example: DRC9_2: Metal2 spacing = 3L
– Fix by drawing a rectangle of metal2 to fill in the gap
between contacts that should be connected
„ Click Next to go to next error, until all are fixed

NOTE: There can be no DRC errors if MOSIS is to

fabricate the chip – they will run their own DRC.
Error: DRC9_2 metal2 spacing = 3L

Draw
rectangle
of metal2
to fill gap

It also called contact-to-contact metal 2 spacing DRC9 2 error

 Layout vs schematic check
Calibre Interactive LVS
„ From ICstation menu: Calibre > Run LVS
– In popup, Calibre location: $MGC_HOME/../Calibre
– Rules: $ADK/technology/ic/process/tsmc035.calibre.rules
– Input: count4.src.net (previously created in DA-IC)
– H-cells: $ADK/technology/adk.hcell (hierarchical cells)
– Extracted file: count4.lay.net
„ Compares extracted transistor-level netlist vs.
netlist saved in DA-IC
 Post-layout parameter extraction
Calibre Interactive PEX
„ Extract Spice netlist, including parasitic RC
– Simulate in Eldo or MachTA
„ ICstation menu: Calibre>Run PEX
– Options similar to Calibre LVS
– Extraction options:
ƒ lumped C + coupling cap’s
ƒ distributed RC
ƒ distributed RC + coupling cap’s
– Output file: count4.pex.netlist
Post-layout simulation with MachTA
„ MachTA is an accelerated Spice simulator
– Digital & mixed-signal circuits
– Analyze timing effects pre- and post-layout
ƒ SPICE netlists with parasitic R/C
– Execute test vector file to verify functionality
„ Algorithms support large designs
– Partition design, simulate only partitions with changes
– Combine time-driven & event-driven operation
– Solves linearized models using a proprietary high-
performance, graph-theory based, matrix solution
algorithm
 Mach TA flow diagram
SPICE
netlist

$ADK/technology/mta/tsmc035
 Post-layout simulation with Mach TA
(netlist extracted by Calibre PEX)
„ Prepare netlist (remove subcircuits for Mach TA)
– Extracted netlist = count4.pex.netlist
– Command: $ADK/bin/mta_prep count4
– Creates SPICE file: count4.sp
„ Invoke Mach TA:
ana - command file to initialize Anacad SW
mta –ezw –t $ADK/technology/mta/tsmc035 count4.sp

‰ Mach PA (mpa) does current & power analysis

 Sample Mach TA “dofile”
(transient analysis)
Signals to observe in EZwave
plot v(clk) v(q[2]) v(q[1]) v(q[0])
measure rising TRIG v(clk) VAL=2.5v RISE=1 TARG v(q[0]) VAL=2.5v
l load
l reset
h count
Measure time from rising edge of clk (TRIGger)
l clk to 1st rising edge of q[0] (TARGet) - voltages
run 5 ns
h reset
h clk Drive signals low/high (Lsim format)
run 5 ns
l clk
run 5 ns Simulate for 5 ns
h clk
run 5 ns

Command to execute: dofile file.do

 EZwave waveform viewer
(results for previous dofile)

Double-click
signal name
to display.
 Alternative Mach TA “dofile”
(same result as previous example)
plot v(clk) v(q[2]) v(q[1]) v(q[0])
measure rising TRIG v(clk) VAL=2.5v RISE=1 TARG v(q[0])
VAL=2.5v
vpulse Vclk clk 0 pulse(0 3.3 10n .05n .05n 10n 20n)
v-levels delay rise fall width period
l load
l reset Nodes to which
h count source connected
Periodic pulses
run 5 ns
h reset Voltage source name

run 200 ns
 Mach TA – test vector file
„ Verify design functionality/behavior
– apply test vectors
– capture outputs
– compare outputs to expected result
– vectors/outputs from behavioral simulation
„ Command to execute a test vector file:
run –tvend tvfile.tv

test vector file (next slide)

 Test vector file format
# Test vector file for modulo7 counter
CODEFILE
UNITS ps
RISE_TIME 50 signal order within vectors
FALL_TIME 50 Header
INPUTS clk,reset,load,count,i[2],i[1],i[0];
OUTPUTS q[2] (to=max),q[1] (to=max),q[0] (to=max);
CODING(ROM)
RADIX <11113>3; Vector format
@0 <01105>X; Sample 5 fs before next vector
@2000 <00105>0;
@7000 <01105>0;
@10000 <11105>5;
@20000 <01015>5; Vectors: @time <input_vector>expected_output
@30000 <11015>6;
@40000 <01015>6;
@50000 <11015>0;
@60000 <01015>0;
…..
END

Test vectors derived from behavioral simulation results

Behavioral simulation listing Corresponding Mach TA test vector file
 Alternate test vector file
(clock generated separately by voltage source)

vpulse vclk clk 0

pulse(0 3.3 10n .5n .5n 10n 20n)

Can mix other simulation

commands with test vector
application.
 Physical Design - FPGA
Component-Level Netlist

Xilinx “ISE”
Altera “Max Plus 2” Map to FPGA
LUTs, FFs, IOBs

FPGA/PLD
User-Specified Technology
Place & Route Files
Constraints

Generate
Generate
Programming
Timing Model
Data

Configuration File Simulation Model

 Xilinx/Altera FPGA/CPLD Design
„ Technology files & libraries for front-end design with
Mentor Graphics tools
– Schematic symbols for Design Architect
– Simulation models for Quicksim II, Quicksim Pro
– Synthesis library for Leonardo
„ Vendor tools for back-end design
(map, place, route, configure, timing)
– Xilinx Integrated Software Environment (ISE)
– Altera Quartus II & Max+Plus2