BOOLEAN VARIABLE MANIPULATION

INSTRUCTIONS
BOOLEAN VARIABLE MANIPULATION
MNEMONIC MNEMONIC

CLR C ORL C,bit

CLR bit ORL C,/bit

MNEMONIC MNEMONIC

SETB C MOV C,bit

SETB bit MOV bit,C
MNEMONIC MNEMONIC
MNEMONIC
CPL C JC rel
CPL bit RL A
JNC rel
MNEMONIC RLC A
JB rel
ANL C,bit RR A
JNB rel
ANL C,/bit RRC A
JBC bit,rel
CLR bitvariable
 Clear bit
 The indicated bit is cleared (reset to
zero).
 CLR can operate on the carry flag or any
directly addressable bit.
 No other flags are affected.
MNEMONIC

CLR C
CLR bit
CLR C
 Clear carry
 The carry bit is cleared (reset to zero).
 No other flags are affected.
 One byte
 12 pulses
 EXAMPLE: CLR C Executing
Executed

Before
CY Execution
AC F0 RS1 After
RS0 Execution
0V - P TIME
PSW A 1 0
78h 0 0 0A 0 78h0 0 D0H
12
11
10
9
8
7
6
5
4
3
2
1
BITPSWD7 D6
80h D5 D4 D3 D2 00h
PSW D1 D0
Address
Clear the carry flag SFR
SFR
FFH FFH
CY 1
0
E0H 78H A E0H 78H A
D0H CY AC
80H F0 RS1 RS0
DOH 0V 00H- P
80H 80H
0
PSW General 0purpose0RAM 0 0 0 purpose
General 0 0
RAMD0H
7FH 7FH
BIT D7 D6 D5 D4 D3 D2 D1 D0
Address

00H 7DH R0 00H 7DH R0

CLR bit
 Clear direct bit
 Two byte instructions
 12 pulses
 EXAMPLE: CLR 0FH Executing
Executed

Before Execution After Execution TIME

21H A 1 0
78h 0 0 0A 0 78h0 0
12
11
10
9
8
7
6
5
4
3
2
1
BIT21H0F 0E
80h 0D 0C 0B
21H 0A 00h09 08
Address
Clear the bit
SFR SFR
FFH FFH
0FH 1
0
E0H 78H A E0H 78H A

80H 80H
0
PSW General 0purpose0RAM 0 0 0 purpose
General 0 0
RAMD0H
7FH 7FH
BIT 0F 0E 0D 0C 0B 0A 09 08
Address 00H
21H 80H 21H

00H 7DH R0 00H 7DH R0

SETB bitvariable
 SET bit
 The indicated bit is set (set to one).
 SET can operate on the carry flag or any
directly addressable bit.
 No other flags are affected.

MNEMONIC

SETB C
SETB bit
SETB C
 SET carry
 The carry bit is set(set to one).
 No other flags are affected.
 One byte
 12 pulses
 EXAMPLE: CLR C Executing
Executed

Before
CY Execution
AC F0 RS1 After
RS0 Execution
0V - P TIME
PSW A 0 0
78h 0 0 0A 0 78h0 0 D0H
12
11
10
9
8
7
6
5
4
3
2
1
BITPSWD7 D6
00h D5 D4 D3 D2 80h
PSW D1 D0
Address
Set the carry flag
SFR SFR
FFH FFH
CY 0
1
E0H 78H A E0H 78H A
D0H CY AC
00H F0 RS1 RS0
DOH 0V 80H- P
80H 80H
1
PSW General 0purpose0RAM 0 0 0 purpose
General 0 0
RAMD0H
7FH 7FH
BIT D7 D6 D5 D4 D3 D2 D1 D0
Address

00H 7DH R0 00H 7DH R0

SETB bit
 Set direct bit
 Two byte instructions
 12 pulses
 EXAMPLE: SETB 0FH Executing
Executed

Before Execution After Execution TIME

21H A 0 0
78h 0 0 0A 0 78h0 0
12
11
10
9
8
7
6
5
4
3
2
1
BIT21H0F 0E
00h 0D 0C 0B
21H 0A 80h09 08
Address
Set the bit
SFR SFR
FFH FFH
0FH 0
1
E0H 78H A E0H 78H A

80H 80H
21H 1 0 0
General purpose RAM
0 0 0 purpose
General 0 0
RAM
7FH 7FH
BIT 0F 0E 0D 0C 0B 0A 09 08
Address
21H 00H 21H 80H

00H 7DH R0 00H 7DH R0

CPL bitvariable
 Compliment bit
 A bit which had been a one is changed to
zero and vice-versa.
 No other flags are affected.
 CPL can operate on the carry or any
directly addressable bit.
MNEMONIC

CPL C
CPL bit
CPL C
 Compliment carry
 The carry bit is complimented
 No other flags are affected.
 One byte
 12 pulses
 EXAMPLE: CPL C Executing
Executed

Before
CY Execution
AC F0 RS1 After
RS0 Execution
0V - P TIME
PSW A 0 0
78h 0 0 0A 0 78h0 0 D0H
12
11
10
9
8
7
6
5
4
3
2
1
BITPSWD7 D6
00h D5 D4 D3 D2 80h
PSW D1 D0
Address
Compliment the carry SFR
SFR flag
FFH FFH
CY 0
1
E0H 78H A E0H 78H A
D0H CY AC
00H F0 RS1 RS0
DOH 0V 80H- P
80H 80H
1
PSW General 0purpose0RAM 0 0 0 purpose
General 0 0
RAMD0H
7FH 7FH
BIT D7 D6 D5 D4 D3 D2 D1 D0
Address

00H 7DH R0 00H 7DH R0

CPL bit
 Compliment direct bit
 Two byte instructions
 12 pulses
 EXAMPLE: CPL 0FH Executing
Executed

Before Execution After Execution TIME

21H A 0 0
78h 0 0 0A 0 78h0 0
12
11
10
9
8
7
6
5
4
3
2
1
BIT21H0F 0E
00h 0D 0C 0B
21H 0A 80h09 08
Address
Compliment the direct SFR
SFR bit
FFH FFH
0FH 0
1
E0H 78H A E0H 78H A

80H 80H
21H 1 0 0
General purpose RAM
0 0 0 purpose
General 0 0
RAM
7FH 7FH
BIT 0F 0E 0D 0C 0B 0A 09 08
Address
21H 00H 21H 80H

00H 7DH R0 00H 7DH R0

 ANL C,sourse bit
 Logical-AND for bit variables
 If the Boolean value of the source bit is a
logical 0 then clear the carry flag; otherwise
leave the carry flag in its current state.
 No other flags are affected.
 Only direct addressing is allowed for the
source operand. MNEMONIC

ANL C,bit
ANL C,/bit
ANL C,bit
 AND direct bit to carry
 No other flags are affected.
 Two byte instruction
 24 pulses
 EXAMPLE: ANL C,bit Executing
Executed

CYExecution
Before AC F0 RS1 After
RS0 Execution
0V - P TIME
PSW 1 0 0 0 0 0 0 0 D0H
21H D7 00h 21H 00hD1
BIT
Address
D6 D5 D4 D3 D2 D0 24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PSW0 80h
0 0 0 PSW
0 0 00h0 0
21H
BIT
Address
0F 0E
SFR
0D 0C 0B 0A
SFR
09 08
FFH Perform logical ANDFFH
operation on bit
CY A
0FHE0H CY A
D0H 1 80H AND PSW 0 DOH = 0 80H PSW
80H 80H
CY AC
General F0RAMRS1
purpose RS0 General
0V purpose
- PRAM
7FH 0
PSW 0 0 0 0
7FH 0 0 0 D0H
BIT D7 D6 D5 D4 D3 D2 D1 D0
21H
Address 00H 21H 00H

00H 7DH R0 00H 7DH R0

ANL C,/bit
 A slash (“/”) preceding the operand in the
assembly language indicates that the
logical complement of the addressed bit is
used as the source value,
but the source bit itself is not affected.
 No other flags are affected.
 Two byte instructions
 12 pulses
 EXAMPLE: ANL C,/bit Executing
Executed

CYExecution
Before AC F0 RS1 After
RS0 Execution
0V - P TIME
PSW 1 0 0 0 0 0 0 0 D0H
21H D7 00h 21H 00hD1
BIT
Address
D6 D5 D4 D3 D2 D0 24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PSW0 80h
0 0 0 PSW
0 0 80h0 0
21H
BIT
Address
0F 0E
SFR
0D 0C 0B 0A
SFR
09 08
FFH Perform logical ANDFFH
operation on bit
CY A
/0FH
E0H
CY A
D0H 1 80H AND PSW /0 DOH= 0 80H PSW
80H 80H
CY AC
General F0RAMRS1
purpose RS0 General
0V purpose
- PRAM
7FH 0
PSW 0 0 0 0
7FH 0 0 0 D0H
BIT D7 D6 D5 D4 D3 D2 D1 D0
21H
Address 00H 21H 00H

00H 7DH R0 00H 7DH R0

 ORL C,sourse bit
 Logical-OR for bit variables
 Set the carry flag if the Boolean value is a
logical 1; leave the carry in its current state
otherwise.
 No other flags are affected.
 Only direct addressing is allowed for the
source operand. MNEMONIC

ORL C,bit
ORL C,/bit
ORL C,bit
 OR direct bit to carry
 No other flags are affected.
 Two byte instruction
 24 pulses
 EXAMPLE:ORL C,bit Executing
Executed

CYExecution
Before AC F0 RS1 After
RS0 Execution
0V - P TIME
PSW 1 0 0 0 0 0 0 0 D0H
21H 00h 21H 80h
BIT D7 D6 D5 D4 D3 D2 D1 D0 24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Address
PSW 80h PSW 80h
21H 0 0 0 0 0 0 0 0
BIT 0F
SFR
0E 0D 0C 0B 0A SFR
09 08
Address
FFH FFH
Perform logical OR operation on bit
CY A 0FHE0H CY A
PSW
D0H
80H
1 80H OR PSW 0 DOH = 1 80H
80H
CY AC
General F0RAMRS1
purpose RS0 General
0V purpose
- PRAM
7FH 1
PSW 0 0 0 0
7FH 0 0 0 D0H
BIT D7 D6
00H D5 D4 D3 D2 D1 D0
21H
Address 21H 80H

00H 7DH R0 00H 7DH R0

ORL C,/bit
 A slash (“/”) preceding the operand in the
assembly language indicates that the
logical complement of the addressed bit is
used as the source value,
but the source bit itself is not affected.
 No other flags are affected.
 Two byte instructions
 12 pulses
 EXAMPLE: ORL C,/bit Executing
Executed
CY AC F0 RS1 RS0 0V - P
PSW 1 Execution
Before 0 0 0 0 Execution
After 0 0 D0H
0 TIME
BIT D7 D6 D5 D4 D3 D2 D1 D0
21H 00h 21H 00h
Address 24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
21H
PSW
0 0 0 0 0
PSW
0 0 0
80h 80h
BIT 0F 0E 0D 0C 0B 0A 09 08
Address
SFR logical OR operation
Perform SFR
on bit
FFH FFH
CY /0FH CY
1 OR A /0 E0H= 1 A
D0H 80H PSW DOH PSW
80H
80H CY AC F0 RS1 RS0
80H 0V - P
1
PSW General 0purpose0RAM 0 0 0 purpose
General 0 0
RAMD0H
7FH D7
BIT D6 D5 D4 D3
7FH D2 D1 D0
Address
21H 00H 21H 00H

00H 7DH R0 00H 7DH R0

BIT RELATED JUMP INSTRUCTIONS

MNEMONIC

JC rel
JNC rel
JB Bit,rel
JNB Bit,rel
JBC bit,rel
JC reladdr

 Jump if carry is set

 JC will branch to the address indicated by
reladdr if the Carry Bit is set.
 If the Carry Bit is not set program
execution continues with the instruction
following the JC instruction.
 Two Byte Instructions
 24 Pulses
JC reladdr

 RELATIVE ADDRESS
 Signed (two's complement) 8-bit offset
byte.
 Range is -128 to +127 bytes relative to
first byte of the following instruction.
 The branch destination is computed by
adding the signed relative-displacement in
the second instruction byte to the PC, after
incrementing the PC twice to point to the
next instruction.
JC reladdr

INSTRUCTIONS
ADDRESS MNEMONICS

1000H MOV A,#30H

1002H ADD A,40H
1004H JC LABEL1
1006H MOV 41H,#01H
1009H LABEL1: MOV 42H,#00H
JC reladdr
1006H = 1004H + 2
 JC
 (PC) ← (PC) + 2
 IF (C) = 1 1009H = 1006H + 03H
 THEN

 (PC) ← (PC) + rel

JC reladdr
INSTRUCTIONS
ADDRESS MNEMONICS

1000H MOV A,#30H

1002H ADD A,40H
1004H JC 03H
1006H MOV 41H,#01H
1009H MOV 42H,#00H
JNC reladdr

 Jump if carry NOT set

 If the carry flag is a zero, branch to the
address indicated; otherwise proceed with
the next instruction.
 Two Byte Instructions
 24 Pulses
JNC reladdr

INSTRUCTIONS
ADDRESS MNEMONICS

1000H LABEL1: ADD A,40H

1002H JNC LABEL1:
1004H MOV 41H,#01H
JNC reladdr
1004H = 1002H + 2
 JNC
 (PC) ← (PC) + 2
 IF (C) = 0 1000H = 1004H +- 04H
FCH
 THEN

 (PC) ← (PC) + rel

JNC reladdr

INSTRUCTIONS
ADDRESS MNEMONICS

1000H ADD A,40H

1002H JNC FCH
1004H MOV 41H,#01H
JB bit,reladdr
 Jump if Bit set
 If the indicated bit is a one, jump to the address
indicated; otherwise proceed with the next instruction.
 The branch destination is computed by adding the
signed relative-displacement in the third instruction
byte to the PC, after incrementing the PC to the
first byte of the next instruction.
 The bit tested is not modified.
 No flags are affected.
 Three byte instruction
 24 pulses
JB bit,reladdr
INSTRUCTIONS
ADDRESS MNEMONICS

1000H MOV A,#30H

1002H ADD A,40H
1004H JB D7H,DOWN
1007H INC R0
1008H DOWN: INC R0
JB D7H,01H
1007H = 1004H + 3
 JB
 (PC) ← (PC) + 3
 IF (D7H) = 1 1008H = 1007H + 01H
 THEN

 (PC) ← (PC) + rel

JB bit,reladdr

INSTRUCTIONS
ADDRESS MNEMONICS

1000H MOV A,#30H

1002H ADD A,40H
1004H JB D7H,01H
1007H INC R0
1008H INC R0
JNB bit,reladdr
 Jump if Bit Not set
 If the indicated bit is a zero, branch to
the indicated address; otherwise proceed
with the next instruction.
 The bit tested is not modified.
 No flags are affected.
 Three byte instruction
 24 pulses
JNB bit,reladdr

INSTRUCTIONS
ADDRESS MNEMONICS

1000H MOV A,#30H

1002H loop: ADD A,40H
1004H JNB D7H,loop
1007H INC R0
1008H INC R0
JNB D7H,01H
1007H = 1004H + 3
 JNB
 (PC) ← (PC) + 3
 IF (D7H) = 0 1002H = 1007H +- 05H
FBH
 THEN

 (PC) ← (PC) + rel

JNB bit,reladdr
INSTRUCTIONS
ADDRESS MNEMONICS

1000H MOV A,#30H

1002H ADD A,40H
1004H JNB D7H,FBH
1007H INC R0
1008H INC R0
JBC bit,reladdr
 Jump if Bit Set and Clear Bit
 JBC will branch to the address indicated by
reladdr if the bit indicated by bit addr is set.
 Before branching to reladdr the instruction will
clear the indicated bit.
 If the bit is not set program execution continues
with the instruction following the JBC instruction.
 No flags are affected.
 Three byte instruction
 24 pulses
JBC bit,reladdr
INSTRUCTIONS
ADDRESS MNEMONICS

1000H SETB 01H

1002H JBC 01H,dow
1005H INC R0
1006H INC R1
1007H INC R2
1008H dow: INC R3
JBC 01H,03H
1005H = 1002H + 3
 JBC
 (PC) ← (PC) + 3

 IF (01H) = 1 1008H = 1005H + 03H

 THEN

 (01H) ← 0

 (PC) ← (PC) + rel

20H 1 0 0 0 0 0 1 0
BIT 07 06 05 04 03 02 01 00
Address
JBC 01H,03H
01H 01H
1 JBC = 0

20H 1 0 0 0 0 0 0 0
BIT 07 06 05 04 03 02 01 00
Address
JBC bit,reladdr
INSTRUCTIONS
ADDRESS MNEMONICS

1000H SETB 00H

1002H JBC 01H,03H
1005H INC R0
1006H INC R1
1007H INC R2
1008H INC R3
 CY AC F0 RS1 RS0 0V - P
PSW 1 0 0 0 0 0 0 0 D0H
BIT D7 D6 D5 D4 D3 D2 D1 D0
Address

21H 0 0 0 0 0 0 0 0
BIT 0F 0E 0D 0C 0B 0A 09 08
Address
Perform logical AND operation on bit
CY /0FH CY
1 AND /0 = 1
CY AC F0 RS1 RS0 0V - P
PSW 1 0 0 0 0 0 0 0 D0H
BIT D7 D6 D5 D4 D3 D2 D1 D0
Address
 CY AC F0 RS1 RS0 0V - P
PSW 1 0 0 0 0 0 0 0 D0H
BIT D7 D6 D5 D4 D3 D2 D1 D0
Address
Clear the carry flag
CY 10
CY AC F0 RS1 RS0 0V - P
PSW 0 0 0 0 0 0 0 0 D0H
BIT D7 D6 D5 D4 D3 D2 D1 D0
Address