AN INTRODUCTION TO

INTEL 8085
MICROPROCESSOR

BY:RAVINDRA NADH.V,
ASSISTANT PROFESSOR,
GST, BANGALORE.
 Basic Concepts of Microprocessors

Microcomputer –a computer with a microprocessor as

its CPU. Includes memory, I/O etc.
Microprocessor –silicon chip which includes ALU,
register circuits & control circuits
Microcontroller –silicon chip which includes
microprocessor, memory & I/O in a single package.
 Definition of the Microprocessor

The microprocessor is a programmable device

that takes in numbers, performs on them
arithmetic or logical operations according to the
program stored in memory and then produces
other numbers as a result.
 3 CYCLE INSTRUCTION EXECUTION MODEL

To execute a program, the microprocessor “reads” each

instruction from memory, “interprets” it, then “executes” it.
To use the right names for the cycles:
The microprocessor fetches each instruction,
Decodes it,
Then executes it.
This sequence is continued until all instructions are
performed.
Intel 8085
Intel 8085
Pin
Configuration
Signals and I/O Pins
 8085 ARCHITECTURE
Intel 8085 CPU Block Diagram
THE 8085 INTRODUCTION
 The 8085 is an 8-bit general purpose microprocessor that can
address 64K Byte of memory.
 It has 40 pins and uses +5V for power. It can run at a maximum
frequency of 3 MHz.
 The pins on the chip can be grouped into 6 groups:

 Address Bus.

 Data Bus.

 Control and Status Signals.

 Power supply and frequency.

 Externally Initiated Signals.

 Serial I/O ports.

The Address and Data Bus Systems
 The address bus has 8 signal lines A8 – A15 which are
unidirectional.
 The other 8 address bits are multiplexed (time shared) with the
8 data bits.
 So, the bits AD0 – AD7 are bi-directional and serve as A0 –

A7 and D0 – D7 at the same time.

 During the execution of the instruction, these lines carry

the address bits during the early part, then during the late
parts of the execution, they carry the 8 data bits.
 In order to separate the address from the data, we can use a

latch to save the value before the function of the bits

changes.
THE CONTROL AND STATUS
SIGNALS
 There are 4 main control and status signals. These are:
 ALE: Address Latch Enable. This signal is a pulse that

become 1 when the AD0 – AD7 lines have an address

on them. It becomes 0 after that. This signal can be used
to enable a latch to save the address bits from the AD
lines.
 RD: Read. Active low.

 WR: Write. Active low.

 IO/M: This signal specifies whether the operation is a

memory operation (IO/M=0) or an I/O operation

(IO/M=1).
 S1 and S0 : Status signals to specify the kind of

operation being performed. Usually not used in small

systems.
 FREQUENCY CONTROL

SIGNALS
There are 3 important pins in the frequency control group.
 X0 and X1 are the inputs from the crystal or clock generating
circuit.
 The frequency is internally divided by 2.

 So, to run the microprocessor at 3 MHz, a clock

running at 6 MHz should be connected to the X0 and
X1 pins.

 CLK (OUT): An output clock pin to drive the clock of the rest
of the system.
 THE ALU
 In addition to the arithmetic & logic circuits, the ALU
includes an accumulator, which is a part of every
arithmetic & logic operation.

 Also, the ALU includes a temporary register used for

holding data temporarily during the execution of the
operation. This temporary register is not accessible
by the programmer.
 REGISTERS
General Purpose Registers:
B, C, D, E, H & L(8 bit registers)
Can be used singly Or can be used as 16 bit register pairs
BC, DE, HL.
H & L can be used as a data pointer (holds memory
address)
Special Purpose Registers:
Accumulator(8 bit register)Store 8 bit data
Store the result of an operation
Store 8 bit data during I/O transfer
 CONT…….
The Program Counter (PC):This is a register that is used
to control the sequencing of the execution of instructions.
This register always holds the address of the next
instruction.
Since it holds an address, it must be 16 bits wide.
The Stack pointer: The stack pointer is also a 16-bit
register that is used to point into memory.
The memory this register points to is a special area
called the stack.
The stack is an area of memory used to hold data
that will be retreived soon.
The stack is usually accessed in a Last In First Out
(LIFO) fashion.
THE FLAGS REGISTER
 There is also a flag register whose bits are affected by the arithmetic & logic
operations.
 S-sign flag

 The sign flag is set if bit D7 of the accumulator is set after an

arithmetic or logic operation.
 Z-zero flag

 Set if the result of the ALU operation is 0. Otherwise is reset. This

flag is affected by operations on the accumulator as well as other
registers.
 AC-Auxiliary Carry

 This flag is set when a carry is generated from bit D3 and passed to
D4 . This flag is used only internally for BCD operations.
 P-Parity flag

 After an ALU operation, if the result has an even number of 1’s, the
p-flag is set. Otherwise it is cleared. So, the flag can be used to
indicate even parity.
 CY-carry flag

 This flag is set when a carry is generated from bit D7 after an

unsigned operation.
 NON PROGRAMMABLE REGISTERS

Instruction Register: Instruction is stored in IR after

fetched by processor

Decoder decodes instruction in IR

Internal Clock generator

 3.125 MHz internally
 6.25 MHz externally
CONTROL SIGNALS
 INTERRUPT SIGNALS
 An interrupt is a hardware-initiated subroutine CALL.
 When interrupt pin is activated, an ISR will be called,
interrupting the program that is currently executing.
 INTR input is enabled when EI instruction is executed.
 The status of the RST 7.5, RST 6.5 and RST 5.5 pins are
determined by both EI instruction and the condition of the
mask bits in the interrupt mask register.
Cont….

20
 ADDRESSING MODES
For 8085, there are 4 types of addressing modes. They are:
Immediate addressing:
Data is present in the instruction.
Load the immediate data to the destination provided.
Example: MVI R, data
Register addressing:
Data is provided through the registers.
Example: MOV Rd, Rs
Direct addressing :
Used to accept data from outside devices to store in the
accumulator or send the data stored in the accumulator to
the outside device.
Example: IN 00H or OUT 01H
 CONT……
 Indirect addressing:
This means that the Effective Address is calculated by

the processor.
And the contents of the address (and the one following)

is used to form a second address.

The second address is where the data is stored.

Note that this requires several memory accesses; two

accesses to retrieve the 16-bit address and a further

access (or accesses) to retrieve the data which is to be
loaded into the register.
 Example: LDAX B
 INSTRUCTION SET
 An Instruction is a command given to the computer to perform a
specified operation on given data.
 The instruction set of a microprocessor is the collection of the
instructions that the microprocessor is designed to execute.
 These instructions have been classified into the following
groups:
 Data Transfer Group

 Arithmetic Group

 Logical Group

 Branch Control Group

 I/O and Machine Control Group

 DATA TRANSFER INSTRUCTIONS
INSTRUCTION EXPLANATION OPERATION
MOV r1, r2 Move the content of the [r1] <-- [r2]
one register to another
MOV r, M Move the content of r <-- [M]
memory register
MOV M, r Move the content of M <-- [r]
register to memory
MVI r, data Move immediate data to [r] <-- data
register
MVI M, data Move immediate data to M <-- data
memory
LXI rp, data Load register pair [rp] <-- data 16 bits, [rh]
immediate <-- 8 LSBs of data
LDA addr Load Accumulator direct [A] <-- [addr]
 Cont…
INSTRUCTION EXPLANATION OPERATION

STA addr. Store accumulator direct [addr] <-- [A]

LHLD addr Load H-L pair direct [L] <-- [addr], [H] <-- [addr+1].

SHLD addr Store H-L pair direct [addr] <-- [L], [addr+1] <-- [H].

LDAX rp LOAD accumulator indirect. rp [A] <-- [[rp]]

point to a memory location.
STAX rp Store accumulator indirect. rp [[rp]] <-- [A].
point to a memory location.
XCHG Exchange the contents of H-L [H-L] <--> [D-E].
with D-E pair
 ARITHMETIC INSTRUCTIONS
INSTRUCTION EXPLANATION OPERATION
ADD r Add register to [A] <-- [A] + [r].
accumulator)
ADD M Add memory to [A] <-- [A] + [[H-L]].
accumulator
ADC r Add register with carry to [A] <-- [A] + [r] + [CS].
accumulator
ADC M Add memory with carry to [A] <-- [A] + [[H-L]]
accumulator [CS].
ADI data Add immediate data to [A] <-- [A] + data
accumulator
ACI data Add with carry immediate [A] <-- [A] + data + [CS].
data to accumulator
 Cont….
INSTRUCTION EXPLANATION OPERATION
DAD rp Add register paid to H-L pair [H-L] <-- [H-L] + [rp].

SUB r Subtract register from [A] <-- [A] – [r].

accumulator
SUB M Subtract memory from [A] <-- [A] – [[H-L]].
accumulator
SBB r Subtract register from [A] <-- [A] – [r] – [CS].
accumulator with borrow
SBB M Subtract memory from [A] <-- [A] – [[H-L]] – [CS].
accumulator with borrow
SUI data Subtract immediate data [A] <-- [A] – data.
from accumulator
 Cont…
INSTRUCTION EXPLANATION OPERATION

SBI data Subtract immediate data [A] <-- [A] – data – [CS].
from accumulator with
borrow

INR r Increment register content [r] <-- [r] +1

INR M Increment memory content [[H-L]] <-- [[H-L]] + 1

DCR r Decrement register content [r] <-- [r] – 1

DCR M Decrement memory content [[H-L]] <-- [[H-L]] – 1

INX rp Increment register pair [rp] <-- [rp]+1

DCX rp Decrement register pair [rp] <-- [rp] -1.

 LOGICAL INSTRUCTIONS
INSTRUCTION EXPLANATION OPERATION
ANA r AND register with [A] <-- [A] ^ [r]
accumulator
ANA M AND memory with [A] <-- [A] ^ [[H-L]]
accumulator
ANI data AND immediate data with [A] <-- [A] ^ data
accumulator
ORA r OR register with [A] <-- [A] v [r]
accumulator
ORA M OR memory with [A] <-- [A] v [[H-L]]
accumulator
ORI data OR immediate data with [A] <-- [A] v data.
accumulator
 Cont…
INSTRUCTION EXPLANATION OPERATION
XRA r EXCLUSIVE – OR [A] <-- [A] v [r]
register with accumulator
XRA M EXCLUSIVE-OR memory [A] <-- [A] v [[H-L]]
with accumulator
XRI data EXCLUSIVE-OR [A] <-- [A] v data
immediate data with
accumulator
CMA Complement the [A] <-- [A] ”
accumulator
CMC Complement the carry [CS] <-- [CS]”
status
STC Set carry status [CS] <-- 1
 Cont…
INSTRUCTION EXPLANATION OPERATION
CMP r Compare register with accumulator [A] – [r]
CMP M Compare memory with [A] – [[H-L]]
accumulator)
CPI data Compare immediate data with [A] – data
accumulator
RLC Rotate accumulator left [An+1] <-- [An],
[A0] <-- [A7],[CS] <-- [A7].
RRC Rotate accumulator right [A7] <-- [A0], [CS] <-- [A0],
[An] <-- [An+1].
RAL Rotate accumulator left through [An+1] <-- [An],
carry [CS] <-- [A7], [A0] <-- [CS].
RAR Rotate accumulator right through [An] <-- [An+1],
carry [CS] <-- [A0], [A7] <-- [CS]
 BRANCH INSTRUCTIONS
INSTRUCTION EXPLANATION OPERATION
JMP addr (label) Unconditional jump: jump [PC] <-- Label
to the instruction specified
by the address
JZ addr (label) Jump if the result is zero [PC] <-- Label
JNZ addr (label) Jump if the result is not [PC] <-- Label
zero
JC addr (label) Jump if there is a carry [PC] <-- Label
JNC addr (label) Jump if there is no carry [PC] <-- Label
JP addr (label) Jump if the result is plus [PC] <-- Label
JM addr (label) Jump if the result is minus [PC] <-- Label
JPE addr (label) Jump if even parity [PC] <-- Label
JPO addr (label) Jump if odd parity [PC] <-- Label
 Cont…
INSTRUCTION EXPLANATION OPERATION

CALL addr (label) call the subroutine [PC] <-- Label

identified by the operand

RET Return from subroutine

RST n The program jumps to the

instruction starting at
restart location
 STACK, I/O AND MACHINE
INSTRUCTIONS
INSTRUCTION EXPLANATION OPERATION
IN port-address Input to accumulator from [A] <-- [Port]
I/O port
OUT port-address Output from accumulator to [Port] <-- [A]
I/O port
PUSH rp Push the content of register
pair to stack
PUSH PSW PUSH Processor Status
Word (Accumulator+ temp
register)
POP rp Pop the content of register
pair, which was saved, from
the stack
POP PSW Pop Processor Status Word
Cont…
INSTRUCTION EXPLANATION
HLT Halt
XTHL Exchange stack-top with H-L

SPHL Move the contents of H-L pair

to stack pointer
EI Enable Interrupts
DI Disable Interrupts
SIM Set Interrupt Masks
RIM Read Interrupt Masks

NOP No Operation