Analog and Digital VLSI Design: Lecture 6: Manufacturing Process

Download as pptx, pdf, or txt
Download as pptx, pdf, or txt
You are on page 1of 37

Analog and Digital VLSI Design

EEE F313/INSTR F313

Lecture 6: Manufacturing Process


Simplified CMOS Process Flow

N-Substrate P-well
P-well Process
N-well Process ? Dual Well Process ?
Layout

p well Cross Section

Layout
Layouts
Layout of an inverter
Layouts
Stick Diagram
Polysilicon
P diffusion
n diffusion
Metal 1
Metal Via
Layouts
Stick Diagram
Polysilicon
P diffusion
n diffusion
Metal 1
Metal Via
Photolithography
optical
oxidation mask

stepper
exposure
photoresist photoresist coating
removal (ashing)

photoresist
development

process
step

spin, rinse, acid etch


dry
P- Well Mask
Light Exposure
Photoresist Development
Acid Etching
Photo Resist Removal
Ion implantation and diffusion
Active Mask
Thin oxide layer
Poly silicon layer deposition
Transistor Formation
N+ select mask
P+ select mask
Contact mask
Metal mask
CMOS inverter

Via

p well

Layout
CMOS inverter

P Diffusion Region N Diffusion Region

p well

Layout

You might also like