By Shilpa Chaman 1

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 Fetching the next instruction while current
instruction is under execution is called
pipelining.
What happens to queue when jump or call

instruction is executed ?

When 8086 is reset the contents of IP are

0000 H and contents of CS are FFFF H.
Other registers are cleared to 0000 h.

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 Allow the memory capacity to be 1Mb even
though the addresses associated with the
individual instructions are only 16 bits wide.
Facilitate the use of separate memory areas for
the program, its data and the stack.
Permit a program and/or its data to be put into
different areas of memory each time the
program is executed.
Multitasking becomes easy.

By Shilpa Chaman 16
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 Control Flag:- Out of nine active flags, six are conditional
flags and the remaining three are called as the control
flag.The three control flags are:
1. The Trap flag(TF)
2. The interrupt flag(IF)
3. The direction flag(DF)

By Shilpa Chaman 19
By Shilpa Chaman 20
 A] Data Category B] Branch Category

A] Data Category
1) Immediate Addressing
2) Direct Addressing

( Segment Override prefix)

3) Register Addressing
4) Register Indirect Addressing

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 5) Register Relative addressing
6) Base Index addressing
7) Relative Base Index addressing
8) Implied /Implicit Addressing

B] Branch Category :
1) Intrasegment Direct
2) Intersegment Indirect
3) Intrasegment Direct
4) Intersegment Indirect

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 In this mode, 8 or 16 bit data can be specified as part of the
instruction.
OP Code
Immediate Operand
Example 1:
MOV CL, 03 H
Moves the 8 bit data 03 H into CL

Example 2:
MOV DX, 0525 H
Moves the 16 bit data 0525 H into DX
In the above two examples, the source operand is in immediate
mode and the destination operand is in register mode

By Shilpa Chaman 23
 The operand to be accessed is specified as residing in an internal
register of 8086. However only the data registers can be accessed
as either a byte or word

Example 1:
MOV DX (Destination Register) , CX (Source Register)
Which moves 16 bit content of CS into DX.

Example 2:
MOV CL, DL
Moves 8 bit contents of DL into CL

MOV BX, CH is an illegal instruction.The register sizes must be the

same.

By Shilpa Chaman 24
 The instruction Opcode is followed by an affective address, this
effective address is directly used as the 16 bit offset of the
storage location of the operand from the location specified by the
current value in the selected segment register.he default segment
is always DS. The 20 bit physical address of the operand in
memory is normally obtained as
PA = DS : EA

Example 1 :
MOV CX, [0040]
If the 16 bit value assigned to the offset is 0040 and [DS] = 3050.
Then BIU generates the 20 bit physical address 30540 H.The
content of 30540 is moved to CL.The content of 30541 is moved to
CH

Example 2 :
MOV CH, [0040]
If [DS] = 3050 and 0040 is offset then 8 bit content of memory
location 30540 is moved to CH.

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 Instruction

Opcode Address A
Memory

Operand
 The EA is specified in either pointer (BX) register or
an index (SI or DI) register. The 20 bit physical
address is computed using DS and ES.

Example : MOV [DI], BX

If [DS] = 5004, [DI] = 0020, [Bx] = 2456 PA=50060.
The content of BX(2456) is moved to memory
locations 50060 H and 50061 H.

By Shilpa Chaman 27
 Instruction

Opcode Register Address R

Memory

Registers

Pointer to Operand Operand

 When memory is accessed PA is computed
from BX and DS and when the stack is
accessed PA is computed from BP and SS.

Example : MOV AL, [BX]

EA : [BX]
PA : [DS] + [EA]
The 8 bit content of this memory location

is moved to AL.

By Shilpa Chaman 29
 Instruction

Opcode [Register (BP or BX)]

Memory

Registers

Pointer to Operand Operand

 When memory is accessed PA is computed
from BX and DS and when the stack is
accessed PA is computed from BP and SS.

Example : MOV AL, 50h[BX]

or
MOV AL, [50h + BX]
EA : [50h] + [BX]
PA : [DS] + [EA]
The 8 bit content of this memory location is
moved to AL.

By Shilpa Chaman 31
 Instruction

Opcode [Register R(BX or BP )] Relative Address

Memory

Registers

Pointer to Operand + Operand

 When memory is accessed PA is
computed from SI and DS or from DI
and ES
Example : MOV BH, [SI]
PA : [SI] + [DS]
The content of this memory is moved into

BH.

By Shilpa Chaman 33
 Instruction

Opcode [Register (SI or DI)]

Memory

Registers

Pointer to Operand Operand

 When memory is accessed PA is
computed from SI and DS or from DI
and ES
Example : MOV BH, 50h [SI]
PA : 50h+ [SI] + [DS]
The content of this memory is moved into

BH.

By Shilpa Chaman 35
 Instruction

Opcode [Register (SI or DI )] Relative Address

Memory

Registers

Pointer to Operand + Operand

 Example : MOV 08h [SI] [BX], CL
If [BX] = 0200, [SI] = 1000 H and [DS] =

3000
Physical address (PA) = 31208
8 bit content of CL is moved to 31208

memory address.

By Shilpa Chaman 37
 In this mode operands are implied and hence are not specified in
the instruction.
This instruction is very compact
Example 1:
STC : Set Carry Flag
Example 2:
CLD : Clear Direction Flag

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 Low / Even
High / Odd
Bank
Bank

8086 Bank select signals

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8086 Minimum-Mode
Signals
Power supply

Vcc
GND

INTR Address / data

bus AD0-AD15,
____ A16/S3-
_ A19/S6
INTA
Interru
pt ____
interfac _ ALE
e TES ____
T BHE/S7
8086
MPU M/IO
NMI
Memory/
DT/R
IO
___
RES controls
RD
DMA ET ___
interfa WR
ce ____
HOL DEN
D
Mode
READY
Select HLD
MN/MX A

CLK
 Address/Data bus: 20 bits vs 8 bits
multiplexed
Status signals: A16-A19 multiplexed with
status signals S3-S6 respectively
S3 and S4 together form a 2 bit binary
code that identifies which of the internal
segment registers was used to generate the
physical address that was output on the
address bus during the current bus cycle.
S5 is the logic level of the internal
interrupt enable flag, s6 is always logic 0.
 BUS CYCLE AND TIME STATES

A Machine cycle defines the basic operation that a microprocessor performs to

communicate with external devices.
Examples of Machine cycle are opcode fetch, memory read, memory write,
input/output read and input/output write.
A Machine cycle corresponds to a sequence of events that starts with an address
being output on the system bus followed by a read or write data transfer.
During these operations, a series of control signal are also produced by the
MPU to control the direction and timing of the bus.
Each Machine cycle consists of at least four clock periods, T1, T2, T3 and T4.
These clock period are also called T-state.
These 4 clock states gives a Machine cycle duration of ( 125 ns * 4 ) = 500 ns in a
8-Mhz 8088
Idle State: no bus activity ; one clock period
Wait state : controlled by READY signal ; inserted between T3 and T4 when
READY = 0 . Bus cycle will complete when READY = 1
 System Timing Diagrams
T-State:
One clock period is referred to as a T-State

T-State
An operation takes an integer number of T-States

CPU Bus Cycle or Machine Cycle:

A bus cycle consists of 4 or more T-States

T1 T2 T3 T4
 Wait and Idle States
Idle State
No bus activity required
Each is 1 clock period long
Occurs when instruction queue is full or
the MPU does not need to read/write to
memory
Wait State
Triggered by events external to MPU
Buffer full will trigger a wait state
Triggered by READY pin
Inserted between T3 and T4
 TIMING DIAGRAM OF 8086
Timer States

T1
Address placed on bus
ALE active
T2
Change direction of Data bus for READ instructions
T3-4
Data transfer occurs
T1 - start of bus cycle. Actions include setting control signals to give the
required values for ALE, DTR, IO/M putting a valid address onto the
address bus.

T2 - the RD or WR control signals are issued, DEN is asserted

and in the case of a write, data is put onto the data bus. The
DEN turns on the data bus buffers to connect the CPU to the
external data bus. The READY input to the CPU is sampled at
the end of T2 and if READY is low, a wait state TW (one or
more) is inserted before T3 begins.

T3 - this clock period is provided to allow memory to access the data. If

the bus cycle is a read cycle, the data bus is sampled at the end of
T3.

T4 - all bus signals are deactivated in preparation for the next

clock cycle. The 8088 also finishes sampling the data (in a
read
cycle) in this period. For the write cycle, the trailing edge of
the
WR signal transfers data to the memory or I/O, which
activates
and write when WR returns to logic 1 level.
 T1 T2 T3 TW T4

CLK

M/IO

ALE
MEMORY ACCESS TIME
ADDR/ RESERVED VALID
A15-A0
DATA FOR DATA D15-D0

ADDR/ A19-A16
STATUS
RD/INTA
READY
DT/R
DEN
 T1 T2 T3 TW T4

CLK

M/IO

ALE

ADDR/
A15-A0 DATA OUT (D15-D0)
DATA
ADDR/ A19-A16
STATUS
WR
READY
DT/R
DEN
Write Cycle Timing Diagram for Minimum Mode

T1 T2 T3 TW T4 T1

ALE

BHE S7 S3
ADD / STATUS A19 A16

ADD / DATA A15 A0 Valid data 15

D D0

WR

DEN

DT / R
What is the duration of the bus cycle in the 8088
based microcomputer if the clock is 8MHz and two
wait states are inserted

The duration of the bus cycle is in an 8MHz system is

given in general by
Tcyc = 500 ns + N x 125ns
Tcyc = 500 ns +2 x 125ns
= 750 ns
 System Clock
Generator-8284
 CLOCK GENERATOR IC

The clock source is generated by 8284 ( clock generator and Driver IC )

CLK ( 8) of 8284 is connected to pin 19 8086
8284 also supplies it with 2 of it's control lines RESET and READY. The
RESET signal does resets the 8086. This line can also be used by other
peripherals on the computer so that they reset when the 8086 resets.
READY used to slow down the 8086 ;
A crystal oscillator is connected between X1 and X2 which provides a
FUNDAMENTAL CRYSTAL FREQUENCY. ( FCF)
33% duty cycle the FCF is divided by 3 internally by 8244 to provide the
necessary CLK
output pin pclk provide 50% of duty cycle to drive periperal devices

http://en.wikipedia.org/wiki/Crystal_oscillator
BASIC 8086 MINIMUM MODE SYSTEM

MN/MX
CLK
8284A M/IO
CLOCK READY
INTA
GENERATO RESET
RD
R
WR 8282
DT/R LATCH
DEN
ALE ADDR
WAIT STATE
GENERATOR AD0-
AD15
A16-A19

8286
TRAN-
ADDR/DATA CEIVER
DATA

RAM 2142 PERI-

2716
PHERAL
PROM
8086 Minimum-Mode
Bus Controller - 8288
Continued
 For multiprocessor environment
8288 Bus Controller is used for bus control
WR,IO/M,DT/R,DEN,ALE, INTA signals
are not available
Instead:
MRDC (memory read command)
MWRT (memory write command)
AMWC (advanced memory write command)
IORC (I/O read command)
IOWC (I/O write command)
AIOWC (Advanced I/O write command)
INTA (interrupt acknowledge)
 They indicate the function of the current
bus cycle. They are normally decoded by
the 8288 bus controller
 The signals shown above are produced by 8288
depending on the state of S0, S1 and S2.
DEN, DT/R and ALE signals are the same as
minimum-mode systems
LOCK: when =0, prevents other processors
from using the bus
QS0 and QS1 (queue status signals) : informs
about the status of the queue
RQ/GT 0 and RQ/GT 1 are used instead of
HOLD and HLDA lines in a multiprocessor
environment as request/grant lines.
Here MRDC* signal is
used instead of RD* as
in case of Minimum
Mode S0* to S2* are
active and are used to
generate control signal.
 Maximum Mode Interface

When the 8086 is set for the maximum-mode

configuration, it provides signals for implementing a
multiprocessor / coprocessor system environment.

By multiprocessor environment we mean that one

microprocessor exists in the system and that each
processor is executing its own program.

Usually in this type of system environment, there

are some system resources that are common to all
processors. They are called as global resources.
There are also other resources that are assigned to
specific processors. These are known as local or
private resources.
 Memory Read Timing in Maximum
mode.
One bus cycle
T1 T2 T3 T4 T1
Clk

ALE

S2 S 0 Active Inactive Active

Add/Status BHE, A19 A16 S7 S3

Add/Data A15 A0 D15 D0

MRDC

DT / R

DEN
 Memory Write Timing in
Maximum mode.

One bus cycle

T1 T2 T3 T4 T1

Clk

ALE

S2 S0 Active Inactive Active

ADD/STATUS BHE S7 S3

ADD/DATA A15-A0 Data out15D D0

AMWC or
AIOWC
MWTC or IOWC

DT / R high
DEN
 Classified into 7 categories:
1] Data Transfer
2] Arithmetic
3] Logical
4] Control
5]Processor Control Instructions
6] String Manipulation
7] Interrupt Control

By Shilpa Chaman 92
 Note : Data Transfer Instructions do not affect any flags
1] MOV dest, src
Note that source and destination cannot be memory
location. Also source and destination must be same
type.
2] PUSH Src: Copies word on stack.
3] POP dest: Copies word from stack into dest.
Reg.
4] IN acc, port : Copies 8 or 16 bit data from port
to accumulator.
a) Fixed Port
b) Variable Port
5] OUT port, acc

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 6] LES Reg, Mem: Load register and extra
segment
register with words from memory.
7] LDS Reg,Mem: Load register and data
segment
register with words from memory.
8] LEA Reg,Src: load Effective address.
(Offset is loaded in specified register)
9] LAHF: Copy lower byte of flag register into AH
register.
10] SAHF: Copy AH register to lower byte of flag

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 11] XCHG dest, src: Exchange contents of
source and destination.
12] XLAT: Translate a byte in AL.

This instruction replaces the byte in AL with

byte pointed by BX.To point desired byte in
look up table instruction adds contains of
BX with AL ( BX+ AL). Goes to this location
and loads into AL.

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 1]ADD dest,src
2] ADC dest,src: Add with carry
3] AAA : ASCII adjust after addition.

We can add two ASCII numbers directly and

use AAA after addition so as to get result
directly in BCD. (Works with AL only)
4] DAA : Decimal adjust accumulator.

( Works with AL only)

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 5] SUB dest, src

6] SBB dest, src: Subtract with borrow.

7] AAS: ASCII adjust for subtraction

( same as AAA and works with AL only)

8] DAS : Decimal adjust after Subtraction.

( works with AL only)

9] MUL src

10 ] IMUL src: Multiplication of signed byte.

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 11] AAM: BCD adjust after multiply.
(works with AL only)
12]DIV src

If any one attempts to divide by 0 , then ?

13] IDIV: Division of signed numbers
14]AAD: BCD to Binary convert before

Division.
15] DEC dest

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 16] INC dest
17] CWD: Convert signed word to

signed double word.

18] CBW : Convert signed byte to

signed word.
(CBW and CWD works only with AL, AX and
DX)
19] NEG dest: Forms 2s complement.

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 1] AND dest, src
2] NOT dest: Invert each bit in destination
3] OR dest, src
4] XOR dest, src
5] RCL dest, count : Rotate left through Carry
Rotate as many times as directly specified in the
instruction. For more no.of rotations, count can be
specified in CL register.

6] RCR dest, count : Rotate right through carry

7] ROL dest, count : Rotate left ( into carry as well
as into LSB)
8] ROR dest, Count : Rotate left ( into carry as well
as into MSB)

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 9] SAL/ SHL dest, count : Shift left and
append 0s on right.
10] SAR dest, count : Shift right retain a

copy of the S-bit and shift all bits to right.

11]SHR dest, count : Shift right append

0s on left
12] TEST dest, src: AND logically,

updates flags but source and dest are

unchanged.

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 13] CMP dest, src
CF, ZF and SF are used

Ex. CMP CX,BX

CF ZF SF
CX = BX 0 1 0
CX> BX 0 0 0
CX<BX 1 0 1

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 1]CALL : Call a procedure
Two types of calls:
i) Near Call ( Intrasegment)
ii) Far Call ( Intersegment)
2] RET : Return execution from

procedure
3] JMP : Unconditional Jump to specified

destination. Two types near and Far

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 4] JA / JNBE: Jump if above / Jump if not
below
The terms above and below are used when
we refer to the magnitude of Unsigned
number .
Used normally after CMP.
5] JAE / JNB / JNC
6] JB / JC / JNAE
7] JBE / JNA
8] JE/ JZ
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 9] JCXZ: Jump if CX is Zero.
10] JG / JNLE: Jump if Greater /Jump if

NOT less than or equal.

The term greater than or less than is used
in connection with two signed numbers.
11] JGE / JNL:
12] JL / JNGE :
13] JLE / JNG :
14]JNE / JNZ :

By Shilpa Chaman 10
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 15] JNO : Jump if no overflow
16] JNS : Jump if no sign
17] JS
18] JO
19] JNP / JPO
20] JP / JPE

In all above conditional instructions the

destination of jump is in the range of -128
to + 127 bytes from the address after jump.
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 21] LOOP: Loop to the specified label if CX
is not equal to Zero.
The count is loaded in CX reg. Every time LOOP
is executed, CX is automatically decremented -
used in delay programs

22] LOOPE/ LOOPZ: Loop while CX is not

equal to zero and ZF = 1.

23] LOOPNE / LOOPNZ: Loop while CX not

equal to zero and ZF = 0.
In all above LOOP instructions the destination of
jump is in the range of -128 to + 127 bytes
from the address after LOOP.
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 1] CLC: Clear Carry flag.
2] STC :Set carry Flag
3] CMC :Complement Carry Flag
4] CLD: Clear Direction Flag.
5] STD: Set Direction Flag
6] CLI :Clear Interrupt Flag.
7] STI : Set Interrupt Flag.
8] HLT: Halt Processing.

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 9] NOP : No Operation
10] ESC: Escape
Executed by Co-processors and actions are
performed according to 6 bit coding in the
instruction.
11] LOCK : Assert bus lock Signal
This is a prefix instruction.
12] WAIT :Wait for test or Interrupt
Signal.
Assert wait states.
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 1] MOVS/ MOVSB/ MOVSW
Dest string name,src string name
This instn moves data byte or word from
location in DS to location in ES.

2] REP / REPE / REPZ / REPNE / REPNZ

Repeat string instructions until specified
conditions exist.
This is prefix a instruction.

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 3] CMPS / CMPSB / CMPSW
Compare string bytes or string words.

4] SCAS / SCASB / SCASW

Scan a string byte or string word.
Compares byte in AL or word in AX. String address is to be loaded
in DI.

5] STOS / STOSB / STOSW

Store byte or word in a string.
Copies a byte or word in AL or AX to memory location pointed by
DI.

6] LODS / LODSB /LODSW

Load a byte or word in AL or AX

Copies byte or word from memory location pointed by SI into AL or

AX register.

By Shilpa Chaman 11
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 1]INT type

2] INTO Interrupt on overflow

3] IRET Interrupt return

By Shilpa Chaman 11
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end label end of program, label is entry point
proc far|near begin a procedure; far, near keywords
specify if procedure in different code
segment (far), or same code segment (near)
endp end of procedure
page set a page format for the listing file
title title of the listing file
.code mark start of code segment
.data mark start of data segment
.stack set size of stack segment
db define byte
dw define word (2 bytes)
dd define double word (4 bytes)
dq define quadword (8 bytes)
dt define tenbytes
equ equate, assign numeric expression to a name
Examples:
db 100 dup (?) define 100 bytes, with no initial values for bytes
db Hello define 5 bytes, ASCII equivalent of Hello.
maxint equ 32767
count equ 10 * 20 ; calculate a value (200)
 1] ASSUME
Used to tell assembler the name of logical
segment. Ex. ASSUME CS: Code here
2] END
3] DB
4] DW
5] DD Define Double Word
6] DQ Define Quad Word
7] DT Define Ten Bytes

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 8] PROC Procedure
PROC DELAY NEAR
9] ENDP
10] ENDS
11] EQU
12] EVEN: Align on even memory address.
13] ORG
14] OFFSET
Ex: MOV BX, Offset of Data Here
15] PTR Pointer

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 16] LABEL
Ex: AGAIN LABEL FAR
17] EXTRN
Tells the assembler that the names or labels
following this directive is in some other
assembly module.
18] PUBLIC

Links modules together

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 19] INCLUDE
Include source code from file.

20] NAME
To give specific name to module.

21] GROUP
Grouping of logical segments.

22] SEGMENT

23] SHORT
Operator that tells assembler about short displacement.

24] TYPE
Type of variable whether byte or word.

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 mov cx,2000
mov ds,cx

mov ax,[0500h]
mov cx,3000

mov ds,cx
mov bx,[0600h]

add ax,bx
mov cx,5000

mov ds,cx
mov [0700h],ax

hlt

By Shilpa Chaman 11
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 MOV AX,WORD1 LB
MOV BX,WORD1 UB
MOV CX,WORD2 LB
MOV DX,WORD2 UB
ADD AX,CX
ADC BX,DX
MOV [0300],AX
MOV [0302],BX

By Shilpa Chaman 12
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 Mov ax,7000h
Mov ds,ax
Mov si, 0200h
Mov di, 0300h
Mov cx,0009h

Back: mov al,[si] // cld

mov [di],al // rep movsb
inc si // HLT
inc di
dec cx
jnz back
HLT

By Shilpa Chaman 12
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 .model small
.stack 10h
extra segment
Array_cpy db
extra ends
data segment
Array db 11h,22h,33h,44h,55h,66h,77h,88h,99h;
data ends
code segment
assume cs:code, es:extra,ds:data
start: mov ax,data
mov ds,ax
mov es,ax
mov si, offset Array
mov di, offset Array_cpy
mov cx,09h
cld
Rep movsb
int 21h
code ends
end start By Shilpa Chaman 12
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;Title : To find the largest Number in an array
.model small
.stack 10h
data segment
array db 5h,7h,6h,4h,10h,09h,03h,01h,02h,0h
largest db
data ends
code segment
Assume cs:code,ds:data
start: mov ax,data
mov ds,ax
xor ax,ax
mov cx,oah
mov si, offset array
Initial : inc si
cmp al,[si]
jnc Conti
mov al,[si]
Conti : loop Initial
mov largest,al
int 21h
code ends
end start
By Shilpa Chaman 12
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 Traverse a collection of elements
Move from the front to the end
Bubble the largest value to the end using
pair-wise comparisons and swapping

1 2 3 4 5 6

77 42 35 12 101 5
 Traverse a collection of elements
Move from the front to the end
Bubble the largest value to the end using
pair-wise comparisons and swapping

1 2 3 4 5 6

42 Swap4277
77 35 12 101 5
 Traverse a collection of elements
Move from the front to the end
Bubble the largest value to the end using
pair-wise comparisons and swapping

1 2 3 4 5 6

42 7735 Swap 35
77 12 101 5
 Traverse a collection of elements
Move from the front to the end
Bubble the largest value to the end using
pair-wise comparisons and swapping

1 2 3 4 5 6

42 35 12 Swap 12
77 77 101 5
 Traverse a collection of elements
Move from the front to the end
Bubble the largest value to the end using
pair-wise comparisons and swapping

1 2 3 4 5 6

42 35 12 77 101 5

No need to swap
 Traverse a collection of elements
Move from the front to the end
Bubble the largest value to the end using
pair-wise comparisons and swapping

1 2 3 4 5 6

42 35 12 77 1015 Swap 101

5
 If we have N elements

And if each time we bubble an

element, we place it in its
correct location

Then we repeat the bubble up

process N 1 times.

This guarantees well correctly

place all N elements.
 1 2 3 4 5 6
42 35 12 77 5 101

1 2 3 4 5 6
35 12 42 5 77 101

1 2 3 4 5 6
N-1

12 35 5 42 77 101

1 2 3 4 5 6
12 5 35 42 77 101

1 2 3 4 5 6
5 12 35 42 77 101
;Title Bubble sort(ascending)
.model small
.stack 10h
data segment
array db 5h,7h,6h,4h,10h,09h,03h,01h,02h,0h
data ends
code segment
Assume cs:code,ds:data
start: mov ax,data Swap : xchg al,[si+1]
mov ds,ax xchg al,[si]
xor ax,ax jmp Conti
mov dx,09h
Return: mov cx,dx exit : int 21h
mov si,offset array code ends
Check: mov al,[si] end start
cmp al,[si+1]
Jnc Swap
Conti : inc si
loop Check
dec dx
jnz Return
jmp exit

By Shilpa Chaman 13
2
;Title Bubble sort(descending)
.model small
.stack 10h
data segment
array db 5h,7h,6h,4h,10h,09h,03h,01h,02h,0h
data ends
code segment
Assume cs:code,ds:data
start: mov ax,data Swap : xchg al,[si+1]
mov ds,ax xchg al,[si]
xor ax,ax jmp Conti
mov dx,09h
Return: mov cx,dx exit : int 21h
mov si,offset array code ends
Check: mov al,[si] end start
cmp al,[si+1]
Jc Swap
Conti : inc si
loop Check
dec dx
jnz Return
jmp exit

By Shilpa Chaman 13
3