Chapter 10

Semiconductor Memories

 Chapter Overview: Types of memories

ROM circuits
SRAM circuits
DRAM circuits

 Classification based on storage and

access:-

 Read Only Memory Circuits: The read-only memory array can also be seen as a
simple combinational Boolean network which produces
a specified output value for each input combination i.e.,
for each address.
Thus, storing binary information at a particular address
location can be achieved by the presence or absence of
a data path from the selected row (word line) to the
selected column (bit line), which is equivalent to the
presence or absence of a device at that particular
location.

 Consider first the 4-bit x4-bit memory array shown in

Fig. Here,
each column consists of a pseudo-nMOS NOR gate
driven by some of the row signals,
i.e., the word lines.

 only one word line is activated (selected) at a time by

raising its voltage to VDD, while all other rows are held
at a low voltage level. If an active transistor exists at
the cross point of a column and the selected row, the
column voltage is pulled down to the logic low level by
that transistor.
If no active transistor exists at the cross point, the
column voltage is pulled high by the pMOS load device.
Thus, a logic " 1 "-bit is stored as the absence of an
active transistor, while a logic 0"-bit is stored as the
presence of an active transistor at the cross point.

 Layout of NOR ROM: Figure shows four nMOS transistors in a NOR ROM array,
forming the intersection of two metal bit lines and two polysilicon word lines.
To save silicon area, the transistors in every two adjacent
rows are arranged to share a common ground line, also
routed in n-type diffusion.
To store a 0-bit at a particular address location, the drain
diffusion of the corresponding transistor must be connected
to the metal bit line via a metal-to-diffusion contact.
Omission of this contact, on the other hand, results in a
stored "1 "-bit.

 4-bit x 4-bit NOR ROM Circuit and Layout:-

 Alternative layout based on implant

masking:-

 Note that in this case, each threshold voltage implant

signifies a stored "1"-bit, and all other (nonimplanted)transistors correspond to stored "0"-bits.
Since each diffusion-to-metal contact in this structure is
shared by two adjacent transistors, the implant-mask ROM
layout can yield a higher core density, i.e., a smaller silicon
area per stored bit, compared to the contact mask

 Next, we will examine a significantly different ROM

array design, which is also called a NAND ROM .
Here, each bit line consists of a depletion-load
NAND gate, driven by some of the row signals, i.e.,
the word lines.
In normal operation, all word lines are held at the
logic-high voltage level except for the selected line,
which is pulled down to logic-low level.
If a transistor exists at the cross point of a column
and the selected row, that transistor is turned off
and the column voltage is pulled high by the load
device.
On the other hand, if no transistor exists (shorted) at
that particular cross point, the column voltage is

 A 4-bit x 4-bit NAND-based ROM

array:-

 Implant-mask layout of the NAND ROM

array:-

 Vertical columns of n-type diffusion intersect at

regular intervals with horizontal rows of poly-silicon,
which results in an nMOS transistor at each
intersection point.
The transistors with threshold voltage implants
operate as normally-on depletion devices, thereby
providing a continuous current path regardless of the
gate voltage level.
Since this structure has no contacts embedded in the
array, it is much more compact than the NOR ROM
array. However, the access time is usually slower
than the NOR ROM, due to multiple series-connected
nMOS transistors in each column.

 Design of Row and Column Decoders: Row Decoder:-

 A most straightforward implementation of this decoder

is another NOR array, consisting of 4 rows (outputs)
and 4 columns (two address bits and their
complements).

Now assume that we select the memory cell by raising its word line voltage to logic
"1," hence, the pass transistors M3 and M4 are turned on. Once the memory cell is
selected, four basic operations may be performed on this cell.

a) Write "1" operation: The voltage level of column C is forced

to logic-low by the data-write circuitry. The driver transistor MI
turns off. The voltage V, attains a logic-high level, while V goes
low.
b) Read "1" operation: The voltage of column C retains its precharge level while the voltage of column C is pulled down by M2
and M4. The data-read circuitry detects the small voltage
difference (V > VZc)and amplifies it as a logic "1" data output.
c) Write "0" operation: The voltage level of column C is forced to
logic-low by the data-write circuitry. The driver transistor M2
turns off. The voltage V2 attains a logic-high level, while V goes
low.

 Column Decoder:A straightforward but costly approach would be to

connect an nMOS pass transistor to each bit-line
(column) output, and to selectively drive one out of 2M
pass transistors by using a NOR-based column address
decoder.

Static Random Access Memory

(SRAM)
Read-write (R/W) memory circuits are designed to
permit the modification (writing) of data bits to be
stored in the memory array, as well as their retrieval
(reading) on demand.
The memory circuit is said to be static if the stored
data can be retained indefinitely (as long as a sufficient
power supply voltage is provided), without any need for
a periodic refresh operation.
The data storage cell, i.e., the 1-bit memory cell in
static RAM arrays, invariably consists of a simple latch
circuit with two stable operating points (states).

 Various configurations of the static RAM cell:-

(a) Symbolic representation of the two-inverter latch circuit with access switches. (b)
Generic circuit topology of the MOS static RAM cell. (c) Resistive-load SRAM cell. (d)
Depletion-load nMOS SRAM cell. (e) Full CMOS

 SRAM Operation Principles: a typical four-transistor resistive-load SRAM cell widely used in highdensity memory arrays, consisting of a pair of cross-coupled inverters.
The two stable operating points of this basic latch circuit are used to
store a one-bit piece of information; hence, this pair of cross-coupled
inverters make up the central component of the SRAM cell.

To perform read and write operations, we use two nMOS pass

transistors, both of which are driven by the row select signal, RS.
Note that the SRAM cells is accessed via two bit lines or columns,
instead of one.

This complementary column arrangement allows for a more reliable

operation.

 Basic structure of the resistive-load SRAM cell, shown with the

column pull-up
transistors:-

Now assume that we select the memory cell by raising its word
line voltage to logic
"1," hence, the pass transistors M3 and M4 are turned on. Once
the memory cell is
selected, four basic operations may be performed on this cell.
Read "0" operation:
The voltage of column C retains its precharge level, while the voltage of column C is pulled down by M1
and M3. The data-read circuitry detects the small voltage
difference and amplifies it as a logic "0" data output.
Write "0" operation: The voltage level of column C is forced to
logic-low by the data-write circuitry. The driver transistor M2 turnsoff. The voltage V2 attains a logic-high level, while V1 goes low.
Read "1" operation:
The voltage of column C retains its precharge level, while the voltage of column C is pulled down by M2
and M4. The data-read circuitry detects the small voltage
difference (V > Vc) and amplifies it as a logic "1" data output.

Write "1" operation:

The voltage level of column C is
forced to logic-low by the data-write circuitry. The driver
transistor M1 turns- off. The voltage V1, attains a logichigh level, while V2 goes low.

Full CMOS SRAM Cell :

A low-power SRAM cell may be designed simply by using cross

coupled CMOS inverters instead of the resistive-load nMOS
inverters.
In this case, the stand-by power consumption of the memory cell
will be limited to the relatively small leakage currents of both
CMOS inverters.
The possible drawback of using CMOS SRAM cells, on the other
hand, is that the cell area tends to increase in order to
accommodate the n-well for the pMOS transistors and the poly-

 CMOS SRAM cell:-

 The most important advantage of this circuit topology is

that the static power dissipation is even smaller; essentially,
it is limited by the leakage current of the pMOS transistors.
A CMOS memory cell thus draws current from the power
supply only during a switching transition.
The low standby power consumption has certainly been a
driving force for the increasing prominence of high- density
CMOS SRAMs.
Other advantages of CMOS SRAM cells include high noise
immunity due to larger noise margins, and the ability to
operate at lower power supply voltages than, for example,
the resistive-load SRAM cells.

 Layouts of different type of SRAM cells:-

(a) Layout of the resistive-load SRAM cell.

b) Layout of the CMOS SRAM cell. (c) Layout of a 4-bit x 4-bit

SRAM array, consisting of 16 CMOS SRAM cells.

Read 0 Operation in SRAM:-

Assuming that a logic "0" is stored in the cell.

M2 and M5 are turned off, while the transistors M1 and M6

operate in the linear mode.

The internal node voltages are V1 = 0 and V2 = VDD before

the cell access (or pass) transistors M3 and M4 are turned on.

Read 0 Operation in SRAM: After the pass transistors M3 and M4 are turned on by the row
selection (RS) circuitry, the voltage level of column C will not
show any significant variation since no current will flow through
M4.
However, M3 and M1 will conduct a nonzero current and the
voltage level of column C will begin to drop slightly.
Note that the column capacitance Cc is typically very large;
therefore, the amount of decrease in the column voltage is limited
to a few hundred mV during the read phase.
While M1 and M3 are slowly discharging the column capacitance,
the node voltage V1, will increase from its initial value of 0 V.

Read 0 Operation in SRAM: Especially if the (W/L) ratio of the access transistor M3 is large
compared to the (W/L) ratio of M1, the node voltage V1 may exceed
the threshold voltage of M2 during this process, forcing an
unintended change of the stored state.
The key design issue for the data-read operation is then to
guarantee that the voltage V1, does not exceed the threshold
voltage of M2, so that the transistor M2 remains turned off during
the read phase, i.e.,
We can assume that after the access transistors, M3 & M4 are
turned on, the column voltage Vc remains approximately equal to
VDD.

Read 0 Operation in SRAM: Hence, M3 operates in saturation while M1 operates in

the linear region.

To summarize:
The transistor M2 will remain in cut-off during the read
"0" operation if above condition is satisfied. A
symmetrical condition also dictates the aspect ratios of
M2 and M4.

Write 0 Operation in SRAM: Assuming that Logic 1 is stored

in the SRAM cell initially.
M1 and M6 are turned off.
M2 and M5 operate in Linear
mode.
V1=VDD and V2=0V before the cell
access pass transistors M3 and
M4 are turned on.
The column voltage Vc is forced
to logic 0 level by the data-write
circuitry and assumed that Vc=0V.

Write 0 Operation in SRAM: Once the pass transistors M3 and M4 are turned on by the row
selection circuitry, we expect that the node voltage V2 remains
below the threshold voltage of M1, since M2 and M4 are
designed accordingly.
Consequently, the voltage level at node (2) would not be
sufficient to turn on M1.
To change the stored information, i.e., to force V1 to 0 V and V2
to VDD, the node voltage V1, must be reduced below the
threshold voltage of M2, so that M2 turns off first.
Similarly M2 will turn off when V1 is reduced below the inversion
threshold.

Write 0 Operation in SRAM: When V = VT,n, the transistor M3 operates in the linear region while M5
operates in saturation.

To summarize:
The transistor M2 will be forced into cut-off mode during the write "0"
operation if above condition is satisfied. This will guarantee that M1
subsequently turns on, changing the stored information.
Note that a symmetrical condition also dictates the aspect ratios of M6 and
M4.

 SRAM write circuitry:-

 Fast Sense Amplifier:-

 The cross-coupled sense amplifier does not

generate an output voltage level which
corresponds to the polarity of the voltage
difference between the two bit lines, but it rather
amplifies the small voltage difference already
existing between the bit lines.
This voltage difference must still be translated into
a logic level, by using a buffer stage.
In most SRAM arrays, the cross-coupled sense
amplifier circuit is used in conjunction with the
differential sense amplifier.
In this case, the cross-coupled amplifier serves as
a front-end structure to amplify the small voltage
difference between the two bit lines, whereas the

 Complete static SRAM cell:-

 CMOS dual-port SRAM cell:-

 The ideal dual-port SRAM allows simultaneous access to the same

location in the memory array, by using two independent sets of bit
lines and associated access switches for each memory cell.
Here, "word line 1" is used to access one set of complementary bit
lines (bit line 1), while "word line 2" allows access to the other set of
bit lines (bit line 2). The capability of simultaneous access
eliminates wait states for the processors during "data read"
operations.
However, contention may still occur if both external processors
accessing the same memory location simultaneously attempt to
write data onto the accessed cell, or if one of the processors
attempts to read data while the other processor writes data onto the
same cell.
In most cases, overlapping operations to the same memory location
can be eliminated by a contention arbitration logic. It can either
allow contention to be ignored and both operations to proceed, or it
can arbitrate and delay one port until the operation on the other

10.4. Dynamic Read-Write Memory

(DRAM) Circuits: In a dynamic RAM cell, binary data is stored simply as
charge in a capacitor, where the presence or absence of
stored charge determines the value of the stored bit.
Note that the data stored as charge in a capacitor
cannot be retained indefinitely, because the leakage
currents eventually remove or modify the stored charge.
Thus, all dynamic memory cells require a periodic
refreshing of the stored data, so that unwanted
modifications due to leakage are prevented before they
occur.

 Various configurations of the dynamic RAM

cell:

(a) Four-transistor DRAM cell with two storage nodes. (b) Three-transistor DRAM cell
with two bit lines and two word lines. (c) Two-transistor DRAM cell with one bit line and
one word line. (d)ne-transistor DRAM cell with one bit line and one word line.

 Three-Transistor DRAM Cell:-

The four pre-charge cycles are numbered 1,3,5, and 7,

respectively. The pre-charge cycle is effectively completed when
both capacitances C2 and C3 voltages reach their steady-state
values.

 Write operation: For the write "1" operation, the inverse data input is at the logic-low level,
because the data to be written onto the DRAM cell is logic "1. Now, the "write
select" signal WS is pulled high. As a result, the write access transistor Ml is
turned on. With M1 conducting, the charge on C2 is now shared with C1.

Since the capacitance C2 is very large compared to C1, the storage node
capacitance C1 attains approximately the same logic-high level as the column
capacitance C2 at the end of the charge-sharing process.

 Read operation: After the write "1" operation is completed, the write access
transistor MI is turned off. With the storage capacitance C
charged-up to a logic-high level, transistor M2 is now conducting.

 In order to read this stored "1," the "read select" signal RS must
be pulled high following a pre-charge cycle.
As the read access transistor M3 turns on, M2 and M3 create a
conducting path between the "data read column capacitance
C3 and the ground.
The capacitance C3 discharges through M2 and M3, and the
falling column voltage is interpreted by the "data read" circuitry
as a stored logic "1."
The active portion of the DRAM cell during the read "1" cycle.
Note that the 3-T DRAM cell may be read repeatedly in this
fashion without disturbing the charge stored in C.

 One-Transistor DRAM Cell: Similar to the 3-T DRAM cell, binary data are stored as the
presence or absence of charge in the storage capacitor. Capacitor
C2 represents the much larger parasitic column capacitance
associated with the word line.

The "data write" operation on the 1-T cell is quite straightforward.

For the write "1"operation, the bit line (D) is raised to logic " 1 "
by the write circuitry, while the selected word line is pulled high
by the row address decoder. The access transistor Ml turns on,
allowing the storage capacitor C to charge up to a logic-high level.

 Read operation: The "data read" operation on the one-transistor DRAM cell is
by necessity a "destructive readout. The read operation
starts with pre-charging the column capacitance C.
The word line is pulled high in order to activate the access
transistor Ml. Charge sharing between C and C occurs and,
depending on the amount of stored charge on C, the
column voltage either increases or decreases slightly.
Note that charge sharing inevitably destroys the stored
charge on C. Hence, we also have to refresh data every
time we perform a "data read" operation.

THE END