Clocking Strategies
Clocking Strategies
Clocking Strategies
Today’s handouts:
(1) Lecture Slides
JMM v1.2
Sequential Logic
Use #1: Get better utilization from
idle combinational logic blocks.
Pipeline the system so that new
computations start before the old ones
complete. Add registers to keep
computations separate.
8
A
8 Use #2: Convert parallel operations
x C
B to a sequence of (faster, smaller)
8 serial operations.
1
A
1
+ C
B
8 8
JMM v1.2
Latches and Flip-Flops
Q follows D
D Q D
G G
Q
level sensitive latch
Q stable
D Q D
clk clk
Q
edge sensitive flip-flop
Q stable
JMM v1.2
Latch Timing Constraints #1
latch a latch b
D Q CLa D Q CLb D Q
G G G
CLK
t1a
t2b
H S
CLK H S
Do I have to
check ALL these t1a = tmqa+ tmda > thb
constraints?
t1b = tmqb + tmdb > tha
t2a = tqa + tda < tc0 - tsb
t2b = tqb + tdb < tc1 - tsa
th = hold time
ts = setup time
tm = min delay from invalid input to invalid output
td = max delay from valid input to valid output for comb. logic
tq = max delay from G to Q
JMM v1.2
Latch Timing Constraints #2
t1a
t2b
H S
CLK H S
JMM v1.2
Static Latches
Basic idea: Want storage node to
be isolated from whatever
Need gain around user does to Q.
this loop to make 0
latch static.
Q
D 1
Would like fast CLK-to-Q,
small setup and zero hold
times.
CLK
Oops… feedback not
Obvious implementation: isolated from Q. Could
add additional
output inverters...
D D
CLKN
CLK CLK
Should we buffer CLK
0, 1 or 2 times?
JMM v1.2
Latch Timing
1 2
CLK
JMM v1.2
Dynamic Latches
Suppose in the interest of speed we were
willing to give up the “static guarantee”
and take our chances with dynamic latches,
i.e., remove feedback path...
Eliminate when
Q fanout is small (1)
D Q
Can combine
other logic
with inverter
CLK local or global
clock inverter?
CLKN
D Q
D Q
CLK
CLK
JMM v1.2
Single-Phase Clocked Systems
RTL #1:
D Q D Q D Q
CLK
latch #2:
D Q D Q D Q
G G G
CLK
clk
MicroLab, VLSI-10 (9/21)
JMM v1.2
Clock Skew
D Q D Q D Q
CLK delay
D Q D Q
clk clk
delay CLK
MicroLab, VLSI-10 (10/21)
JMM v1.2
Two-Phase Clocked Systems
D Q D Q D Q
G G G
PHI1
PHI2
phi1
“non-overlapping
two phase clocks” phi2
≥1 phi2
JMM v1.2
Clock Distribution
Two main techniques for clock distribution exist:
u a single large buffer (see Alpha processor)
n-bit datapath
n-bit datapath
n-bit datapath
n-bit datapath
n-bit datapath
n-bit datapath delays have
n-bit datapath to match
clk n-bit datapath between
n-bit datapath stages
n-bit datapath
n-bit datapath
n-bit datapath
clk
JMM v1.2
Phase Locked Loop Clock Technique
Phase locked loops (PLL) are used to generate
internal clocks on chips for two main reasons:
u to synchronize the internal clock of a chip with an
external clock
u to operate the internal clock at a higher rate than
the external clock input
clock clock
PLL
clock clock
route route
dclk dclk
dclk+dpad dclk+dpad
clock clock
dclk dclk
JMM v1.2
Flip-flops (registers)
Using alternating positive and negative dynamic latches with
a single clock gives great speed and small area, but…
w lots of worries about clock skew
w must balance logic delays to minimize wastage
w need latch size checks (check optimizations!)
D D Q D Q Q D D Q Q
master slave
G G CLK
CLK
D
CLK
Q
!
MicroLab, VLSI-10 (14/21)
JMM v1.2
Flip-flop Implementations
Obvious implementation:
Q
D
CLK
D Q
CLK
JMM v1.2
Flip-Flop Timing
D Q CLa D Q
clk clk
CLK
t1
t2
CLK
JMM v1.2
Dynamic Flip-Flops
I’ll have the Christer Svensson
special please!
2
CLK QN
CLK is low:
w node 1 follows not(D)
w node 2 pulled up
w QN is “floating” with it’s old value
CLK is high:
w node 2 = “0” if node 1 = “1”,
otherwise it stays “1”
ð node 2 = not(node 1) shortly after CLKé
w QN = not(node 2) ð stable soon after CLKé
w node 1 can be pulled down if D goes to “0” (capacitive
coupling), but node 2 won’t change!
MicroLab, VLSI-10 (17/21)
JMM v1.2
Static Timing Analysis
Do I have to Yup, for every pair of connected
check ALL the register/latches AND for all
constraints? possible data values!
JMM v1.2
Stage Delay Computation
Look at each gate and use knowledge of input timing and rise/fall
timing to compute earliest and latest time output could change for
both rising and falling output transitions.
IN VDD
D é ð OUT ê
C1 COUT
2
CLKN min ð 1=OV, fast
IN OUT max ð 1=VDD, slow
CLK
1 IN GND
D ê ð OUT é
C2 COUT
Other transitions:
CLK é, CLK ê, CLKN é, CLKN ê min ð 2= VDD , fast
max ð 2=0V, slow
JMM v1.2
Coming Up...
Next topic…
Finite state machines: state diagrams, state
minimization, state assignment, logic and PLA
implementations.
Selfstudy…
Weste:
u PLL section 9.3.5.3
JMM v1.2
Exercises: VLSI-10
JMM v1.2